NANO-CMOS CIRCUIT AND PHYSICAL DESIGN potx

[...]... noise, and waveform integrity analysis are discussed In the last part of the chapter we investigate physical and circuit design solutions to improve signal integrity in high-speed signaling Chapter 9 provides a comprehensive overview of existing PREFACE xvii design- and run-time low-power design techniques on different levels of a system design, with a focus on circuit- level logic and memory design. .. challenges of 157-nm and extreme UV (EUV) lithography are monumental and will increase tooling and mask costs and fabrication turnaround time If 157-nm lithography is not brought online by the 65-nm technology node, we will see the subwavelength gap widen further Circuit and physical designers can no longer design simply by technology design rules and expect a functional, let alone a scalable design that also... integration complexities and fabrication and process control difficulties We will suggest techniques that circuit and physical designers can employ to mitigate the challenges of working with sub-100-nm technologies, and provide some understanding of the process technology with which they are designing Similarly, it is important for process engineers to understand the basis of physical design so that the technology... CHALLENGES 1.6 17 NEW BREED OF CIRCUIT AND PHYSICAL DESIGN ENGINEERS CMOS technology scaling is at a point where traditional assumptions that allowed total decoupling between circuit and physical design from process development are falling apart This therefore demands a paradigm shift in the way we implement circuits [20] Even the Application-Specific Integrated Circuit (ASIC) design methodology, which pushes... if the design is to be functional and scalable beyond the 100-nm drawn feature sizes High-performance design, in particular, will require significantly different approaches This demands a new breed of circuit and physical design engineers who understand the difficulties so that they can be a part of the solution by creating lithographically friendly physical design to enable a robust, scalable, and high-yielding... impact on the fabrication yield of the final product Other layout styles may mitigate dopant fluctuation and poly-CD variation in circuits where device matching is important for circuit functionality The new breed of circuit and physical designers must understand the proximity effects on circuits and design circuits accordingly, so that silicon behavior is as predicted during simulations Proximity effects... section of six chapters describing design issues, with special attention paid to the interactions between technology and design, such as signal integrity and interconnects as well as practical solutions The third and final section addresses the impact of design on yield or design for manufacturability This book is for both IC designers and technologists who want a convenient and up-to-date reference written... robust and high-performance circuits despite process variation The chapter begins with a discussion of the sources of process and other variations, and their impact on circuit functionality and performance Three principal design areas (clocks, SRAM, and selected digital circuits) were chosen as case studies to illustrate these principles The chapter also includes some guidelines for a DFM-friendly design. .. on circuit design and physical implementation In the final part we cover issues concerning manufacturability and yield and provide guidance to ensure that a part is manufacturable and meets the yield and performance targets Chapter 1 provides an overview of the issues designers face in the deepsubmicron processes This chapter provides a framework for the rest of the book Part I contains Chapters 2 and. .. design goals, such as high performance and low-power mobile applications from a single mask set Designers must know when to use more relaxed rules and not simply relax the rules on the entire design, which negates physical scaling Combinations of materials and processes used to fabricate new structures create integration complexities that require design and layout solutions [20] Process engineers and .