báo cáo môn học thiết kế số sử dụng vhdl project design i2c controller core

WISHBONE interfacewb_rst_i 1 Input Synchronous reset, active higharst_i 1 Input Asynchronous resetwb_adr_i 3 Input Lower address bitswb_dat_i 8 Input Data towards the corewb_dat_o 8 Outp

ĐẠI HỌC BÁCH KHOA HÀ NỘI

TRƯỜNG ĐIỆN – ĐIỆN TỬ

Báo cáo môn học

Thiết kế số sử dụng VHDL

GVHD: TS Võ Lê Cường

Nhóm thực hiện: Nhóm 8

Đỗ Nhật Hoàng – 20193219

Nguyễn Việt Anh – 20193203

Nguyễn Tuấn Hải – 20193215

I INTRODUCTION

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method

of data exchange between devices It is most suitable for applications requiring occasional communication over a short distance between many devices The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus

simultaneously.

The interface defines 3 transmission speeds:

- Normal: 100Kbps

- Fast: 400Kbps

- High speed: 3.5Mbps

Only 100Kbps and 400Kbps modes are supported directly For High speed special IOs are needed If these IOs are available and used, then High speed is also supported.

II SPECIFICATIONS

1 I2C bus standard

· Multi Master Operation

· Software programmable clock frequency

· Clock Stretching and Wait state generation

· Interrupt or bit-polling driven byte-by-byte data-transfers

· Arbitration lost interrupt, with automatic transfer cancelation

· Bus busy detection

· Supports 7-bit and 10-bit addressing mode

· Static synchronous design

· Only 100Kbps and 400Kbps modes are supported directly

· Fully synthesizable

2 Wishbone bus.

- All output signals are registered

- Two-cycle access time

- A non-WISHBONE compatible signal, arst_i, is an asynchronous reset signal provided for FPGA implementations

3 Functional.

4 Pin.

WISHBONE interface

wb_rst_i 1 Input Synchronous reset, active high

arst_i 1 Input Asynchronous reset

wb_adr_i 3 Input Lower address bits

wb_dat_i 8 Input Data towards the core

wb_dat_o 8 Output Data from the core

wb_we_i 1 Input Write enable input

wb_stb_i 1 Input Strobe signal/Core select input

wb_cyc_i 1 Input Valid bus cycle input

wb_ack_o 1 Output Bus cycle acknowledge output

wb_inta_o 1 Output Interrupt signal output

I2C interface

scl_pad_i 1 Input Serial Clock line input

scl_pad_o 1 Output Serial Clock line output

scl_pad_oe 1 Output Serial Clock line output enable

sda_pad_i 1 Input Serial Data line input

sda_pad_o 1 Output Serial Data line output

sda_pad_oe 1 Output Serial Data line output enable

5 Module design.

The I2C core is built around four primary blocks; the Clock Generator, the Byte Command Controller, the Bit Command Controller and the DataIO Shift Register

All other blocks are used for interfacing or for storing temporary values

• Top-level module (i2c_master_top.v)

-> In addition to connecting all the functional blocks together, this module generates byte-wide data, acknowledgement, and interrupt for the WISHBONE interface

• Internal Registers

-> A 2-bit by 8-bit register space

-> Below is the Internal Register List in module

PRERlo 0x00 8 RW Clock Prescale register lo-byte

PRERhi 0x01 8 RW Clock Prescale register hi-byte

SCL SDA

Prescale Register

clock generator

Command Register

Status Register

Byte Command Controller

Bit Command Controller

WISHBONE

Interface

Transmit Register Receive Register

DataIO Shift Register

Fig 5.1 Internal structure I2C Master Core

CTR 0x02 8 RW Control register

TXR 0x03 8 W Transmit register

RXR 0x03 8 R Receive register

CR 0x04 8 W Command register

SR 0x04 8 R Status register

Prescale Register

This register is used to prescale the SCL clock line Due to the structure of the I C interface, the core uses 2

a 5*SCL clock internally The prescale register must be programmed to this 5*SCL frequency (minus 1) Change the value of the prescale register only when the ‘EN’ bit is cleared

Example: wb_clk_i = 32MHz, desired SCL = 100KHz

Reset value: 0xFFFF

Control register

Bit # Access Description

7 RW EN, I C core enable bit.2

When set to ‘1’, the core is enabled

When set to ‘0’, the core is disabled

6 RW IEN, I C core interrupt enable bit.2

When set to ‘1’, interrupt is enabled

When set to ‘0’, interrupt is disabled

Reset Value: 0x00

The core responds to new commands only when the ‘EN’ bit is set Pending commands are finished Clear the ‘EN’ bit only when no transfer is in progress, i.e after a STOP command, or when the command register has the STO bit set When halted during a transfer, the core can hang the I C bus.2

Transmit register

Bit # Access Description

7:1 W Next byte to transmit via I2C

0 W In case of a data transfer this bit represent the data’s LSB

In case of a slave address transfer this bit represents the RW bit

‘1’ = reading from slave

‘0’ = writing to slave

Reset value: 0x00

Receive register

Bit # Access Description

7:0 R Last byte received via I2C

Reset value: 0x00

Command register

Bit # Access Description

7 W STA, generate (repeated) start condition

6 W STO, generate stop condition

5 W RD, read from slave

4 W WR, write to slave

3 W ACK, when a receiver, sent ACK (ACK = ‘0’) or NACK (ACK = ‘1’)

Reset Value: 0x00

The STA, STO, RD, WR, and IACK bits are cleared automatically These bits are always read as zeros

Status register

Bit # Access Description

7 R RxACK, Received acknowledge from slave

This flag represents acknowledge from the addressed slave

‘1’ = No acknowledge received

‘0’ = Acknowledge received

‘1’ after START signal detected

‘0’ after STOP signal detected

This bit is set when the core lost arbitration Arbitration is lost when:

a STOP signal is detected, but non requested The master drives SDA high, but SDA is low

See bus-arbitration section for more information

1 R TIP, Transfer in progress

‘1’ when transferring data

‘0’ when transfer complete

0 R IF, Interrupt Flag This bit is set when an interrupt is pending, which will

cause a processor interrupt request if the IEN bit is set

The Interrupt Flag is set when:

one byte transfer has been completed arbitration is lost

Reset Value: 0x00

All reserved bits are read as zeros To ensure forward compatibility, they should be written as zeros

Byte Command Controller Module (i2c_master_byte_ctrl.v)

- This module directly controls the I2C bus, scl and sda lines, by generating the correct sequences for START, STOP, repeated START, READ, and WRITE commands

- Each bit operation is divided into five clock cycles (states) (idle, A, B, C, and D), except for the START command that has six clock cycles This ensures that the logical relationship between the scl and sda lines meets the I2C requirement for these critical commands The internal clock running at 5 x scl frequency is used for the registers in this module

- The microcontroller issues commands and data through the WISHBONE interface in byte format The information is fed into the Byte Command Controller module and is translated into I2C sequences required for a byte transfer

- This module includes a state machine, as shown below, to handle normal I2C sequences The module then breaks up a single command into multiple clock cycles for the Bit Command Controller to work on bitlevel I2C operations

- This module also contains a shift register which is used for both READ and WRITE cycle

- During a READ cycle, the input to the shift register comes from the sda line After eight scl cycles, the shifted-in data is copied into the Receive Register During a WRITE cycle, the input to the shift register comes from the WISHBONE data bus The data in the shift register is shifted out

to the sda line during WRITE

- Table of the Pin descriptions of module:

Name Input/Output Description

clk Input Master clock

rst Input Synchronous active high reset nReset Input Asynchronous active low reset ena Input Core enable signal clk_cnt Input Clock prescale value start Input Control input

stop Input Control input

read Input Control input

write Input Control input

ack_in Input Control input

din Input Control input (data in [7:0]) scl_i Input I2c signal clock line input sda_i Input I2c data line input cmd_ack Output Command acknowledge ack_out Output Acknowledge output i2c_busy Output I2c bus busy

i2c_al Output I2c arbitration lost dout Output Data out

scl_o Output I2c signal clock line output scl_oen Output I2c clock line output enable sda_o Output I2c data line output sda_oen Output I2c data line output enable

- The internal register and wire used to connect to other module of module:

Name Type Description

core_cmd Register Core command (bit controller) core_txd Register Core transfer data (bit controller) core_rxd Register Core receive data (bit controller)

sr Register 8 bit shift register

shift Register Signal for shift register

ld Register Signal for shift register dcnt Register Data count

c_state Register State

core_ack Wire Core acknowledge (bit controller)

go Wire Signal for state machine cnt_done Wire Signal for state machine, count done

I2C Byte Command control State Machine:

No

Idle state

Read /

Write

bit set ?

Yes

START

bit set ?

Yes START signal state

No

START

generat

ed ?

No

Yes

Read

bit set ?

Yes READ state

Byte

Read ?

No

Yes ACK state

WRITE state

Byte Written

?

No

Yes No

ACK bit Read Written

No Yes

I2C Byte command control FSM

I2C Byte command control ASM

Bit Command Controller Module (i2c_master_bit_ctrl.v)

-This module directly controls the I2C bus, scl and sda lines, by generating the correct sequences for START, STOP, repeated START, READ, and WRITE commands

-Each bit operation is divided into five clock cycles (states) (idle, A, B, C, and D), except for the START command that has six clock cycles This ensures that the logical relationship between the scl and sda lines meets the I2C requirement for these critical commands The internal clock running at 5 x scl frequency is used for the registers in this module

I2C Bit Command Illustration:

Figure: Bit command controller illustration

Figure: Bit command controller I2C of a temperature sensor

Figure: Bit command controller simulation on Proteus

Pin description of this module:

clk Input System clock rst Input Synchronous active high reset nReset Input Asynchronous active low reset ena Input Core enable signal clk_cnt Input Clock prescale value cmd Input Command from byte controller cmd_ack Output Command completes

acknowledge busy Output I2c bus busy

al Output I2c bus busy

dout Output Data out scl_i Input I2c clock line input scl_o Output I2c clock line output scl_oen Output I2c clock line output enable

(active low) sda_i Input I2c data line input sda_o Output I2c data line output sda_o Output I2c data line output enable

(active low)

Inertial Register of this module:

cSDA Capture SCL

cSDA Capture SDA

fSCL Filtered and synchronized SCL inputs fSDA Filtered and synchronized SDA inputs dSCL Delayed version of sSCL dSDA Delayed version of sSDA dscl_oen Delayed scl_oen

sda_chk Check SDA output

clk_en Clock generation signals slave_wait Slave inserts wait states cnt Clock divider counter

filter_cnt Clock divider for filter

FSM for I2C bit command control:

ASM for I2C bit command control:

III, Design I2C Master Core with interface.

1 Master Registers:

2 Byte Command Controller:

3 Bit Command Controller:

4 Master Wishbone Top Module:

IV Verify the design:

1 Testbench:

2.Waveform.

V, Conclusions.

Through this project, we have learnt the operation of I2C master core, how to implement the interface of I2C master core with Wishbone bus, Phillips I2C bus and its applications in real life This information would be a huge package for our career

VI, Reference.

1 Implementation of I2C master bus controller on FPGA

2 Github

3 I2C-Whishbone Master Compatible

4 Wishbone Master Controller