Digital System Design II Pipelined 128 points FFTIFFT

HA NOI UNIVERSITY OF SCIENCE AND TECHNOLOGY ELECTRICAL AND ELECTRONICS ENGINEERING  Digital System Design II Pipelined 128 points FFT/IFFT Instructor: Nguyen Duc Minh Class: ET-E4 K63 Team: 11 Member 1: Le Bao Ngoc -20182930 Member 2: Vu Minh Nhat-20182931 Member 2: Vu Minh Duct-20182911 TABLE OF CONTENTS I)Overview of our project II)Specification III)FFT-128 Algorithm IV)ASMD and block diagram of FFT-128 V)Implement Algorithm on C++ VI)Implentation And Result VII)Acknowledgement I)Overview of our project 1)Introduction In our electronics and telecommunications industry, spectrum analysis such as energy spectrum, amplitude spectrum, phase spectrum of signals in general and spectrum of digital signals in particular in the frequency domain plays a very important role It tells us how the frequency components contribute to the signal, how their energy is, how to use energy effectively… From that we have a way to handle that signal appropriately The problem is how to transform the digital signal from the time domain to the frequency domain to observe its spectrum The simplest answer is to use the Discrete Fourier Transform (DFT) Discrete Fourier transform is used in many fields, it is used in speech processing, image processing, It would not be an exaggeration to say that anything related to digital signal processing requires Fourier transforms However, the use of discrete Fourier transform has a problem, that is, the computation is relatively complicated when the data length to be calculated increases But as we know an image file, or any signal, is usually quite long, so if you just calculate the DFT normally, the execution time will be very long and complicated, so it won't satisfied time requirements Although the DFT machine produces good products, but the speed is too slow, the manufacturer will certainly not be satisfied at all That is why the fast Fourier transform (FFT) algorithm Transform) was created 2)Overview of FFT The idea of the FFT algorithm is the divide-and-conquer technique Instead of calculating the DFT for an entire signal with a large length, we will perform a DFT calculation for each smaller signal segment in that signal and then from the obtained result we calculate the DFT of the original signal to be calculated first FFT has a very important role: - FFT has improved the speed and accuracy of digital signal processing - FFT opens up a very wide field of spectrum analysis: telecommunications, astronomy, geophysics management, medical diagnosis,… - The FFT has rekindled the interests of many branches of mathematics that were previously fully exploited - FFT has laid the foundation for computing other transformations such as Walsh transform,Hamadard transform, Haar transform,… => Idea: Center’s goal is a FFT algorithm/architecture with the programmability necessary to meet the variety of functional FFT demands of future wireless and other signal processing applications So, our project of the FFT128 core architecture to explain its proper use FFT128 soft core is the unit to perform the Fast Fourier Transform (FFT) It performs one dimensional 128 – complex point FFT The data and coefficient widths are adjustable in the range to 16 II)Specification 1)Interface: The FFT128 processor has the minimum multiplier number which is equal to This fact makes this core attractive to implement in ASIC When configuring in Xilinx FPGA, these multipliers are implemented in DSP48 units respectively The customer can select the input data, output data, and coefficient widths which provide application dynamic range needs This can minimize both logic hardware and memory volume *Signal Description: Signal CLK RST start n[6:0] DR[15:0] DI[15:0] fft_ready shift[3:0] DOR[19:0] DIR[19:0] k[6:0] Output_ready OVF1 OVF2 Type Input Input Input Input Input Input Input Input Output Output Output Output Output Output Description Global clock Global reset FFT Start Address of input data Input data real sample Input data imaginary sample Input data accepting fft ready Shift left code Output data real sample Output data imaginary sample Result number or address Output data of FFT ready Overflag of output data real Overflag of output imaginary real *Note: input and output data are represented by 16 and 20 bit twos complement complex integers, respectively The twiddle coefficients are 16bit wide numbers 2)Typical core interconnection Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT The core interconnection depends on the application nature where it is used The simple core interconnection considers the calculation of the unlimited data stream which are inputted in each clock cycle The data source, for example, the analog-to-digital converter, FFT128 is the core, which is customized as one with inner data buffers The FFT algorithm starts with the impulse START The respective results are outputted after the READY impulse and followed by the address code ADDR The signal START is needed for the global synchronization, and can be generated once before the system operation The input data have the natural order, and can be numbered from to 63 When inner data buffers are configured then the output data have the natural order When inner data buffers are configured then the output data have the 8-th inverse order, the order is 0,8,16, 56,1,9,17, III)FFT-128 Algorithm 1)Basic of FFT algorithm *From the radix2 FFT, we now have other bases like radix 4, radix 8, along with various types of FFT calculation constructs such as parallelism, SDF(single delay feedback), MDC (multipath delay commutator), in-place (in-place),floods, increasingly affirm the important role of FFT Here we only study the DIF frequency division FFT Let x[n] be a sequence of length N The discrete Fourier transform DFT of x[n] is calculated according to the following formula: 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From formula (2),we can have: Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT 11111 0101100111 11110 0001101100 b[14][7] = -194484.47+41739.19i 11111 1111111111 11110 0100011000 b[15][0] = 549304.00+485144.00i 11111 1111111111 11111 1111111111 b[15][1] = -99656.21+45452.12i 11111 1000010101 11110 0110001100 b[15][2] = 768856.00+454880.00i 11111 1111111111 11111 1111111111 b[15][3] = -42461.36+12117.91i 11110 0100101111 11100 0111101011 b[15][4] = 76824.00+434080.03i 11111 0010110000 11111 1111111111 b[15][5] = 312264.66+-10280.56i 11111 1111111111 11100 0100000101 b[15][6] = 396856.00+947416.00i 11111 1111111111 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Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT 11111 1111111111 b[15][7] = 248540.66+-19685.41i 11111 1111111111 11101 0011001110 VI)Implentation And Result 1)Main Verilog code for pipelined FFT-128(each module’s code in main modue of FFT-128 will be attach with my report) Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT 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Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT Post-implementation after utilization The following table illustrates the performance of the FFT128 core with two data buffers based on BlockRAMs in Xilinx Virtex device when implementing 128point FFT for 10 and 16-bit data and coefficients Note that DSP48 units in all projects are used The results are derived using the Xilinx ISE 9.1 tool VII)Acknowledgement - Find out about the company structure, the positions that graduates can apply later recruit - Improve soft skills such as teamwork, planning, time division time, communication - Orientation to jobs after graduation, improve basic knowledge department, specializing in electronics - See the shortcomings and limitations of your own knowledge and skills to can be replenished in a timely manner - Applying knowledge learned in class and self-finding knowledge solve the problem - Learn more useful knowledge such as programming MatLab, C++, Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT Verilog language - A preliminary understanding of the hardware verification process in IC design Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT Digital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFTDigital.System.Design.II.Pipelined.128.points.FFTIFFT