DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS 2 nd Edition FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: Digital Timing Measurements – From Scopes and Probes to Timing and Jitter Maichen, W., Vol. 33 ISBN 0-387-32418-0 Fault-Tolerance Techniques for SRAM-based FPGAs Kastensmidt, F.L., Carro, L. (et al.), Vol. 32 ISBN 0-387-31068-1 Data Mining and Diagnosing IC Fails Huisman, L.M., Vol. 31 ISBN 0-387-24993-1 Fault Diagnosis of Analog Integrated Circuits Kabisatpathy, P., Barua, A. (et al.), Vol. 30 ISBN 0-387-25742-X Introduction to Advanced System-on-Chip Test Design and Optimi Larsson, E., Vol. 29 ISBN: 1-4020-3207-2 Embedded Processor-Based Self-Test Gizopoulos, D. (et al.), Vol. 28 ISBN: 1-4020-2785-0 Advances in Electronic Testing Gizopoulos, D. (et al.), Vol. 27 ISBN: 0-387-29408-2 Testing Static Random Access Memories Hamdioui, S., Vol. 26 ISBN: 1-4020-7752-1 Verification by Error Modeling Redecka, K. and Zilic, Vol. 25 ISBN: 1-4020-7652-5 Elements of STIL: Principles and Applications of IEEE Std. 1450 Maston, G., Taylor, T. (et al.), Vol. 24 ISBN: 1-4020-7637-1 Fault injection Techniques and Tools for Embedded systems Reliability… Benso, A., Prinetto, P. (Eds.), Vol. 23 ISBN: 1-4020-7589-8 Power-Constrained Testing of VLSI Circuits Nicolici, N., Al-Hashimi, B.M., Vol. 22B ISBN: 1-4020-7235-X High Performance Memory Memory Testing Adams, R. Dean, Vol. 22A ISBN: 1-4020-7255-4 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation Chakrabarty, K. (Ed.), Vol. 21 ISBN: 1-4020-7205-8 Test Resource Partitioning for System-on-a-Chip Chakrabarty, K., Iyengar & Chandra (et al.), Vol. 20 ISBN: 1-4020-7119-1 A Designers’ Guide to Built-in Self-Test Stroud, C., Vol. 19 ISBN: 1-4020-7050-0 Boundary-Scan Interconnect Diagnosis de Sousa, J., Cheung, P.Y.K., Vol. 18 ISBN: 0-7923-7314-6 by DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS Manoj Sachdev University of Waterloo Ontario, Canada José Pineda de Gyvez Philips Research Laboratories, and Eindhoven University of Technology Eindhoven, The Netherlands and 2 nd Edition A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN-10 0-387-46546-4 (HB) ISBN-13 978-0-387-46546-3 (HB) ISBN-10 0-387-46547-2 (e-book) ISBN-13 978-0-387-46547-0 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com Printed on acid-free paper All Rights Reserved © 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Dedication “To Santosh and Baldev Sachdev; Savitri and Dharm Bir Sawhney” Manoj Sachdev “To my teachers Jochen Jess and Edgar Sánchez-Sinencio for their invaluable knowledge” José Pineda de Gyvez vii Contents Dedication v Preface xiii Foreword xvii Foreword for the First Edition xix Acknowledgements xxi Chapter 1. Introduction 1 1. Evolution of CMOS Technology 1 2. The Test Complexity 5 3. Quality and Reliability Awareness 9 4. Building Quality and Reliability 11 5. Objectives of this Book 15 6. Book Organization 16 Chapter 2. Functional and Parametric Defect Models 23 1. Brief Classification of Defects 23 1.1 Defect-Fault Relationship 26 viii Defect-oriented Testing for Nano-metric CMOS VLSI Circuits 2. Inductive Fault Analysis 28 2.1 IC Design and Layout Related Defect Sensitivity 29 2.2 Defect Sensitive Design 29 2.3 Basic Concepts of IFA 30 3. Parametric Defect and Fault Models 32 3.1 Threshold Voltage Mismatch (ΔV t ) Fault Modeling 32 3.2 Sources of Threshold Voltage Variability 33 3.3 Leakage Current due to V t Mismatch 34 3.4 Delay in Parallel-connected Networks 39 3.5 Delay Variation Model with ΔV t for Parallel Transistor Networks 41 3.6 Spot Defect Statistics: Resistive Opens 45 4. Functional Defect Models 50 4.1 Critical Areas 53 4.2 Defect Statistics 54 4.3 Average Probability of Failure of Long Interconnects 58 4.4 Average Critical Area of N Conductors 61 5. Conclusions 64 Chapter 3. Digital CMOS Fault Modeling 69 1. Objectives of Fault Modeling 69 2. Levels of Testing 71 3. Levels of Fault Modeling 73 3.1 Logic Level Fault Modeling 73 3.2 Transistor Level Fault Modeling 81 3.3 Layout Level Fault Modeling 90 3.4 Function Level Fault Modeling 91 3.5 Delay Fault Models 92 3.6 Leakage Fault Model 97 3.7 Temporary Faults 98 4. Conclusions 102 Chapter 4. Defects in Logic Circuits and their Test Implications 111 1. Introduction 111 Contents ix 2. Stuck-at Faults and Manufacturing Defects 113 2.1 Study by Galiay, Crouzet and Vergniault 114 2.2 Study by Banerjee and Abraham 115 2.3 Study by Maly, Ferguson and Shen 120 2.4 Gate Oxide Shorts: Study by Hawkins and Soden 123 3. IFA Experiments on Standard Cells 126 4. I DDQ versus Voltage Testing 130 5. Defects in Sequential Circuits 133 5.1 Undetected Defects 135 5.2 Defect Detection Technique 137 5.3 I DDQ Testable Flip-flop 139 5.4 Defects and Scan Chains 139 6. Defect Classes and their Testing 143 7. Application of IFA in Nano-metric Technologies 143 8. Conclusions 146 Chapter 5. Testing Defects and Parametric Variations in RAMs 151 1. Introduction 151 2. Traditional RAM Fault Models 153 2.1 Stuck-at Fault Model 153 2.2 Coupling Fault Model 154 2.3 Pattern Sensitivity Fault Model 154 3. Defect Based RAM Fault Model Development 155 3.1 Defect based SRAM Fault Models and Test Algorithms 155 3.2 Subsequent Defect-oriented SRAM Test Development 160 3.3 Defect based DRAM Fault Models and Test Algorithms 163 3.4 TCAM Fault Models and Test Algorithms 176 4. Address Decoder Defects 185 4.1 Early Work on Address Decoder Faults 187 4.2 Technological Differences 187 x Defect-oriented Testing for Nano-metric CMOS VLSI Circuits 4.3 Failure and Analysis 189 4.4 Why Non-detection by March Tests? 192 4.5 Address Decoder Open Defects 193 4.6 Supplementary Test Algorithm 195 4.7 Testability Techniques for Decoder Open Defects 197 4.8 Recent Work on Address Decoder Defects 200 5. Parametric Testing of SRAMs 200 5.1 SRAM Cell and SNM 203 5.2 Process Variation and SNM 207 5.3 Manufacturing Defects and SNM 209 5.4 Weak Cell Fault Model 210 5.5 DfT Techniques to Detect Weak Cells 211 6. I DDQ Based RAM Testing 215 7. Conclusions 215 Chapter 6. Defect-oriented Analog Testing 225 1. Introduction 226 2. Analog Test Complexity 227 3. Previous Work 228 3.1 Estimation Method 228 3.2 Topological Method 228 3.3 Taxonomical Method 230 4. Defect Based Realistic Fault Dictionary 230 4.1 Implementation 234 5. A Case Study 240 5.1 Fault Matrix Generation 240 5.2 Stimuli Matrix 242 5.3 Simulation Results 243 5.4 Silicon Results 244 5.5 Observations and Analysis 248 5.6 IFA: Strengths and Weaknesses 249 6. Input Stimuli Generation 251 6.1 Power Supply Ramp Input Test Stimuli 252 6.2 Amplifier Specs 254 Contents xi 6.3 Structural vs. Functional Fault Coverage 259 6.4 Experimental Results 264 7. IFA Based Fault Grading and DfT for Analog Circuits 268 7.1 A/D Converter Testing 268 7.2 Description of the Experiment 269 7.3 Fault Simulation Issues 270 7.4 Fault Simulation Results 272 8. High Level Analog Fault Models 278 9. Conclusions 281 Chapter 7. Yield Engineering 289 1. Mathematical Models for Yield Prediction 289 1.1 Layout Oriented Yield Prediction 300 2. Yield Engineering 301 3. Economics and Yield Forecasting 306 4. Conclusions 312 Chapter 8. Conclusion 317 1. Test and Yield Engineering Complexity in Nano-metric Technologies 317 2. Role of Defect-oriented Testing 320 2.1 Strengths of Defect-oriented Testing 320 2.2 Limitations of Defect-oriented Testing 321 3. Future Directions 321 Index 325 [...]... techniques, such as a power supply ramp testing method, have been added 5 A new chapter on yield engineering is added xvii xviii Defect-oriented Testing for Nano-metric CMOS VLSI Circuits This edition will be useful to those who work or plan to work in the area of VLSI testing, namely, practicing engineers and students I thank the authors for their timely effort I must, however, remind them that technology... verification and testing could have detected this error very early in the design phase for a fraction of the cost [38] ICs for the automotive branch are just another example of the need for quality and reliability with preferably zero ppm levels DfT strategies have 10 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits an important role to play in reducing high costs associated with testing and debugging... root to Frank Wanlass He invented the concept of CMOS logic in 1963 [52] and called it nanowatt logic [53] However, CMOS technology did not gain popularity until the late 1970s Since then, CMOS has been the technology of choice for a vast majority of applications owing to its relatively simple, inexpensive 1 2 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits manufacturing process, integration... Defect-oriented Testing for Nano-metric CMOS VLSI Circuits expected to face numerous challenges in their quest to improve quality, reliability and yield of contemporary integrated circuits Some of these challenges are mentioned below, and described through the book For economic reasons, test simplification is needed for SoC VLSI circuits It is not unusual that an analog test engineer spends 20% of his/her efforts... research papers and company reports xix xx Defect-oriented Testing for Nano-metric CMOS VLSI Circuits A strength of this book is its breadth Types of designs considered include analog and digital circuits, programmable logic arrays, and memories Having a fault model does not automatically provide a test Sometimes, design for testability hardware is necessary Many design for testability ideas, supported by... design, manufacturing, and test is called design for yield (DfY) A design and its layout are implemented to be insensitive to the most common manufacturing defects for a given process Similarly, the testing strategies are devised to catch the likely defects Critical area analyses (CAA) of layouts help to find 14 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits areas where faults are likely to... parameters, while others such as threshold voltage (Vt) cannot be scaled by the same factor Therefore, voltage should be scaled less aggressively by a factor g (where g > 1) GSS offers the performance benefits of CFS or CVS while its power dissipation is in between CFS and CVS 4 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits It appears that the industry is now in a deep sub-micron regime, and a number... test a single IC The test becomes even longer if the IC contains sequential logic Moreover, exhaustive testing may not be enough to detect defective parts if the faulty behavior becomes sequential In this case, newer test methods 6 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits such as delay testing as well as stressing conditions including temperature and low power supply voltage are needed... to ensure the quality of the tested devices while maintaining the economics of the production In other words, testing of RAMs in an efficient, reliable, and cost effective manner is becoming an increasingly challenging task [29] 8 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits For example, a study of DRAMs identified the test cost, along with process complexity, die size, and equipment... of defect-oriented testing The target audience of this book consists of design and test professionals However, this book may also be used as a reference book for graduate level courses on VLSI testing, or on VLSI quality and reliability Our motivation to write the second edition comes from two diverse sources Firstly, the field of defectoriented testing is more than two decades old However, the information . following people of Philips Research. Guido Gronthoud for his continuous support and encouragement on various topics such as analog testing, and process-aware testing. Rodger Schuttert for providing. applications owing to its relatively simple, inexpensive 2 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits manufacturing process, integration capability, and extremely small power. techniques, such as a power supply ramp testing method, have been added. 5. A new chapter on yield engineering is added. xviii Defect-oriented Testing for Nano-metric CMOS VLSI Circuits This