Three phase scvd based boost inverter with low common mode voltage for transformerless photovoltaic grid connected system doctor of philosophy major electrical engineering

Doctoral Dissertation A Three-Phase SCVD Based Boost Inverter with Low Common Mode Voltage for Transformerless Photovoltaic Grid-Connected System Department of Electrical Engineering Graduate School, Chonnam National University Tran Tan Tai August 2020 A Three-Phase SCVD Based Boost Inverter with Low Common Mode Voltage for Transformerless Photovoltaic Grid-Connected System Department of Electrical Engineering Graduate School of Chonnam National University Tran Tan Tai Supervised by Professor Joon-Ho Choi A dissertation submitted in partial fulfillment of the requirements for the Doctor of Philosophy in Electrical Engineering Committee in Charge: Prof Young-Cheol Lim Prof In-Seon Yeo Assit Prof Dong-Hee Kim Dr Minh-Khai Nguyen Prof Joon-Ho Choi August 2020 Contents Contents i List of Figures iii List of Tables vii List of Abbreviations viii Abstract ix Chapter Introduction 1.1 Research Background 1.1.1 Modulation-Based Methods 1.1.2 Topology-Based Methods 11 1.2 Research Focus 15 1.3 Research Contributions 15 1.4 Organization of the Dissertation 16 Chapter Proposed Three-Phase SCVD Based Boost Inverter 18 2.1 Introduction 18 2.2 Proposed Topology 19 2.2.1 Common-Mode Leakage Current Model 19 2.2.2 Operation Principles 21 2.3 SVM Control Techniques for Proposed Topology 27 2.3.1 DPWM technique for Proposed Topology 27 2.3.2 Zero-Even PWM (ZEPWM) Technique for Proposed Topology 29 2.3.3 Near State PWM (NSPWM) Technique for Proposed Topology 31 2.4 Summary 31 Chapter Modified Three-Phase SCVD Based Boost Inverter with Constant Common-Mode Voltage for Photovoltaic Application 34 3.1 Introduction 34 i 3.2 Proposed Topology 34 3.3 PWM Control Strategy for Introduced Topology 41 3.4 Comparison Between the Proposed Inverters and Existing Topologies 42 Chapter Simulation and Experimental Verifications 45 4.1 Three-Phase SCVD Based Boost Inverter 45 4.1.1 Simulation Verifications 45 4.1.2 Experimental Verifications 58 4.2 Modified Three-Phase SCVD Based Boost Inverter 71 4.2.1 Simulation Verifications 71 4.2.2 Experimental Verifications 75 Chapter Conclusions 81 References 82 Abstract by Korean 91 Acknowledgement 92 ii List of Figures Fig 1.1 Conventional VSIs topology (a) Equivalent circuit; (b) Voltage vectors in the conventional VSIs Fig 1.2 CM model of conventional VSIs topology Fig 1.3 Voltage vectors and the area definition (a) Type A areas (b) Type B areas Fig 1.4 Demonstration of the voltage vectors and the reference vector for ASZPWM1 in area A1 Fig 1.5 Demonstration of the voltage vectors and the reference vector for NSPWM in area B2 Fig 1.6 Demonstration of the voltage vectors and the reference vector for RSPWM3 in area B1 Fig 1.7 Four-leg topology for transformerless PV systems 10 Fig 1.8 Transformerless H7 grid-connected inverter topology 11 Fig 1.9 Transformerless voltage-clamping topology 12 Fig 1.10 Transformerless H-8 grid-connected inverter topologies (a) type in [67]; (b) type in [69] 13 Fig 1.11 Three-phase zero-voltage state rectifier topology for operating transformerless photovoltaic (PV) systems 14 Fig 2.1 Proposed three-phase SCVD based boost inverter 18 Fig 2.2 Common-mode model of introduced three-phase SCVD based boost inverter (a) Simplified common-mode model and (b) Simplified equivalent 19 Fig 2.3 Configuration of the introduced SCVD based boost inverter for state and state (a) State (000) and (b) State (100) 23 Fig 2.4 Configuration of the introduced SCVD based boost inverter for state and state (a) State (110) and (b) State (010) 24 Fig 2.5 Configuration of the introduced SCVD based boost inverter for state and iii state (a) State (011) and (b) State (001) 25 Fig 2.6 Configuration of the introduced SCVD based boost inverter for state and state (a) State (101); (b) State (111) 26 Fig 2.7 DPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three phase inverter; (b) Switching pattern in sector 1; (c) CMV of the conventional VSIs compared to the introduced SCVD based boost inverter under DPWM technique 28 Fig 2.8 ZEPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three phase inverter; (b) Switching pattern and CMV of introduced SCVD based boost inverter in sector 30 Fig 2.9 NSPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three phase inverter; (b) Switching pattern and CMV of introduced SCVD based boost inverter in sector 32 Fig 3.1 Modified three-phase SCVD based boost inverter 35 Fig 3.2 Configuration of the introduced mSCVD based boost inverter for state and state (a) State (000) and (b) State (100) 36 Fig 3.3 Configuration of the introduced mSCVD based boost inverter for state and state (a) State (110) and (b) State (010) 37 Fig 3.4 Configuration of the introduced mSCVD based boost inverter for state and state (a) State (011) and (b) State (001) 38 Fig 3.5 Configuration of the introduced mSCVD based boost inverter for state and state (a) State (101); (b) State (111) 39 Fig 3.6 Block diagram of the PWM control generation module 42 Fig 4.1 Vg, VPN, VAB and load currents under DPWM technique 46 Fig 4.2 FFT of VAB and load current under DPWM technique 46 Fig 4.3 Vg, VPN, VAB and load currents under ZEPWM technique 47 Fig 4.4 FFT of VAB and load current under ZEPWM technique 47 iv Fig 4.5 Vg, VPN, VAB and load currents under NSPWM technique 48 Fig 4.6 FFT of VAB and load current under NSPWM technique 48 Fig 4.7 VCa, VCb, VDSa and VDSb under DPWM strategy 49 Fig 4.8 VCa, VCb, VDSa and VDSb under ZEPWM strategy 50 Fig 4.9 VCa, VCb, VDSa and VDSb under NSPWM strategy 51 Fig 4.10 Phase-A voltage and simulated CMV under DPWM technique 52 Fig 4.11 Phase-A voltage and simulated CMV under ZEPWM technique 53 Fig 4.12 Phase-A voltage and simulated CMV under NSPWM technique 54 Fig 4.13 FFT of simulated CMV (a) DPWM technique, (b) ZEPWM technique, and (c) NSPWM technique 55 Fig 4.14 Grid voltage, grid current and simulated CMC for the conventional VSIs with DPWM technique 56 Fig 4.15 Grid voltage, grid current and simulated CMC for the introduced SCVD based boost inverter with DPWM technique 56 Fig 4.16 Grid voltage, grid current and simulated CMC for introduced SCVD based boost inverter with NSPWM technique 57 Fig 4.17 Grid voltage, grid current and simulated CMC for introduced SCVD based boost inverter with ZEPWM technique 57 Fig 4.18 Prototype photo of the introduced SCVD based boost inverter 59 Fig 4.19 Vg, VPN, VAB and FFT of VAB under DPWM technique 60 Fig 4.20 Load currents and their FFT under DPWM technique 60 Fig 4.21 Vg, VPN, VAB and FFT of VAB under ZEPWM technique 61 Fig 4.22 Load currents and their FFT under ZEPWM technique 61 Fig 4.23 Vg, VPN, VAB and FFT of VAB under NSPWM technique 62 Fig 4.24 Load currents and their FFT under NSPWM technique 62 Fig 4.25 VCa, VCb, VDSa and VDSb under DPWM technique 64 Fig 4.26 VCa, VCb, VDSa and VDSb under ZEPWM technique 65 v Fig 4.27 VCa, VCb, VDSa and VDSb under NSPWM technique 66 Fig 4.28 Phase-A voltage and CMV under DPWM technique 67 Fig 4.29 Phase-A voltage and CMV under ZEPWM technique 68 Fig 4.30 Phase-A voltage and CMV under NSPWM technique 69 Fig 4.31 FFT of CMV under various PWM (a) DPWM, (b) ZEPWM, and (c) NSPWM 70 Fig 4.32 Vg, VPN, VAB and load currents of the introduced mSCVD based boost inverter 72 Fig 4.33 FFT of VAB and ia of the introduced mSCVD based boost inverter 72 Fig 4.34 Voltage across additional switches (a)-(b) From top to bottom: VDSa, VDSb, VDSc and VDSd 73 Fig 4.35 Waveforms capacitor voltage of introduced mSCVD based boost inverter From top to bottom: VCa, VCb and VCc 74 Fig 4.36 Phase-A voltage, simulated CMV, and simulated CMC of introduced mSCVD based boost inverter 74 Fig 4.37 Prototype photo of the introduced mSCVD based boost inverter 75 Fig 4.38 VPN, VAB and Vg of the introduced mSCVD based boost inverter 76 Fig 4.39 Load currents and their FFT of the introduced mSCVD based boost inverter 76 Fig 4.40 Experimental waveforms of additional switches From top to bottom: (a)-(b) VDSd, VDSc, VDSb, and VDSa 77 Fig 4.41 Experimental waveforms of capacitor voltages From top to bottom: VCa, VCb, and VCc 78 Fig 4.42 Phase-A voltage and CMV of the introduced mSCVD based boost inverter 78 Fig 4.43 Measured efficiency comparison between the SCVD based boost inverter with the mSCVD based boost inverter 79 vi List of Tables Table 1.1 The corresponding CMV value under eight switching states Table 2.1 State of each of common-mode voltage and semiconductor devices of proposed SCVD based boost inverter for different switching states 21 Table 3.1 State of each of common-mode voltage and semiconductor device of introduced mSCVD based boost inverter for different switching states 35 Table 3.2 Comparison of the introduced configurations and existing topologies for the same dc-bus voltage (VPN) 43 Table 4.1 Simulation and Experimental Parameters of introduced SCVD based boost inverter 45 Table 4.2 Simulation and Experimental Parameters of introduced mSCVD based boost inverter 71 vii List of Abbreviations PV photovoltaic VSIs voltage source inverters EMI electromagnetic interference EMC electromagnetic compatibility CM common-mode CMV common-mode voltage CMC common-mode current PWM pulse width modulation THD total harmonic distortion SVM space vector modulation SVPWM space vector PWM AZSPWM active zero-state PWM RSPWM remote state PWM NSPWM near state PWM ZEPWM Zero-Even PWM ZVR zero-voltage-state rectifier SCVD Switched-Capacitor-Voltage-Doubler mSCVD Modified Switched-Capacitor-Voltage-Doubler viii  V AO      V B O     VCO       V A O   V A O  V O O  V B O  V O O  V C O  V O O (2.1)  V BO   VCO   Where VAO, VBO, and VCO are the voltages between the inverter outputs and the PV negative terminal VAO’, VBO’, and VCO’ are the phase voltages respectively VO’O is the voltage between neutral of grid and the PV negative terminal From equation (2.1), the CMV (VCMV) of the introduced SCVD based boost inverter can be defined as follows: VCMV  VO O  V AO  VBO  VCO (2.2) Also, from Fig 2.1, we have the following mathematical equations:  V AO  V AN  V NO     V BO  V BN  V NO     V CO  V CN  V NO (2.3) From equation (2.2) and (2.3), the CMV (VCMV) of the introduced SCVD based boost inverter can be rewritten as follows: VCMV  VAN VBN VCN VNO (2.4) From Fig 2.2, we have the following mathematical equations: V P V  V A N  V N O  sI a L f  V ga     V P V  V B N  V N O  sI b L f  V gb     V P V  V C N  V N O  sI c L f  V gc    V ga  V gb  V gc        I a  I b  I c  I CM The CMC can be calculated as follows: iCM (t)  CPV dvPV (t) dt 20 (2.5) (2.6) From equation (2.4), (2.5), and (2.6), The stray capacitor voltage of VPV can be derived as follows: VPV (s)  VCMV (s)  s L f CPV (2.7) From (2.6), we can see that the CMC depends on both the stray capacitance and dVPV(t)/dt In practice, the value of the stray capacitance is small, e.g., 330 nF So, the CMC can be effectively reduced if the parasitic capacitor voltage is constant From (2.7), we can see that parasitic capacitor voltage is dependent on the CMV Therefore, the CMV is the main concern Table 2.1 STATE OF EACH OF COMMON-MODE VOLTAGE AND SEMICONDUCTOR DEVICES OF PROPOSED SCVD BASED BOOST INVERTER FOR DIFFERENT SWITCHING STATES Switch Diode VCMV State S1 S3 S5 Sa Sb Da Db State Off Off Off On Off Off On State On Off Off On Off Off On VPN/3 State On On Off Off On On Off VPN/6 State Off On Off On off Off On VPN/3 State Off On On Off On On Off VPN/6 State Off Off On On Off Off On VPN/3 State On Off On Off On On Off VPN/6 State On On On Off On On Off VPN/2 2.2.2 Operation Principles From Fig 2.1, typical voltage across diode Db (VNO) is expressed as follows VCb VNO   0 switch Sb is turned on (2.8) switch Sb is turned off From (2.4, and (2.8), the corresponding CMV and all the switching states of the introduced SCVD based boost inverter are shown in Table 2.1 21 Similar to the conventional VSIs, the introduced SCVD based boost inverter has also eight switching states as illustrated in Fig 2.3-Fig 2.6 The operating principle of the introduced SCVD based boost inverter can be explained as follows During state [see Fig 2.3 (a)]: switch Sa is on while switch Sb is off So, the diode Da is reverse-biased while diode Db is forward-biased The capacitor Cb is charged as well as the capacitor Ca is discharged The capacitor Cb voltage stands at input voltage, Vg During state 0, the CMV of the introduced SCVD based boost inverter is like that in the VSIs  VCb  V g     V C M      V P N  V C a  V C b (2.9) During state 1, state and state [see Fig 2.3(b), Fig 2.4(b), and Fig 2.5(b)]: switch Sa is on while switch Sb is off So, diode Da is reverse-biased while diode Db is forward-biased The capacitor Cb is charged while the capacitor Ca is discharged Capacitor Cb voltage stands at input voltage, Vg During these states, the CMV of the introduced SCVD based boost inverter is VPN/3 V C b  V g     V PN  V C M      V  VCa  VCb    PN (2.10) During state 2, state and state [see Fig 2.4(a), Fig 2.5(a), and Fig 2.6(a)]: switch Sa is off while switch Sb is on So, diode Db is reverse-biased while diode Da is forward-biased Capacitor Ca is charged while capacitor Cb is discharged Capacitor Ca voltage stands at input voltage, Vg During even active states, the corresponding CMV is VPN/6 22 Da P S1 Sa S5 S3 Ca A Cg B Vg PV Sb Cb C S4 S2 S6 Db N O (a) Da P S5 S3 S1 Sa Ca A Vg Cg B PV Cb Sb C S4 S2 S6 Db O O N (b) Fig 2.3 Configuration of the introduced SCVD based boost inverter for state and state (a) State (000) and (b) State (100)  VCa  V g     V PN  V C M      V  VCa  VCb    PN (2.11) During state [see Fig 2.6(b)]: switch Sa is off while switch Sb is on So, diode Da is 23 forward-biased while diode Db is reverse-biased Capacitor Ca is charged while capacitor Cb is discharged Capacitor Ca voltage stands at input voltage, Vg During this state, the corresponding CMV is VPN/2 Da P S1 Sa S3 S5 Ca A Cg B Vg PV Sb Cb C S4 S2 S6 Db N O (a) Da P S1 Sa S3 Ca A Cg B Vg PV Sb Cb C S2 S4 S6 Db N O (b) Fig 2.4 Configuration of the introduced SCVD based boost inverter for state and state (a) State (110) and (b) State (010) 24 Da P S3 S1 Sa S5 Ca A Cg B Vg PV Sb Cb C S2 S4 S6 S3 S5 Db N O (a) Da P S1 Sa Ca A Cg B Vg PV Sb Cb C S2 S4 S6 Db N O (b) Fig 2.5 Configuration of the introduced SCVD based boost inverter for state and state (a) State (011) and (b) State (001)  VCa  V g     V PN  V C M      V  VCa  VCb    PN (2.12) Therefore, the DC-bus voltage of the introduced SCVD based boost inverter is 25 Da P S1 Sa S3 S5 Ca A Cg B Vg PV Sb Cb C S4 S2 S6 Db N O (a) Da P S1 Sa S3 S5 Ca A Cg B Vg PV Sb Cb C S2 S4 S6 Db O O N (b) Fig 2.6 Configuration of the introduced SCVD based boost inverter for state and state (a) State (101); (b) State (111) VPN  VCa  VCb  2Vg (2.13) From above operating principles of the introduced SCVD based boost inverter, we can see that the CMV changes from VPN/6 to VPN/3 (16.6% of VPN) during active states Besides, the DC-bus voltage of the introduced SCVD based boost inverter is twice of that of the VSIs 26 for the same input DC voltage 2.3 SVM Control Techniques for Proposed Topology For the conventional VSIs, the traditional DPWM technique performs good efficacy in voltage linearity, DC-bus current ripple, switching losses, and THD of output currents However, the traditional DPWM technique performs bad common-mode voltage characteristics 2.3.1 DPWM Technique for Proposed Topology Fig 2.7 presents DPWM technique for the introduced SCVD based boost inverter As shown in Fig 2.7, the DPWM technique which only uses active states and one zero state (state 0) is applied into H-bridge circuit Besides, Sa is off as well as Sb is on in the time of even active states In the time of odd active states as shown in Fig 2.3(b), Fig 2.4(b), and Fig 2.5(b), Sa is on as well as Sb is off This ensures that the CMV only gets values of 0, VPN/6, or VPN/3 As indicated in Fig 2.7(c), CMV of the introduced SCVD based boost inverter under DPWM technique is significantly decreased The variation of common-mode voltage is VPN/3 like that in [65]–[69] Similar to the VSIs under DPWM technique, the introduced SCVD based boost inverter has major features such as low THD of output current, low switching losses, low DC-bus current ripple, and full modulation range (0 ≤ Mi ≤ 1) Besides, the introduced SCVD based boost inverter under DPWM technique has additional advantage of low variation in CMV 27 Section  V3 (010)  V2 (110) β Section Section  V0 (000)  V4 (011) θ  V1 (100)    V ref α Section Section   V5 (001) Section V6 (101) (a) S1 S3 S5 Sa Sb (b) Ts Conventional VSIs 2VPN /3 Proposed SCVD-BI VPN /3 VPN /6 Ts/2 (c) Ts Fig 2.7 DPWM technique for the introduced SCVD based boost inverter (a) Space vector in output of three-phase inverter; (b) Switching pattern in sector 1; (c) CMV of the conventional VSIs compared to the introduced SCVD based boost inverter under DPWM technique 28 2.3.2 Zero-Even PWM (ZEPWM) Technique for Proposed Topology Fig 2.8 highlights the ZEPWM technique for proposed the introduced SCVD based boost inverter The ZEPWM technique utilizes a group of one zero vector and two even active vectors to produce the output voltage vector as highlighted in Fig 2.8 (a) Besides, Sa is turned off as well as Sb is turned on in the time of even active states as shown in Fig 2.4(a), Fig 2.5(a), and Fig 2.6(a) During State as shown in Fig 2.3 (a), Sa is on as well as Sb is off This ensures that the CMV gets values of or VPN/6 As demonstrated in Fig 2.8 (b), the high frequency and amplitude of CMV of the introduced SCVD based boost inverter is significantly dropped The variation in CMV is VPN/6 In sector 1, the two active vectors ⃗ and ⃗ and a zero vector ⃗, are used to produce the reference vector ( ⃗ ) as shown in Fig 2.8(a) According to the volt-second balance principle, we have:     Vref Ts  V2T2 V6T6 V0T0 (2.14) where T0, T2 and T6 are time intervals of ⃗ , ⃗ and ⃗ , respectively Ts is the switching period The time intervals of ⃗, ⃗ and ⃗ can be calculated as: T2  Mi  Ts  sin(   / 3)  T6  Mi  Ts  cos(   / 6)  T0  Ts  3Mi  Ts  cos( ) (2.15) In sector 2, the two active vectors ⃗ and ⃗ and a zero vector ⃗, are used to produce the reference vector ( ⃗) as shown in Fig 28 (a) The time intervals of ⃗, ⃗ and ⃗ can be calculated as: T2  Mi  Ts  sin( )  T4  Mi  Ts  sin(   / 3)  T0  Ts  3Mi  Ts  cos(   / 3) (2.16) 29  V2 (110) Section  V0 (000)  V4 (011) Section Section  V6 (101) (a) S1 S3 S5 Sa Sb CMV VPN /6 0 VPN /6 (b) Ts Fig 2.8 ZEPWM technique for introduced SCVD based boost inverter (a) Space vector in output of three-phase inverter; (b) Switching pattern and CMV of the introduced SCVD based boost inverter in sector 30 In sector 3, the two active vectors ⃗ and ⃗ and a zero vector ⃗ are used to produce the reference vector ( ⃗) as shown in Fig 28 (a) The time intervals of ⃗, ⃗ and ⃗ can be calculated as: T6  Mi  Ts  cos(   / 2)  T4  Mi  Ts  cos(  5 / 6)  T0  Ts  3Mi  Ts  sin(   / 6) (2.17) The ZEPWM technique performs only linearly at low modulation index (Mi < 0.57) 2.3.3 Near State PWM (NSPWM) Technique for Proposed Topology Fig 2.9 presents the NSPWM technique for the introduced SCVD based boost inverter As indicated in Fig 2.9 (a), a set of three active vectors is utilized to produce the output vector Besides, during even active states as shown in Fig 2.4(a), Fig 2.5(a), and Fig 2.6(a), Sa is turned off as well as Sb is on During odd active states as presented in Fig 2.3(b), Fig 2.4(b), and Fig 2.5(b), Sa is on as well as Sb is off So, the common-mode voltage takes values of VPN/3 or VPN/6 As indicated in Fig 2.9 (b), CMV of the introduced SCVD based boost inverter is significantly dropped The variation of CMV is VPN/6 Like the NSPWM technique [32]-[33] for conventional VSIs, the NSPWM technique for the introduced SCVD based boost inverter performs only linearly at high modulation index (Mi > 0.66) 2.4 Summary This chapter has discussed three-phase SCVD based boost inverter topology for CMV reduction By combining an SCVD network of the conventional three-phase H-bridge inverter, the DC-bus voltage of the introduced SCVD based boost inverter is twice of input voltage So, the output voltage peak of the introduced SCVD based boost inverter can be higher than the input voltage Like the past works, under DPWM technique, the amplitude of CMV of 31  V3 (010)  V2 (110) Section  V4 (011) Section Section Section Section  V1 (100) Section  V5 (001)  V6 (101) (a) S1 S3 S5 Sa Sb VPN /3 VPN /3 VPN /6 CMV (b) Ts Fig 2.9 NSPWM technique for the introduced SCVD based boost inverter (a) Space vector in output of three-phase inverter; (b) Switching pattern and CMV of the introduced SCVD based boost inverter in sector 32 the introduced SCVD based boost inverter is about VPN/3 The CMV of the introduced SCVD based boost inverter under DPWM technique varies from to VPN/3 Moreover, NSPWM technique can be utilized for higher modulation index Under NSPWM technique, the amplitude of CMV of the introduced SCVD based boost inverter is VPN/6 The CMV of the introduced SCVD based boost inverter under DPWM technique varies from VPN/6 to VPN/3 ZEPWM technique can be utilized for lower modulation index Like NSPWM technique, the amplitude of CMV of the introduced SCVD based boost inverter under ZEPWM technique is about 16.6% VPN The CMV of the introduced SCVD based boost inverter under DPWM technique varies from to VPN/6 33 Chapter Modified Three-Phase SCVD Based Boost Inverter with Constant Common-Mode Voltage for Photovoltaic Application 3.1 Introduction As discussed in Chapter 2, an SCVD network that consists of two capacitors, two activeswitches, and two power diodes is inserted at dc side of the conventional VSIs Therefore, the DC-bus voltage of the introduced SCVD based boost inverter is twice of input voltage Compared to the existing solutions, the variation in CMV of the introduced SCVD based boost inverter can be restricted within one-sixth of DC-bus voltage Besides, the voltage stress across extra diodes and switches stands at VPN/2 In this Chapter, a modified SCVD network is discussed to step up the DC-bus voltage to triple of input voltage instead of twice of input voltage as that in three-phase SCVD based boost inverter Besides, the CMV of the introduced configuration can be canceled through switching the four extra active-switches based on the Boolean logic function Compared to three-phase SCVD based boost inverter, CMV of the introduced configuration can be maintained as constant at V Moreover, the voltage stress across extra semiconductor devices is equal to VPN/3 3.2 Proposed Topology The modified SVCD based boost inverter, which is indicated in Fig 3.1, is combined of a modified SCVD (mSCVD) network and three-phase bridge circuit The mSCVD network which consists of three capacitors, four diodes, and four switches is inserted into between the three-phase bridge circuit and the dc input voltage source Like proposed three-phase SCVD based boost inverter as presented in chapter 2, the introduced mSCVD based boost inverter also has eight switching states as illustrated in Fig 3.2, Fig 3.3, Fig 3.4 and Fig 3.5 Table 3.1 highlights all the switching states and the CMV of the introduced mSCVD based boost inverter The operating principle of the introduced mSCVD based boost inverter can be explained as follows 34