PRINCIPLES OF I/O HARDWARE 5.2 PRINCIPLES OF I/O SOFTWARE 5.3 I/O SOFTWARE LAYERS 5.4 DISKS 5.5 CLOCKS 5.6 CHARACTER-ORIENTED TERMINALS 5.7 GRAPHICAL USER INTERFACES 5.8 NETWORK TERMINALS 5.9 POWER MANAGEMENT 5.10 RESEARCH ON INPUT/OUTPUT 5.11 SUMMARY
8 MULTIPLE PROCESSOR SYSTEMS 8.1 MULTIPROCESSORS 8.2 MULTICOMPUTERS 8.3 DISTRIBUTED SYSTEMS 8.4 RESEARCH ON MULTIPLE PROCESSOR SYSTEMS 8.5 SUMMARY C C C C C C C C M C C C C C Shared memory Inter- connect CPU Local memory (a) (b) (c) M C C M C M C M C C M C C M C M C C M M M M C+ M C+ M C+ M C+ M C+ M C+ M Complete system Internet Fig. 8-1. (a) A shared-memory multiprocessor. (b) A message- passing multicomputer. (c) A wide area distributed system. CPU CPU M Shared memory Shared memory Bus (a) CPU CPU M Private memory (b) CPU CPU M (c) Cache Fig. 8-2. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories. Memories CPUs Closed crosspoint switch Open crosspoint switch (a) (b) (c) Crosspoint switch is closed Crosspoint switch is open 000 001 010 011 100 101 110 111 100 101 110 111 000 001 010 011 Fig. 8-3. (a) An 8 × 8 crossbar switch. (b) An open crosspoint. (c) A closed crosspoint. A B X Y (a) (b) Module Address Opcode Value Fig. 8-4. (a) A 2 × 2 switch. (b) A message format. CPUs b b b b a aa a 3 Stages Memories 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 1A 1B 1C 1D 2A 2B 2C 2D 3A 3B 3C 3D Fig. 8-5. An omega switching network. Directory Node 0 Node 1 Node 255 (a) (b) Bits 8186 (c) Interconnection network CPU Memory Local bus CPU Memory Local bus CPU Memory Local bus Node Block Offset 0 1 2 3 4 0 0 1 0 0 2 18 -1 82 … Fig. 8-6. (a) A 256-node directory-based multiprocessor. (b) Divi- sion of a 32-bit memory address into fields. (c) The directory at node 36. Has private OS CPU 1 Has private OS CPU 2 Has private OS CPU 3 Has private OS CPU 4 Memory I/O 12 Data Data 34 Data Data OS code Bus Fig. 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. The boxes marked Data are the operating system’s private data for each CPU. Master runs OS CPU 1 Slave runs user processes CPU 2 Slave runs user processes CPU 3 User processes OS CPU 4 Memory I/O Bus Slave runs user processes Fig. 8-8. A master-slave multiprocessor model. Runs users and shared OS CPU 1 Runs users and shared OS CPU 2 Runs users and shared OS CPU 3 Runs users and shared OS OS CPU 4 Memory I/O Locks Bus Fig. 8-9. The SMP multiprocessor model. [...]... Machine 1 Machine 2 Machine 1 Machine 2 Machine 1 Machine 2 Application Application Application Application Application Application Run-time system Run-time system Run-time system Run-time system Run-time system Run-time system Operating system Operating system Operating system Operating system Operating system Operating system Hardware Hardware Hardware Hardware Hardware Hardware Shared memory Shared memory... 1 3 8 6 4 10 12 CPU 1 7 14 CPU 2 11 13 15 CPU 3 (c) Fig 8- 23 (a) Pages of the address space distributed among four machines (b) Situation after CPU 1 references page 10 (c) Situation if page 10 is read only and replication is used CPU 1 Shared page CPU 2 A B A B Code using variable A A and B are unrelated shared variables that just happen to be on the same page Code using variable B Network Fig 8- 24... CPU, RAM, net interface Shared exc maybe disk Same room Dedicated interconnect Multiple, same One, shared One organization Distributed System Complete computer Full set per node Possibly worldwide Traditional network Possibly all different Each node has own Many organizations Fig 8- 27 Comparison of three kinds of multiple CPU systems Common base for applications Application Application Application Application... elp Ya w h ed n Ne es k Ta (a) I’m bored (b) Fig 8- 26 (a) An overloaded node looking for a lightly loaded node to hand off processes to (b) An empty node looking for work to do ? Item Node configuration Node peripherals Location Internode communication Operating systems File systems Administration Multiprocessor CPU All shared Same rack Shared RAM One, shared One, shared One organization Multicomputer... (a) A single switch (b) A ring (c) A grid (d) A double torus (e) A cube (f) A 4D hypercube CPU 1 Input port Four-port switch Output port A Entire packet B A B A B C D C D C D CPU 2 Entire packet (a) (b) Fig 8- 17 Store -and- forward packet switching Entire packet (c) Node 1 CPU Node 2 Main RAM 1 User OS Main RAM CPU 3 2 4 5 Switch Main RAM Main RAM CPU CPU Node 3 Optional on- board CPU Interface board... Message Ethernet 1 header IP TCP Ethernet Headers Fig 8- 32 Accumulation of packet headers Message Uni versi of North South ty School of Humanities School of Sciences School of Social Sciences Science Northern University Social sciences Astronomy Biology Chemistry Physics Geography History Languages Main page Anthropology Psychology Sociology Main page Main page Geography Dept History Dept Languages... Router Home PC Local router Host Ethernet Fig 8- 30 A portion of the Internet Service Example Reliable message stream Remote login Digitized voice Unreliable datagram Network test packets Acknowledged datagram Registered mail Request-reply Connectionless Reliable byte stream Unreliable connection Connection-oriented Sequence of pages of a book Database query Fig 8- 31 Six different types of network service... Application Application Middleware Middleware Middleware Middleware Windows Linux Solaris Mac OS Pentium Pentium SPARC Macintosh Network Fig 8- 28 Positioning of middleware in a distributed system Computer Computer Switch Ethernet Ethernet (a) (b) Fig 8- 29 (a) Classic Ethernet (b) Switched Ethernet Backbone Regional network Mediumbandwidth fiber High-bandwidth fiber Router at ISP Dial-up line to home... K L I M N (c) Fig 8- 12 Using a single data structure for scheduling a multiprocessor 8- CPU partition 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 6-CPU partition 1 25 26 27 28 29 30 31 Unassigned CPU 4-CPU partition 12-CPU partition Fig 8- 13 A set of 32 CPUs split into four partitions, with two CPUs available Thread A0 running CPU 0 A0 B0 A0 B0 Time 0 A1 100 B1 A1 Reply 2 Reply 1... Request 1 CPU 1 A0 B1 200 A1 300 400 500 Fig 8- 14 Communication between two threads belonging to process A that are running out of phase 600 CPU 0 0 A0 1 A1 2 A2 3 A3 4 A4 5 A5 1 B0 B1 B2 C0 C1 C2 2 Time 3 slot 4 D0 D1 D2 D3 D4 E0 E1 E2 E3 E4 E5 E6 A0 A1 A2 A3 A4 A5 5 B0 B1 B2 C0 C1 C2 6 D0 D1 D2 D3 D4 E0 7 E1 E2 E3 E4 E5 E6 Fig 8- 15 Gang scheduling (a) (b) (c) (d) (e) (f) Fig 8- 16 Various interconnect . I/O 12 Data Data 34 Data Data OS code Bus Fig. 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. The boxes marked Data are the operating. 2 Main RAM Main RAM Node 4 Interface board Optional on- board CPU Interface board RAM Node 3 Main RAM Main RAM Node 1 3 2 1 4 5 User OS Fig. 8-18. Position of the network interface boards in a multicom- puter. Node. (a) An 8 × 8 crossbar switch. (b) An open crosspoint. (c) A closed crosspoint. A B X Y (a) (b) Module Address Opcode Value Fig. 8-4. (a) A 2 × 2 switch. (b) A message format. CPUs b b b b a aa a 3