vlsi design course lecture notes ch6

ECE 410, Prof. A. Mason Lecture Notes 6.1 Intrinsic Silicon Properties • Read textbook, section 3.2.1, 3.2.2, 3.2.3 • Intrinsic Semiconductors – undoped (i.e., not n+ or p+) silicon has intrinsic charge carriers – electron-hole pairs are created by thermal energy – intrinsic carrier concentration ≡ n i = 1.45x10 10 cm -3 , at room temp. – function of temperature: increase or decrease with temp? – n = p = n i , in intrinsic (undoped) material •n ≡ number of electrons, p ≡ number of holes – mass-action law, np = n i 2 • applies to undoped and doped material ECE 410, Prof. A. Mason Lecture Notes 6.2 Extrinsic Silicon Properties •doping, adding dopants to modify material properties – n-type = n+, add elements with extra an electron • (arsenic, As, or phosphorus, P), Group V elements •n n ≡ concentration of electrons in n-type material •n n = N d cm -3 , N d ≡ concentration of donor atoms •p n ≡ concentration of holes in n-type material •N d p n = n i 2 , using mass-action law – always a lot more n than p in n-type material – p-type = p+, add elements with an extra hole • (boron, B) •p p ≡ concentration of holes in p-type material •p p = N a cm -3 , N a ≡ concentration of acceptor atoms •n p ≡ concentration of electrons in p-type material •N a n p = n i 2 , using mass-action law – always a lot more p than n in p-type material –if both N d and N a present, n n = N d -N a , p p =N a -N d do example on board n i 2 = 2.1x10 20 n+/p+ defines region as heavily doped, typically ≈ 10 16 -10 18 cm -3 less highly doped regions generally labeled n/p (without the +) P P + + - group V element ion electro n n-type Donor free carrier B B + + - group III element hole p-type Acceptor ion free carrie r ECE 410, Prof. A. Mason Lecture Notes 6.3 Conduction in Semiconductors • doping provides free charge carriers, alters conductivity • conductivity, σ, in semic. w/ carrier densities n and p – σ = q(μ n n + μ p p), q ≡ electron charge, q = 1.6x10 -19 [Coulombs] • μ≡mobility [cm 2 /V-sec], μ n ≅ 1360, μ p ≅ 480 (typical values) • in n-type region, n n >> p n – σ≈qμ n n n • in p-type region, p p >> n p – σ≈qμ p n p • resistivity, ρ = 1/σ • resistance of an n+ or p+ region –R = ρ l , A = wt • drift current (flow of charge carriers in presence of an electric field, E x ) – n/p drift current density: Jxn = σ n E x = qμ n n n E x , Jxp = σ p E x = qμ p p p E x – total drift current density in x direction Jx = q(μ n n + μ p p) E x = σ E x mobility = average velocity per unit electric field μ n > μ p electrons more mobile than holes ⇒conductivity of n+ > p+ l t w A Mobility often assumed constant but is a function of Temperature and Doping Concentration ECE 410, Prof. A. Mason Lecture Notes 6.4 pn Junctions: Intro • What is a pn Junction? – interface of p-type and n-type semiconductor – junction of two materials forms a diode • In the Beginning… – ionization of dopants at material interface • Diffusion -movement of charge to regions of lower concentration – free carries diffuse out – leave behind immobile ions – region become depleted of free carriers – ions establish an electric field • acts against diffusion donor ion and electron free carrier acceptor ion and hole free carrier p-type hole diffusion hole current electron diffusion electron current N acceptors/cm A 3 N donors/cm D 3 n-type - + - + - + - + - + - + - + - + + - + - + - + - + - + - + - + - + - + - + - E depletion region immobile acceptor ions (negative-charge) immobile donor ions (positive-charge) electric field x p W x n - - - - - - - - + + + + + + + + p-type N acceptors/cm A 3 N donors/cm D 3 n-type p-type Si wafer pn diode junction depletion region boundaries dielectric insulato (oxide) contact to p-side contact to n-side p+ n+ n “well” r p-type n-type ECE 410, Prof. A. Mason Lecture Notes 6.5 pn Junctions: Equilibrium Conditions • Depletion Region – area at pn interface void of free charges – charge neutrality • must have equal charge on both sides •q A x p N A = q A x n N D , A=junction area; x p , x n depth into p/n side • ⇒ x p N A = x n N D • depletion region will extend further into the more lightly doped side of the junction • Built-in Potential – diffusion of carriers leaves behind immobile charged ions – ions create an electric field which generates a built-in potential •where V T = kT/q = 26mV at room temperature E depletion region immobile acceptor ions (negative-charge) immobile donor ions (positive-charge) electric field x p W x n - - - - - - - - + + + + + + + + p-type N acceptors/cm A 3 N donors/cm D 3 n-type N A N D ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =Ψ 2 0 ln i DA T n NN V ECE 410, Prof. A. Mason Lecture Notes 6.6 pn Junctions: Depletion Width • Depletion Width use Poisson’s equation & charge neutrality –W = x p + x n •where V R is applied reverse bias • One-sided Step Junction –if N A >>N D (p+n diode) • most of junction on n-side –if N D >>N A (n+p diode) • most of junction on p-side E depletion region immobile acceptor ions (negative-charge) immobile donor ions (positive-charge) electric field x p W x n - - - - - - - - + + + + + + + + p-type N acceptors/cm A 3 N donors/cm D 3 n-type N A N D ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =Ψ 2 0 ln i DA T n NN V () () 2 1 0 2 ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + +Ψ = ADA DR p NNqN NV x ε () () 2 1 0 2 ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + +Ψ = ADD AR n NNqN NV x ε () 2 1 0 2 ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + +Ψ = AD AD R NN NN q V W ε () 2 1 0 2 ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ +Ψ =≅ A R p qN V xW ε () 2 1 0 2 ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ +Ψ =≅ D R n qN V xW ε ε is the permittivity of Si ε = 1.04x10 -12 F/cm ε = K S ε 0 , where ε 0 = 8.85x10 -14 F/cm and K S = 11.8 is the relative permittivity of silicon ECE 410, Prof. A. Mason Lecture Notes 6.7 pn Junctions - Depletion Capacitance • Free carriers are separated by the depletion layer • Separation of charge creates junction capacitance –Cj = εA/d ⇒ (d = depletion width, W) – A is complex to calculate in semiconductor diodes • consists of both bottom of the well and side-wall areas – Cj is a strong function of biasing • must be re-calculated if bias conditions change – CMOS doping is not linear/constant • graded junction approximation • Junction Breakdown – if reverse bias is too high (typically > 30V) can get strong reverse current flow () ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ +Ψ ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + = R DA DA j V NN NNq AC 0 2 1 1 2 ε ε is the permittivity of Si ε = 11.8⋅ε 0 = 1.04x10 -12 F/cm V R = applied reverse bias ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ Ψ + = 0 1 R jo j V C C () 2 1 0 2 ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ +Ψ = DA DA jo NN NNq AC ε ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ Ψ + = 3 0 1 R jo j V C C ECE 410, Prof. A. Mason Lecture Notes 6.8 • Forward Bias; V D > Ψ 0 – acts against built-in potential – depletion width reduced – diffusion currents increase with V D • minority carrier diffusion • Reverse Bias; V R = -V D > 0 – acts to support built-in potential – depletion width increased – electric field increased – small drift current flows • considered leakage • small until V R is too high and breakdown occurs Diode Biasing and Current Flow + V - D V D V f + V - D I D I D I D p n ( ) 1−= TD VV SD eII ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ +∝ AD S NN AI 11 ECE 410, Prof. A. Mason Lecture Notes 6.9 MOSFET Capacitor • MOSFETs move charge from drain to source underneath the gate, if a conductive channel exists under the gate • Understanding how and why the conductive channel is produced is important • MOSFET capacitor models the gate/oxide/substrate region – source and drain are ignored – substrate changes with applied gate voltage •Consider an nMOS device – Accumulation, V G < 0, (-)ve charge on gate • induces (+)ve charge in substrate • (+)ve charge accumulate from substrate holes (h+) – Depletion, V G > 0 but small • creates depletion region in substrate • (-)ve charge but no free carriers – Inversion, V G > 0 but larger • further depletion requires high energy • (-)ve charge pulled from Ground • electron (e-) free carriers in channel Si substrate = bulk gate oxide G G S D B B gate channel = p-type Si substrate depletion layer depletion layer Accumulation Depletion Inversion p-type Si substrate p-type Si substrate V < 0 G V > 0 G V >> 0 G BB B + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ECE 410, Prof. A. Mason Lecture Notes 6.10 Capacitance in MOSFET Capacitor • In Accumulation – Gate capacitance = Oxide capacitance – Cox = ε ox /t ox [F/cm 2 ] • In Depletion – Gate capacitance has 2 components – 1) oxide capacitance – 2) depletion capacitance of the substrate depletion region •Cdep= ε si /x d , x d = depth of depletion region into substrate – Cgate = Cox (in series with) Cdep = Cox Cdep / (Cox+Cdep) < Cox • C’s in series add like R’s in parallel • In Inversion – free carries at the surface – Cgate = Cox Cgate V G Cox inversion depletion accumulation Cox Cdep [...]... Mason • Rn = 1/[βn(VDD-Vtn)] Lecture Notes 6.24 MOSFET Capacitances -Preview • Need to find CS and CD • MOSFET Small Signal model Gate vg Cgs Cgd + vgs - • • • • • • Cgs Cgd Cgb Cdb Csb no Csd! gmvgs gmbvsb is vs Source – Model Capacitances Cgb ro Drain v d id Cdb Csb Body (Bulk) • MOSFET Physical Capacitances – layer overlap – pn junction ECE 410, Prof A Mason Lecture Notes 6.25 RC Model Capacitances... switching speed • Important Notes – models developed for saturation (active) region – models presented are simplified (not detailed) • RC Model Capacitances – Source Capacitance • models capacitance at the Source node • CS = CGS + CSB – Drain Capacitance • models capacitance at the Drain node • CD = CGD + CDB What are CGS, CGD, CSB, and CDB? ECE 410, Prof A Mason Lecture Notes 6.26 MOSFET Parasitic... Capacitance • CS = CGS + CSB – Drain Capacitance • CD = CGD + CDB ECE 410, Prof A Mason Cgd + vgs - i s vs Source Cgb ro gmvgs gmbvsb Drain v d id Cdb Csb Body (Bulk) Lecture Notes 6.30 Junction Areas • Note: calculations assume following design rules – – – – poly size, L = 2λ poly space to contact, 2λ contact size, 2λ active overlap of contact, 1λ ⇒ W = 4λ X1 = 5λ, X2= 2λ, X3 = 6λ X1 • Non-shared Junction... drift or diffusion current? nMOS • MOSFET I-V Characteristics VDS = VGS - Vtn source @ ground ↑ VGS Charge Flow Current Flow ECE 410, Prof A Mason drain @ (+)ve potential Electron Flow Current Flow Lecture Notes 6.14 Channel Charge and Current • Threshold Voltage = Vtn, Vtp – amount of voltage required on the gate to turn tx on – gate voltage > Vtn/p will induce charge in the channel • nMOS Channel Charge... = Qc L CG = CoxWL ⇒| Qc |= CoxWL(VG − Vtn ) – I = μnCox (W/L) (VG-Vtn) VDS : linear model, assumes constant charge in channel similar analysis applies for pMOS, see textbook ECE 410, Prof A Mason Lecture Notes 6.15 Transconductance and Channel Resistance • nMOS Channel Charge: Qc = -CG(VG-Vtn) • nMOS linear model Channel Current: – I = μnCox(W/L)(VG-Vtn) VDS • assumes constant charge in channel, valid... – Rn = 1/( βn (VG-Vtn) ) • pMOS: k’p = μpCox, βp = μpCox (W/L) ECE 410, Prof A Mason similar analysis applies for pMOS, see textbook Rn = 1 W (VGS − Vtn ) L 1 Rp = W μ p Cox VSG − Vtp L μ nCox ( ) Lecture Notes 6.16 nMOS Current vs.Voltage • Cutoff Region General Integral for expressing ID • channel charge = f(y) • channel voltage = f(y) • y is direction from drain to source – VGS < Vtn ⇒ ID = 0 VD... near drain • assume channel charge varies linearly from drain to source – at source: Qe = -Cox (VGS-Vtn), at drain: Qe = 0 ⇒ ID = [2(V L μ n COX W 2 GS 2 − Vt )V DS − V DS ] ECE 410, Prof A Mason Lecture Notes 6.17 nMOS Current vs.Voltage • Saturation Region (Active Region) – VGS > Vtn, VDS > VGS-Vtn • surface potential at drain, φsd = VGS-Vtn-VDS • when VDS = VGS-Vtn, φsd = 0 ⇒ channel not inverted... current is saturated, no longer increases • substitute Vsat=VGS-Vtn for VDS into triode equation ID = μ n C OX W 2 L (VGS − Vt ) 2 ECE 410, Prof A Mason ID = [2(V L μ n COX W 2 GS 2 − Vt )V DS − V DS Lecture Notes 6.18 ] Other Stuff • Transconductance – process transconductance, k’ = μn Cox • constant for a given fabrication process – device transconductance, βn= k’ W/L • Surface Mobility – mobility at... under the gate • depletion spreading from drain-substrate junction L (drawn) S Leff = L(drawn) − 2 LD − X d ⎛ 2ε (V − (VG − Vt )) ⎞ ⎟ Xd = ⎜ s D ⎜ ⎟ qN A ⎝ ⎠ ECE 410, Prof A Mason D G xd LD ~xd Leff Lecture Notes 6.19 Second Order Effects • Channel Length Modulation – Square Law Equation predicts ID is constant with VDS – However, ID actually increases slightly with VDS • due to effective channel getting... are grounded if source not at ground, source-to-bulk voltage exists, VSB > 0 VSB > 0 will increase the threshold voltage, Vtn = f(VSB) called Body Effect, or Body-Bias Effect ECE 410, Prof A Mason Lecture Notes 6.20 pMOS Equations • Analysis of nMOS applies to pMOS with following modifications – physical • change all n-tpye regions to p-type • change all p-type regions to n-type – substrate is n-type . ECE 410, Prof. A. Mason Lecture Notes 6.1 Intrinsic Silicon Properties • Read textbook, section 3.2.1, 3.2.2, 3.2.3 • Intrinsic. mass-action law, np = n i 2 • applies to undoped and doped material ECE 410, Prof. A. Mason Lecture Notes 6.2 Extrinsic Silicon Properties •doping, adding dopants to modify material properties –. Donor free carrier B B + + - group III element hole p-type Acceptor ion free carrie r ECE 410, Prof. A. Mason Lecture Notes 6.3 Conduction in Semiconductors • doping provides free charge carriers, alters conductivity