Realization of synchronization of coupled multiple delay systems on FPGA platform

Realization of Synchronization of Coupled Multiple Delay Systems on FPGA Platform Viet-Thanh Pham, Mattia Frasca and Luigi Fortuna Tran Tuan Anh, Thang Manh Hoang Dipartimento di Ingegneria Elettrica Elettronica e Informatica Universita di Catania Catania, Italy Email: mfrasca@diees.unict.it School of Electronics and Telecommunications Hanoi University of Science and Technology Hanoi, Viet Nam Email: hmt@mail.hut.edu.vn Abstract—This paper presents the experimental synchronization of multiple time delay systems which are implemented on a Field Programmable Gate Array (FPGA) The obtained results verify the correctness and the feasibility of theoretical synchronization Moreover, the digital approach here could be applied to arbitrary multi–delay feedback systems to realize secure chaotic communication Index Terms—chaos synchronization; time delay systems; FPGA I I NTRODUCTION Model with a single constant time delay has attracted interest due to its importance in describing engineering system [1] as well as biological phenomena [2] With the presence of time delay, these systems become infinite–dimensional dynamical ones exhibited diverse strange behaviors, for example, chaos can occur even in one–dimensional continuous–time systems with delay [3] Developments of the mathematical theory of functional and delay differential equations (DDEs) provide us the essential tool for studying these models Recently, multiple delay system is also studied and its potential applications are presented in control, networking [4] and especially in secure chaotic communication [5] According to [5], a chaos-based secure communication system is proposed by using the projective–lag and/or projective anticipating synchronizations of coupled multidelay feedback systems associated with the synchronization–manifold shift keying (SMSK) technique The security of this kind of communication system is improved significantly because of the highly dimensional dynamics of driving system Thus, one practical problem in this field is chaos synchronization which refers to a process wherein two or many identical or non– identical chaotic systems adjust a given property of their motion to a common behaviour due to a coupling or to a periodical or noisy forcing [6] It has been investigated in [7], [8], [9], [10] by theoretical analysis and numerical simulations Moreover, synchronization also have been substantiated in coupled multiple time–delay external cavity semiconductor lasers [11] However, the experimental set–up is complicated and expensive due to the used optical devices such as lasers, beam splitters, mirrors or optical isolators As the result, the circuit–based multidelay system is required to investigate novel features more detail and confirm the theoretical results Fig General model of multiple delay feedback system (with two delays τ1 and τ2 ) Furthermore, the main motivation behind the interest in the circuit is directly potential applications in the enhanced security for communication systems In this work, to verify the feasibility of theory, a realization of synchronization in two– delay systems based on field programmable gate array (FPGA) is proposed The paper is organized as follows: in the next Section the model with two delay and diverse synchronization schemes are discussed; in Section the simulation and experimental results are presented Finally, the last Section summarizes the concluding remarks II M ODEL OF THE MULTIDELAY SYSTEM AND CHAOS SYNCHRONIZATION SCHEMES A Model of multiple delay system with two delays We consider one multiple delay feedback model with two time delays τ1 and τ2 as shown in Fig The model consists of two delay units, two nonlinear units, three multiplier, one adder and one digital integrator Nonlinear function f (.) has the following form f (x) = sin(x) On the other word, this model describes one modified Ikeda system [1] with the dynamical equation dx mi f (xτi ), = −αx + dt i=1 Fig Chaos synchronization in coupled multiple time delay systems using driving signal [5] where α, mi , τi ∈ ℜ and xτi = x (t − τi ) It has the practical meaning described the dynamics of an optical bi– stable resonator [1] where physically x(t) is the phase lag of the electric field across the resonator In addition, this model could be easily changed to display one arbitrary DDE with multiple delays defined as N dx = −αx + mi fi (xτi ), dt i=1 ax by added other delays and nonlinear units, e.g., f (x) = 1+x c for the Mackey–Glass model [12], odd piecewise linear function for the Lu model [3], f (x) = π b − sin2 (x − x0 ) for the Vallee model [13], or f (x) = −10.44x3 − 13.95x2 − 3.63x + 0.85 for the Voss model [14] etc B Chaos synchronization schemes in coupled multiple time delay systems Using the described model, we will verify experimentally the theoretical synchronization approaches proposed in the literature [5], [6] This part reviews the main ideas of these methods and presents the chosen parameters for next Sections The synchronization model of coupled multidelay systems is illustrated in Fig where the master system (MS) and slave system (SL) are coupled by the driving signal (DRV) Driving signal DRV (t) is the sum of multiple nonlinear components of delayed state variable Hence, the complexity degree of the driving signal is considerable complicated and could be changed through the number of nonlinear components and/or the value of delays and parameters 1) Scheme of complete synchronization: Complete synchronization [6] refers to the phenomenon in which the state of MS is equal to one of SL Master system, driving signal and slave system are constructed as MS: dx dt = −αx + mi f (xτi ), i=1 DRV: DRV (t) = SL: dy dt ki f (xτi ), i=1 = −αy + ni f (yτi ), i=1 where α, mi , ni , ki ∈ ℜ and τi ∈ ℜ+ By using Krasovskii-Lyapunov functional approach [9], [15], the synchronization occurs when choosing the parameters satisfied the following conditions   ni = mi − ki ,  α> |ni | |sup f ′ (xτi )| , i=1 where sup f ′ (.) denoting the supreme limit of f ′ (.) and f ′ (.) stands for the derivative of f (.) with respect to time The parameters are selected as α = 2.5, m1 = −13.5, m2 = −0.5, n1 = −2, n2 = −0.1, k1 = −11.5, k2 = −0.4, τ1 = 2.6 and τ2 = 0.5 2) Projective–lag synchronization scheme: The projective– lag synchronization [7] corresponds to the fact that the proportion of retarded state of MS to the state of SL is a constant or ay(t) = bx(t − τd ) where a, b are nonzero real numbers and τd (τd ≥ 0) is synchronization manifold’s delay Master system with driving signal and slave system are expressed as MS: dx (1) = −αx + mi f (xτi ), dt i=1 DRV: DRV (t) = ki f xτ2+i , (2) i=1 SL: dy ni f (yτi ), = −αy + dt i=1 (3) where α, mi , ni , ki ∈ ℜ, and τi , τ2+i ∈ ℜ+ According to the Krasovskii-Lyapunov theory [15], the condition for synchronization is given as   ani = bmi − aki ,  α> |ani | |sup f ′ (xτi +τd )| , i=1 and τ2+i = τi + τd The parameters of systems are chosen as α = 2.5, a = 1, b = −1.5, m1 = −13.5, m2 = −0.5, n1 = −2, n2 = −0.1, k1 = 22.25, k2 = 0.85, τ1 = 2.6, τ2 = 0.5, τ3 = 4.6, τ4 = 2.5 and τd = 3) Projective–anticipating synchronization scheme: Projective–anticipating synchronization [7] in (1)–(3) is defined by ay(t) = bx(t + τd ) in which a, b are nonzero real numbers and τd (τd ≥ 0) is anticipate time Similar to the projective–lag synchronization circumstance, the sufficient condition for synchronization is   ani = bmi − aki ,  α> |ani | |sup f ′ (xτi −τd )| , i=1 and τ2+i = τi − τd It is noted that the value of anticipate time must be nonnegative or τi ≥ τd The selected parameters of systems are α = 2.5, a = 1, b = −1.5, m1 = −13.5, m2 = −0.5, n1 = −2, n2 = −0.1, k1 = 22.25, k2 = 0.85, τ1 = 2.6, τ2 = 0.5, τ3 = 2.2, τ4 = 0.1 and τd = 0.4 III I MPLEMENTATION AND RESULTS Delay systems were constructed by real components [16] or by analog electronic devices [14], [17] The circuit of Voss [14] included: a nonlinearity (built from a transistor and an adjustable amplifier), a low–pass RC filter and a commercially available bucket brigade delay line In [17], the analog electronic circuit consisted of a tunable delay unit, a nonlinear device and a fixed RC filter which played the role of one analog integrator The delay unit composed of a series of Fig x(t) with from the simulation with α = 2.5, m1 = −13.5, m2 = −0.5, τ1 = 2.6 and τ2 = 0.5 LCL filters However, it is difficult to change the configuration as well as parameters of these systems due to the complexity and separation of components Another solution is implementation on digital hardware platform because of fundamental arithmetic components, such as summation, subtraction, multiplier, and digital integrator could be realized conveniently by hardware description languages, e.g VHDL or Verilog The digital integrator in Fig is employed as follows Fig Phase portrait x versus xτ form simulation with α = 2.5, m1 = −13.5, m2 = −0.5, τ1 = 2.6 and τ2 = 0.5 x (t + h) = x (t) + hx˙ (t) , where h is the step size In our work, the nonlinear function has the polynomial form, in contrast to the piecewise linear function [3] which is appropriate for analog approach Because of the fact that the Maclaurin representation of the sine function could be written as ∞ sin x = n (−1) ; (2n + 1)! n=0 hence, the approximation of sine function has the following form x5 x3 + sin x ≈ x − 3! 5! A Simulation results Multiple time delay models is constructed by digital solution with fundamental components such as adder, subtraction, multiplier, register and digital integrator using Simulink and DSP–Builder software Numerical simulations of the analysis model as well as the complete synchronization are shown in Figs 3, 4, Corresponding VHDL code is generated and then is simulated by ModelSim Simulation results of complete synchronization, projective–lag and projective–anticipating synchronization (Fig 6) validate functional precision of our design It is clear to observe from Fig 6b that the state variable of slave is retarded with the time length of τd in compared to that of master in the lag synchronization In contrast, in the anticipate synchronization (Fig 6c), the slave appears earlier than the master B Implementation results Recently, FPGA is available to implement almost circuit including digital signal processing, communication devices, Fig Phase portrait x versus y of complete synchronization from simulation with α = 2.5, m1 = −13.5, m2 = −0.5, τ1 = 2.6, n1 = −2, n2 = −0.1, k1 = −11.5, k2 = −0.4, τ1 = 2.6 and τ2 = 0.5 system on chip or control systems [18] Generally speaking, FPGA is one kind of integrated circuit containing programmable logic components which allow to be configured by the customer The circuit is described by HDL [19] to synthesize, simulate and validate its functionality As the result, in this work, the FPGA-based digital approach is employed to reduce the developing time and reuse the configuration Developed VHDL code is compiled on DE2 development broad with Altera Cyclone II 2C35 FPGA device by Quartus II software By employing the RTL Viewer tool in Quartus II, the schematic diagram of overall synchronized system could be illustrated, for example, complete synchronization circumstance as in Fig The FPGA resource consumption for complete synchronous scheme, projective–lag and projective– anticipating synchronization are reported in Table I Total logic–element consumption around 3.3% guarantees the feasibility of our method Finally, using digital–to–analog converter, generated signals from FPGA could be observed by oscilloscope The measured signal x(t) is shown in Fig 8; while, the experimental synchronizations of complete, projective–lag and projective– TABLE I U TILIZED RESOURCES FOR IMPLEMENTATION OF THREE SYNCHRONIZATION SCHEMES Utilized Components Total logic elements Total registers Total memory bits Complete Synch 3.25% 824 23% Proj.–Lag Synch 3.37% 848 28% Proj.–Anti Synch 3.38% 850 21% (a) Complete sychronization Fig Experimentally observed x signal Horizontal axis: 50ms/div; vertical axis: 2V/div (b) Lag sychronization Fig 9c respectively Note also that, in our experiments, the amplitude of the output signal x(t) as in Fig is reduced to be appropriate with the limited features of digital–to–analog converters As the result, the amplitude of experimental signal is smaller than that of simulation signal (as in Fig 3) As expected, the experimental results fixed with the theoretically analysis and simulation results proves one proper method to realize multiple time delay feedback systems (c) Anticipate synchronization Fig State variables from simulation of three synchronization schemes by ModelSim, in each sub–figures: x (upper panel), y (lower panel) IV C ONCLUSION This paper has investigated the experimental synchronization in FPGA–based multiple delay systems By adjusting the driving signal and parameters of master and slave, three synchronization schemes are studied The experimental results agreed with the numerical simulations show not only the precision of theoretical synchronous techniques but also the effectiveness of FPGA–based designing method Due to its simplicity, the digital approach to realize the two delay system could also be modified to implement diverse multiple delay feedback systems with complex dynamics which are effectively applied as chaotic generators Further, it is the first step to achieve one advanced chaotic secure communication as demonstrated in [5] ACKNOWLEDGMENT This work is supported by the Vietnams National Foundation for Science and Technology Development (NAFOSTED) under Grant No 102.992010.17 Fig Schematic of the complete synchronization displayed by RTL Viewer tool R EFERENCES anticipating scheme are illustrated in Fig 9a, Fig 9b and [1] K Ikeda and K Matsumoto, “High-dimensional chaotic behavior in systems with time-delayed feedback,” Physica D, vol 29, pp 223–235, 1987 (a) Complete synchronization (b) Projective–lag synchronization (c) Projective–anticipating synchronization Fig Experimental synchronization of two multiple delay feedback system Horizontal axis: 2V/div; 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