Programming embedded systems ii a 10 week course, using c

Programming Embedded Systems II A 10-week course, using C Michael J Pont University of Leicester P0.3 P0.2 VCC P1.3 P0.4 P1.0 P1.4 P0.5 P0.1 P1.5 P0.6 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 / PSEN ALE / EA P0.7 P1.6 XTL1 XTL2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 RST P1.7 P0.0 P3.0 P1.1 10 VSS P1.2 11 12 13 14 15 16 17 18 19 20 ‘8051’ 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 [v2.0] I Copyright © Michael J Pont, 2002-2004 This document may be freely distributed and copied, provided that copyright notice at the foot of each OHP page is clearly visible in all copies II Seminar 1: Seminar 2: A flexible scheduler for single-processor embedded systems Overview of this seminar Overview of this course By the end of the course you’ll be able to … Main course text IMPORTANT: Course prerequisites Review: Why use C? Review: The 8051 microcontroller Review: The “super loop” software architecture Review: An introduction to schedulers Review: Building a scheduler Overview of this seminar The Co-operative Scheduler Overview The scheduler data structure and task array The size of the task array One possible initialisation function: IMPORTANT: The ‘one interrupt per microcontroller’ rule! The ‘Update’ function The ‘Add Task’ function The ‘Dispatcher’ Function arguments Function pointers and Keil linker options The ‘Start’ function The ‘Delete Task’ function Reducing power consumption Reporting errors Displaying error codes Hardware resource implications What is the CPU load of the scheduler? Determining the required tick interval Guidelines for predictable and reliable scheduling Overall strengths and weaknesses of the scheduler Preparations for the next seminar 10 11 12 13 14 15 16 17 18 19 20 22 24 25 28 29 30 31 34 35 36 38 40 41 42 III Seminar 3: Analogue I/O using ADCs and PWM Overview of this seminar PATTERN: One-Shot ADC PATTERN: One-Shot ADC Using a microcontroller with on-chip ADC Using an external parallel ADC Example: Using a Max150 ADC Using an external serial ADC Example: Using an external SPI ADC Overview of SPI Back to the example … Example: Using an external I2C ADC Overview of I2C Back to the example … What is PWM? PATTERN: Software PWM Preparations for the next seminar 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 59 62 IV Seminar 4: A closer look at co-operative task scheduling (and some alternatives) Overview of this seminar Review: Co-operative scheduling The pre-emptive scheduler Why we avoid pre-emptive schedulers in this course? Why is a co-operative scheduler (generally) more reliable? Critical sections of code How we deal with critical sections in a pre-emptive system? Building a “lock” mechanism The “best of both worlds” - a hybrid scheduler Creating a hybrid scheduler The ‘Update’ function for a hybrid scheduler Reliability and safety issues The safest way to use the hybrid scheduler Other forms of co-operative scheduler PATTERN: 255-TICK SCHEDULER PATTERN: ONE-TASK SCHEDULER PATTERN: ONE-YEAR SCHEDULER PATTERN: STABLE SCHEDULER Mix and match … Preparations for the next seminar 63 64 65 66 67 68 69 70 71 75 76 78 81 83 85 86 87 88 89 90 91 V Seminar 5: Improving system reliability using watchdog timers 93 Overview of this seminar The watchdog analogy PATTERN: Watchdog Recovery Choice of hardware Time-based error detection Other uses for watchdog-induced resets Recovery behaviour Risk assessment The limitations of single-processor designs Time, time, time … Watchdogs: Overall strengths and weaknesses PATTERN: Scheduler Watchdog Selecting the overflow period - “hard” constraints Selecting the overflow period - “soft” constraints PATTERN: Program-Flow Watchdog Dealing with errors Hardware resource implications Speeding up the response PATTERN: Reset Recovery PATTERN: Fail-Silent Recovery Example: Fail-Silent behaviour in the Airbus A310 Example: Fail-Silent behaviour in a steer-by-wire application PATTERN: Limp-Home Recovery Example: Limp-home behaviour in a steer-by-wire application PATTERN: Oscillator Watchdog Preparations for the next seminar 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 110 111 112 114 115 116 117 118 119 122 124 VI Seminar 6: Shared-clock schedulers for multi-processor systems Overview of this seminar Why use more than one processor? Additional CPU performance and hardware facilities The benefits of modular design The benefits of modular design So - how we link more than one processor? Synchronising the clocks Synchronising the clocks Synchronising the clocks - Slave nodes Transferring data Transferring data (Master to Slave) Transferring data (Slave to Master) Transferring data (Slave to Master) Detecting network and node errors Detecting errors in the Slave(s) Detecting errors in the Master Handling errors detected by the Slave Handling errors detected by the Master Enter a safe state and shut down the network Reset the network Engage a backup Slave Why additional processors may not improve reliability Redundant networks not guarantee increased reliability Replacing the human operator - implications Are multi-processor designs ever safe? Preparations for the next seminar 125 126 127 128 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 VII Seminar 7: Linking processors using RS-232 and RS-485 protocols Review: Shared-clock scheduling Overview of this seminar Review: What is ‘RS-232’? Review: Basic RS-232 Protocol Review: Transferring data to a PC using RS-232 PATTERN: SCU SCHEDULER (LOCAL) The message structure Determining the required baud rate Node Hardware Network wiring Overall strengths and weaknesses PATTERN: SCU Scheduler (RS-232) PATTERN: SCU Scheduler (RS-485) RS-232 vs RS-485 [number of nodes] RS-232 vs RS-485 [range and baud rates] RS-232 vs RS-485 [cabling] RS-232 vs RS-485 [transceivers] Software considerations: enable inputs Overall strengths and weaknesses Example: Network with Max489 transceivers Preparations for the next seminar 153 154 155 156 157 158 159 160 163 165 166 167 168 169 170 171 172 173 174 175 176 177 VIII Seminar 8: Linking processors using the Controller Area Network (CAN) bus Overview of this seminar PATTERN: SCC Scheduler What is CAN? CAN 1.0 vs CAN 2.0 Basic CAN vs Full CAN Which microcontrollers have support for CAN? S-C scheduling over CAN The message structure - Tick messages The message structure - Ack messages Determining the required baud rate Transceivers for distributed networks Node wiring for distributed networks Hardware and wiring for local networks Software for the shared-clock CAN scheduler Overall strengths and weaknesses Example: Creating a CAN-based scheduler using the Infineon C515c Master Software Slave Software What about CAN without on-chip hardware support? Preparations for the next seminar 179 180 181 182 184 185 186 187 188 189 190 192 193 194 195 196 197 198 211 218 220 IX Seminar 9: Applying “Proportional Integral Differential” (PID) control Overview of this seminar Why we need closed-loop control? Closed-loop control What closed-loop algorithm should you use? What is PID control? A complete PID control implementation Another version Dealing with ‘windup’ Choosing the controller parameters What sample rate? Hardware resource implications PID: Overall strengths and weaknesses Why open-loop controllers are still (sometimes) useful Limitations of PID control Example: Tuning the parameters of a cruise-control system Open-loop test Tuning the PID parameters: methodology First test Example: DC Motor Speed Control Alternative: Fuzzy control Preparations for the next seminar 221 222 223 227 228 229 230 231 232 233 234 235 236 237 238 239 241 242 243 245 248 249 X ... seminar PATTERN: One-Shot ADC PATTERN: One-Shot ADC Using a microcontroller with on-chip ADC Using an external parallel ADC Example: Using a Max150 ADC Using an external serial ADC Example: Using. .. seminar PATTERN: SCC Scheduler What is CAN? CAN 1.0 vs CAN 2.0 Basic CAN vs Full CAN Which microcontrollers have support for CAN? S -C scheduling over CAN The message structure - Tick messages... shared-clock CAN scheduler Overall strengths and weaknesses Example: Creating a CAN-based scheduler using the Infineon C5 1 5c Master Software Slave Software What about CAN without on-chip hardware