Logic kỹ thuật số thử nghiệm và mô phỏng P11
Logic kỹ thuật số thử nghiệm và mô phỏng P11
... paths to ground or power. On average, a node is going to be at logic 0 half the time and at logic 1 half the time. If the node is at logic 0 and is connected to a pullup, a path exists for current ... pulldowns. No floating nodes. No logic contention. If analog circuits appear in the design, they should be on separate power supplies. No unconnected inputs on unused logic. The purpose...
Ngày tải lên: 07/11/2013, 20:15
Logic kỹ thuật số thử nghiệm và mô phỏng P2
... ignores delay values within a logic element; it simply calculates the logic function performed by the element. A nominal-delay simulator assigns delay values to logic elements based on manufacturer’s ... of logic, is the set of elements encoun- tered during a backtrace from an internal circuit node, called the apex, to input state points. Definition 2.3 A predecessor of a logic elemen...
Ngày tải lên: 17/10/2013, 22:15
Logic kỹ thuật số thử nghiệm và mô phỏng P3
... follows, the positive logic convention will be used. Any voltage between ground (Gnd) and +0.8 V represents a logic 0. A voltage between +2.4 V and +5.0 V (Vcc) represents a logic 1. A voltage between ... is arbitrarily selected and required to generate a logic 1, then the upper AND gate must generate a logic 1, requiring that inputs X 1 and X 2 must both be at logic 1. As befor...
Ngày tải lên: 20/10/2013, 17:15
Logic kỹ thuật số thử nghiệm và mô phỏng P4
... is an AND gate, and a logic 1 on its output only occurs if all its inputs have logic 1 values. This is called implication ; a 1 on the output of an AND gate implies logic 1 on all its inputs. ... greater difficulties because a logic assignment at its upper input must be justified through other logic, and a test at its output must be propagated through additional logic. An arbitra...
Ngày tải lên: 20/10/2013, 17:15
Logic kỹ thuật số thử nghiệm và mô phỏng P5
... 254 SEQUENTIAL LOGIC TEST develop D-cubes for the super logic blocks by extending the basic memory element D-cubes through the preceding combinational logic. In the second step, beginning with a super logic ... super logic blocks. 2. Trace super logic block D-cubes to define sequential D-chains that define sequential circuit propagation paths. 3. Determine an exercise sequence for e...
Ngày tải lên: 24/10/2013, 15:15
Logic kỹ thuật số thử nghiệm và mô phỏng P6
... AUTOMATIC TEST EQUIPMENT Pin data PD 1 and PD 2 are identical; a logic 1 in pin memory is followed by a logic 0, another 1, and then a 0. However, because the timing generators are ... if all of them fail in an identical fashion, then the logical assumption is that there is a design error that occurred during either the logic design process or the physical design proc...
Ngày tải lên: 24/10/2013, 15:15
Logic kỹ thuật số thử nghiệm và mô phỏng P7
... of vectors, see Section 7.9.5. 7.8.3 Behavioral Fault Simulation The advent of RTL logic design and the resulting reliance on logic synthesis has had a major impact on design styles and productivity. ... No general method exists for spotting redundancies in logic circuits. 7.5.4 Bridging Faults Faults can be caused by shorts or opens. In TTL logic, an open at an input to an AND gate pr...
Ngày tải lên: 28/10/2013, 22:15
Logic kỹ thuật số thử nghiệm và mô phỏng P8
... shadow logic between scan registers and memory. 19 This is combinational logic that can not be directly accessed by the scan circuits. If the shadow logic consists solely of addressing logic, ... with IEEE1149.1 boundary scan. TDI TDO T A P TMS TCK TAP TAP TAP TAP TMS TCK Core logic Core logic Core logic Core logic ... the output of the AND gate fans out to other logic, that...
Ngày tải lên: 28/10/2013, 22:15
Logic kỹ thuật số thử nghiệm và mô phỏng P9
... test the oper- ational logic. Examples of first-degree hardcore include such things as a ROM dedicated to test which is loaded via a special access path not used by operational logic, a dedicated ... Mode SRL + SRL Data Scan-in Scan-out Scan-out (a) (b) + + Scan-in MISR PRG SI 1 SI 2 SI 3 SI n SO 1 SO 2 SO 3 SO N Comb. logic Comb. logic 488 BUILT-IN SELF-TEST Figure 9.21 Desktop Manageme...
Ngày tải lên: 07/11/2013, 20:15
Logic kỹ thuật số thử nghiệm và mô phỏng P10
... 45% random logic. Assume that in shipped parts, memory has 2 DPM (defects per million) and that the logic has 1100 DPM. What is the overall DPM for the chip? If process yield for the logic is 70%, ... array faults, and read/write logic faults. From there we use the fact, demonstrated by Nair, Thatte, and Abraham, 7 that faults in memory addressing and read/write logic, which includes...
Ngày tải lên: 07/11/2013, 20:15