Logic kỹ thuật số thử nghiệm và mô phỏng P3
Logic kỹ thuật số thử nghiệm và mô phỏng P3
... follows, the positive logic convention will be used. Any voltage
between ground (Gnd) and +0.8 V represents a logic 0. A voltage between +2.4 V
and +5.0 V (Vcc) represents a logic 1. A voltage between ... is
arbitrarily selected and required to generate a logic 1, then the upper AND gate must
generate a logic 1, requiring that inputs X
1
and X
2
must both be at logic 1. As befor...
Logic kỹ thuật số thử nghiệm và mô phỏng P2
... of logic, is the set of elements encoun- tered during a backtrace from an internal circuit node, called the apex, to input state points. Definition 2.3 A predecessor of a logic element is a logic ... behavior. 2.4 THE LOGIC SYMBOLS Test problems, as well as other circuit issues, are often described most effectively by means of schematic diagrams. Figure 2.1 introduces the logic symbol...
Logic kỹ thuật số thử nghiệm và mô phỏng P4
... processes,
propagation and justification, can be used to find a test for almost any fault in the cir-
cuit (redundant logic, as we shall eventually see, presents testing problems). Fur-
thermore, propagation and justification ... consequence of another assignment. Only one assignment is
possible. Consider the assignment of a logic 1 to the output of gate H. This implied
that all of its inputs...
Logic kỹ thuật số thử nghiệm và mô phỏng P5
... 5.3
254
SEQUENTIAL LOGIC TEST
develop D-cubes for the super logic blocks by extending the basic memory element
D-cubes through the preceding combinational logic.
In the second step, beginning with a super logic ... super logic blocks.
2. Trace super logic block D-cubes to define sequential D-chains that define
sequential circuit propagation paths.
3. Determine an exercise sequence f...
Logic kỹ thuật số thử nghiệm và mô phỏng P6
...
AUTOMATIC TEST EQUIPMENT
Pin data
PD
1
and
PD
2
are identical; a logic 1 in pin memory is followed by a
logic 0, another 1, and then a 0. However, because the timing generators are ... if all of them
fail in an identical fashion, then the logical assumption is that there is a design error
that occurred during either the logic design process or the physical design proc...
Logic kỹ thuật số thử nghiệm và mô phỏng P7
... By performing toggle counts during gate-level
logic simulation and linking switching activity to X-Y coordinates on the die, it is
323
Digital Logic Testing and Simulation
,
Second Edition
... No general method exists for
spotting redundancies in logic circuits.
7.5.4 Bridging Faults
Faults can be caused by shorts or opens. In TTL logic, an open at an input to an
AND gate preve...
Logic kỹ thuật số thử nghiệm và mô phỏng P8
... lesser num-
ber contained the more complex control logic and handshaking protocols. Test
programs for control logic would be created by requiring a logic designer or test
engineer to write vectors ... manipulated.
However, the real stumbling block for ATPG has been sequential logic. Because
of the inability of ATPGs to successfully deal with sequential logic, a growing num-
ber of dig...
Logic kỹ thuật số thử nghiệm và mô phỏng P9
... is to make field repair of logic boards possible.
This in turn can help to reduce investment in inventory of logic boards. It has been
estimated that a manufacturer of logic boards may have up ... Figure 9.4 adds logic to a functional register to permit dual-purpose
operation: normal functional mode and test response compaction. A more general
solution is the built-in logic block obs...
Logic kỹ thuật số thử nghiệm và mô phỏng P10
... 45% random
logic. Assume that in shipped parts, memory has 2 DPM (defects per million)
and that the logic has 1100 DPM. What is the overall DPM for the chip? If
process yield for the logic is 70%, ... array faults, and read/write logic faults. From there we use the fact,
demonstrated by Nair, Thatte, and Abraham,
7
that faults in memory addressing and
read/write logic, which includes...
Logic kỹ thuật số thử nghiệm và mô phỏng P11
... paths to ground or power. On
average, a node is going to be at logic 0 half the time and at logic 1 half the time. If the
node is at logic 0 and is connected to a pullup, a path exists for current ... behavioral model for very low level behavioral
devices, namely, the logic gates.
Faults such as high-resistance bridging shorts, inside a logic gate or between con-
nections to adjacen...