Digital logic testing and simulation phần 9 docx
Digital logic testing and simulation phần 9 docx
... J., Testing Memories: Advanced Concepts, Tutorial 12, International Test
Conference, 199 7.
9. Panel Discussion, A D&T Roundtable: Online Test, IEEE Des. Test Comput., January–
March 199 9, ... ED-26, No. 1, January 197 9, pp. 2 9.
20. Bossen, D. C., and M. Y. Hsiao, A System Solution to the Memory Soft Error Problem,
IBM J. Res. Dev., Vol. 24, No. 3, May 198 0, pp. 390 – 398 .
21....
Digital logic testing and simulation phần 1 pdf
...
:
Miczo, Alexander.
Digital logic testing and simulation / Alexander Miczo—2nd ed.
p. cm.
Rev. ed. of: Digital logic testing and simulation. c 198 6.
Includes bibliographical references and index. ... references and index.
ISBN 0-471-4 399 5 -9 (cloth)
1. Digital electronics Testing. I. Miczo, Alexander. Digital logic testing and simulation
II. Title.
TK7...
Digital logic testing and simulation phần 3 ppsx
... automated.
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Digital Logic Testing and Simulation
,
Second Edition
, by Alexander Miczo
ISBN 0-471-4 399 5 -9 Copyright © 2003 John Wiley & Sons, Inc.
CHAPTER 3
Fault Simulation
... Electron.
Testing: Theory and Applications, Vol. I, 199 0, pp. 7–13.
9. Armstrong, D.B., A Deductive Method for Simulating Faults in Logic Circuits, IEEE
Tr...
Digital logic testing and simulation phần 4 doc
... gate Q
if ((OR/NAND and C_O == 1) or (AND/ NOR and C_O == 0))
choose new objective net n; //input to Q
// n = X, and EASIEST to control
else
// ((OR/NAND and C_O == 0) or (AND/ NOR and C_O == 1))
choose ... was
made and choose an alternate assignment. This can be very CPU and/ or memory
intensive, depending on how many conflicts occur and how they are handled.
PODEM (path-orient...
Digital logic testing and simulation phần 5 potx
... 2, February 196 5, pp. 76– 79.
2. Putzolu, G., and J. P. Roth, A Heuristic Algorithm for the Testing of Asynchronous
Circuits, IEEE Trans. Comput., Vol. C20, No. 6, June 197 1, pp. 6 39 647.
3. Bouricius, ... Sensitizing Algorithm for Diagnosis of Binary Sequential Logic, Proc.
9th Symposium on Switching and Automata Theory, 197 0, pp. 250–2 59.
7. Kriz, T. A., Machine Identification...
Digital logic testing and simulation phần 6 pdf
... computed to be 99 .9% , the real coverage may be 99 .7% or 99 .94 %. In either
case you will have significantly fewer tester escapes than when the fault simulator
predicts 70% coverage. Fault simulation ... The 16 faults now appear as
SA0 and SA1 faults on the outputs of P and R and on each of the three inputs to S and
T. The SA0 faults at the inputs of AND gates S and T are e...
Digital logic testing and simulation phần 7 pps
... problem for scan. Memory and analog circuits must be iso-
lated from the digital logic, circuit partitioning becomes critical, and testing
strategies for memories and random logic must now coexist.
Sometimes ... developed the IEEE 11 49. 1 boundary scan standard.
In this section we first look, briefly, at the NAND tree and then look in detail at
boundary scan.
8.6.1 The NAND Tree...
Digital logic testing and simulation phần 8 pps
... than .99 975?
9. 16 If the probability of detection of a single randomly selected fault is .99 975,
what is the probability that 100 such randomly selected faults will all be
detected?
Figure 9. 34 ... that required 59 hours to generate contained 152 megabytes and included test
commands, signatures, and a logic model of the part. Fault coverage for the TCMs
ranged from 94 .5% up to...
Digital logic testing and simulation phần 10 pps
... September 199 3, pp. 16–28.
6. Syzgenda, S. A., and A. A. Lekkos, Integrated Techniques for Functional and Gate-Level
Digital Logic Simulation, Proc. 10th Design Automation Conf., 197 3, pp. 1 59 172.
7. ... Misconceptions in Digital Test Generation, Comput. Des.,
January 197 7, pp. 89 94 .
8. Bening, L., and H. Foster, Principles of Verifiable RTL Design, Kluwer, Boston, 2000.
9...
TRUYỀN HÌNH SỐ VÀ MULTIMEDIA (Digital Compressed Television and Multimedia) - Phần 3 docx
... Association)
DAVIC (Digital Audio Visual Council)
DAVIC (Digital Audio Visual Council)
VESA (Video Electronics Standards Association)
VESA (Video Electronics Standards Association)
MHEG (Multimedia and ... interface)
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