Digital logic testing and simulation phần 3 ppsx

... circuit. Figure 3. 7 Equivalent and dominant faults. D 1 Sel D 0 A B C D Z PROBLEMS 161 Figure 3. 17 Using deductive fault simulation. 3. 12 Finish the fault simulation example for Figure 3. 10 in Section 3. 6.1. ... circuit of Figure 3. 10 using the faults and vectors defined in the preceding problem. 3. 15 Again using the circuit in Figure 3. 10, and the faults and vectors...

Ngày tải lên: 09/08/2014, 16:20

... Test Plan 31 5 6.11 Visual Inspection 31 6 6.12 Test Cost 31 9 6. 13 Summary 31 9 Problems 32 0 References 32 1 7 Developing a Test Strategy 32 3 7.1 Introduction 32 3 7.2 The Test Triad 32 3 7 .3 Overview ... 0.08005 0. 035 31 0.02160 0.00927 0.00702 0.00 532 JSSC 0.2 138 3 0.1 137 3 0. 037 30 0.01548 0.00 834 0.0 036 2 0.00048 CAD 0.21714 0.12 439 0.04556 0.01985 0.01090 0.0...

Ngày tải lên: 09/08/2014, 16:20

... get g·D 3 (h) = g·D 3 (u·v) = g·u·D 3 (v) (from property 9) Property 5 can now be used to yield D 3 (x 1 + x 3 ) = x 1 ·D 3 (x 3 ) ⊕ x 3 ·D 3 (x 1 ) ⊕ D 3 (x 3 ) ·D 3 (x 1 ) The independence theorem ... gate Q if ((OR/NAND and C_O == 1) or (AND/ NOR and C_O == 0)) choose new objective net n; //input to Q // n = X, and EASIEST to control else // ((OR/NAND and C...

Ngày tải lên: 09/08/2014, 16:20

... tables. S 0 S 1 S 2 S 3 0 1 0 1 01 1 0 0 (a) S 0 S 1 S 2 S 3 0 1 1 01 1 0 (b) S 0 S 1 S 2 S 3 S 1 S 3 S 1 S 0 S 1 S 2 S 3 S 0 01 01 Data S 0 S 1 S 2 S 3 S 1 S 3 S 1 S 3 S 1 S 2 S 3 S 0 Data 260 SEQUENTIAL LOGIC TEST if a test exists, ... 6, June 1976, pp. 630 – 636 . 5. Marlett, Ralph, EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits, Proc. 15t...

Ngày tải lên: 09/08/2014, 16:20

... | !(CN)); wire A_EQ_B = F3 & F2 & F1 & F0; xy U3 (X3,Y3,S3,S2,S1,S0,A3,B3); xy U2 (X2,Y2,S3,S2,S1,S0,A2,B2); xy U1 (X1,Y1,S3,S2,S1,S0,A1,B1); xy U0 (X0,Y0,S3,S2,S1,S0,A0,B0); endmodule When ... multiplexer. Faults Detected AB C F (NAND) (NOR) 0 1 0 0 1.1, 2.1 SA1 3. 1 SA0 1 0 1 0 1.2, 2.2 SA1 3. 2 SA0 X 1 1 1 3. 2 SA1 2.2 SA0 1 X 0 1 3. 1 SA1 1.1 SA0 A S B A S B 4 1 2 4 1 3...

Ngày tải lên: 09/08/2014, 16:20

... problem for scan. Memory and analog circuits must be iso- lated from the digital logic, circuit partitioning becomes critical, and testing strategies for memories and random logic must now coexist. Sometimes ... boundary scan standard. In this section we first look, briefly, at the NAND tree and then look in detail at boundary scan. 8.6.1 The NAND Tree The NAND tree, shown in Fig...

Ngày tải lên: 09/08/2014, 16:20

... Table IC Pin Signature IC Pin Signature U21 2 8UP3 U41 3 37A3 3 713A 5 84U4 4 01F6 6 F0P1 7 69CH 8 1147 9 8P7U 9 77H1 11 684C 11 10UP 15 H1C3 14 135 9 15 U11A 504 BUILT-IN SELF-TEST The reliability ... operation and signal the system that they have failed. Maintenance software then runs tests on the board. If it passes, the maintenance routines assume the error 5 13 Digital Logic...

Ngày tải lên: 09/08/2014, 16:20

... 406–4 13. 13. Dekker, R. et al., A Realistic Self-Test Machine for Static Random Access Memories, Proc. Int. Test Conf., 1988, pp. 35 3 36 1. 14. Franklin, M., and K. K. Saluja, Built-in Self -Testing ... periods. Pullups and pulldowns provide resistive paths to ground or power. On average, a node is going to be at logic 0 half the time and at logic 1 half the time. If the node...

Ngày tải lên: 09/08/2014, 16:20

... September 19 93, pp. 16–28. 6. Syzgenda, S. A., and A. A. Lekkos, Integrated Techniques for Functional and Gate-Level Digital Logic Simulation, Proc. 10th Design Automation Conf., 19 73, pp. 159–172. 7. ... IEEE Spectrum, Vol. 33 , No. 6, June 1996, pp. 68–71. 31 . Clarke, E. M., and R. P. Kurshan, Computer-aided Verification, IEEE Spectrum, June 1996, Vol. 33 , No. 6, pp. 61–67....

Ngày tải lên: 09/08/2014, 16:20

... be   =−07 035 3, giving an estimated variance reduction ratio of  1 −07 035  −1 = 3 37 3. Another way to estimate the v.r.r. is to note that an estimate of 1 + −1 from Equation (5 .3) is vrr ... generated is approximately √ 2 ln 524 = 3 54 and that the largest negative value is approximately −  2ln4 × 131  /3 = 3 21. In a random sample of 2 30 such variates, correspond...

Ngày tải lên: 09/08/2014, 16:21