design of cmos operational amplifiers pdf

This book presents important details and design methodologies for different architectures of single-ended op amps Complete chapters are dedicated to the critical issues of CMOS output stages, fully differential op amps, and CMOS reference generators Also included is an introduction to CMOS technology and a discussion of the basics of the physical aspects of MOS transistors, providing the foundation needed to fully master the material Rasoul Dehghani is an assistant professor in the Department of Electrical and Computer Engineering at Isfahan University of Technology in Iran He holds a Ph.D in electronics from Sharif University, Tehran, Iran He is a well-published and frequently cited author in the field Include bar code ISBN 10: 1-60807-153-7 ISBN 13: 978-1-60807-153-1 BOSTON LONDON www.artechhouse.com ni Design of CMOS Operational Amplifiers CMOS operational amplifiers (op amps) are one of the most important building blocks in many of today’s integrated circuits This cutting-edge volume provides professionals and students with an analytical method for designing CMOS op amp circuits, placing emphasis on the practical aspects of the design process Readers take an in-depth look at CMOS differential amplifiers and learn why and how they serve as the main part of any op amp Rasoul Dehghani De Op sig Am er n Ra p at of so li io C f n M ul ie a OS De rs l hg Dehghani Design of CMOS Operational Amplifiers Design of CMOS Operational Amplifiers www.TechnicalBooksPDF.com For a complete listing of titles in the Artech House Microwave Library, turn to the back of this book www.TechnicalBooksPDF.com Design of CMOS Operational Amplifiers Rasoul Dehghani www.TechnicalBooksPDF.com Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S Library of Congress British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Cover design by Adam Renvoize ISBN 13: 978-1-60807-153-1 © 2013 ARTECH HOUSE 685 Canton Street Norwood, MA 02062 All rights reserved Printed and bound in the United States of America No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized Artech House cannot attest to the accuracy of this information Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark 10 www.TechnicalBooksPDF.com Contents Chapter Basic Specifications of Op Amps 1.1 Op Amp Parameters 1.2 Conclusion 1 13 Chapter CMOS Technology and Physics 2.1 Basic Processes in MOS Transistor Fabrication 2.2 Principles of MOS Transistor Functioning 2.2.1 MOS Transistor Operating in Saturation Region 2.2.2 MOS Transistor Operating in Subthreshold Regime 2.3 Small-Signal Model of MOS Device 2.3.1 Gate to Substrate Capacitance 2.3.2 Gate to Source/Drain Capacitance 2.3.3 Source/Drain to Bulk Capacitance 2.4 Conclusion 15 15 17 17 21 21 24 26 27 31 Chapter CMOS Differential Amplifiers 3.1 Source-Coupled Differential Pair Characteristic 3.2 CMOS Differential Amplifier with Active Load 3.2.1 Large-Signal Characteristic of CMOS Differential Amplifier 3.2.2 Offset Voltage of CMOS Differential Amplifier 3.3 Common-Mode Behavior of CMOS Differential Amplifier 3.4 CMOS Differential Amplifier Frequency Response 3.5 Noise Calculations in CMOS Differential Amplifier 3.6 Conclusion 33 33 36 Chapter CMOS Single-Ended Output Op Amps 4.1 CMOS Two-Stage Op Amp 4.1.1 Offset Voltage 4.1.2 Two-Stage Op Amp Frequency Response 4.1.3 CMOS Two-Stage Op Amp Design Procedure Design Example 4.1.4 PSRR of CMOS Two-Stage Op Amp 4.2 Telescopic Cascode Op Amp 4.3 Folded-Cascode Op Amp Design Example 4.4 Current Mirror Op Amp Design Example 4.5 Rail-to-Rail Input Op Amp 4.6 Conclusion 36 38 42 43 47 53 55 55 56 59 65 69 72 83 86 87 90 94 96 105 v www.TechnicalBooksPDF.com vi Contents Chapter CMOS Fully Differential Op Amps 5.1 Advantages of Fully Differential Op Amps 5.2 Common-Mode Feedback Concept 5.3 Common-Mode Feedback Circuits 5.3.1 Common-Mode Feedback Circuit with Resistive Sensing 5.3.2 Differential Difference Common-Mode Feedback Circuit 5.3.3 Common-Mode Feedback Circuit Using MOS Devices Operating in the Triode Region 5.3.4 Switched-Capacitor Common-Mode Feedback Circuit 5.4 Fully Differential CMOS Op Amp Architectures 5.4.1 Fully Differential Two-Stage Op Amp 5.4.2 Fully Differential Current Mirror Op Amp 5.4.3 Fully Differential Folded-Cascode Op Amp Design Example 5.5 Conclusion 118 119 123 123 127 129 130 134 Chapter CMOS Output Stages 6.1 Class A and Class B Output Stages 6.1.1 Source-Follower as an Output Stage 6.1.2 Class B Power Amplifier 6.2 Drain-Coupled Complementary Transistors as Output Stage 6.3 Low-Voltage Class AB Buffer 6.4 Class AB Output Stage Using a Translinear Loop 6.5 Case Study Design Example 6.6 Conclusion 135 135 135 139 142 149 153 159 163 166 Chapter CMOS Reference Generators 7.1 CMOS Voltage Reference Generators 7.1.1 Bandgap Voltage Reference Generator Design Example 7.1.2 Low-Voltage Bandgap Reference Generator Design Example 7.1.3 CMOS Voltage Reference Generator without Resistors 7.2 CMOS Current Reference Generators 7.2.1 Gm-Constant Circuit 7.2.2 Fully Integrated Precision CMOS Current Reference 7.2.3 CMOS Current Reference without Resistors Design Example 7.3 Conclusion Index 167 167 168 170 173 174 176 180 182 186 188 191 193 195 www.TechnicalBooksPDF.com 107 107 109 111 112 114 Chapter Basic Specifications of Op Amps An operational amplifier is one of the most important building blocks in many analog systems For instance, in an integrated analog filter such as a switchedcapacitor or a Gm-C filter, the op amp is an integral part of the circuit Data converters including both analog-to-digital and digital-to-analog converters are other categories in which the op amp plays a fundamental role to achieve the desirable performance In voltage and current reference generators an op amp has remarkable influence on the operation of these circuits In the enumerated instances many parameters of the system are extensively dependent on the specifications of the op amps used in that system It should be noted that the criteria applied to the design of an op amp employed in such systems are usually different from those used for designing a general-purpose op amp that is to be available as a stand-alone component in discrete circuitries In general, the behavior of an op amp is described by many different parameters in which some of them might be more important than others in a particular analog system In this chapter we introduce the main op amp parameters that have significant impact on the behavior of an analog system where an op amp has been exploited 1.1 Op Amp Parameters DC gain: Ideally the value of this parameter is considered infinity but in reality, due to the limited intrinsic voltage gain of each device used in the op amp circuit, the entire gain of an op amp has a finite value in the typical range of to (40 dB-100 dB) Exploiting an op amp in a linear amplifier involves putting the op amp in a negative-feedback loop In this situation a high dc gain of the op amp could be essential In the following we demonstrate the reason for such an assertion Supposing that the open-loop gain of the feedback is quite high, we can calculate the closed-loop gain of the circuit based on the values of the feedback network components independent of the op amp parameters As an example consider the inverting feedback amplifier shown in Figure 1.1 Denoting the low-frequency voltage gain of the op amp as , we can calculate the exact www.TechnicalBooksPDF.com Basic Specifications of Op Amps C2 C1 vi − vo + Figure 1.1 Inverting feedback amplifier closed-loop voltage gain as (1.1) Where is the feedback factor If it is assumed that , (1.1) can be approximated as In an ideal case, for , the amplifier gain is completely independent of the op amp gain and equals In practice, for a particular feedback gain error, we need to increase the op amp gain above a certain level For example, ideal feedback gain of with an error less than 0.1% is achievable provided that or if we have Thus, in order to achieve more accurate feedback gain the dc gain of the op amp needs to be quite high Limited linearity range For a certain level of the input and output signal variations, the internal devices of op amp operate in the linear part of their characteristics At input, the devices remain in their active operation region when the variation range of the input common-mode voltage is limited to a particular range known as input common-mode range (ICMR) [1] This parameter depends on the op amp structure and the type and biasing conditions of the input devices The linear operation range for a differential input signal in an open-loop state is much more limited Of course when an op amp is used in a negative-feedback loop, the linearity behavior is significantly improved by the feedback mechanism An amplified signal at the output of an op amp can also swing in the limited range at the most between two supply rails, although its precise level depends on the particular structure utilized as the output stage Common-mode rejection ratio One of the most outstanding advantages of an op amp is its capability to amplify the difference of two input signals without output being affected significantly by the changes in the input common-mode level This property results in immunity against any common-mode undesirable signal that www.TechnicalBooksPDF.com 1.1 Op Amp Parameters might appear at the inputs of the op amp The parameter of common-mode rejection ratio (CMRR) is used to quantify this performance [2] The definition of this parameter is a little bit different for the two types of op amp In a fully differential op amp in which both input and output signals are differential, the differential-mode and common-mode components of the output voltage are expressed as a linear combination of the corresponding input voltages as follows !"# $# !%$ !"$ ## !%# $$ !%$ (1.2a) #$ !%# (1.2b) where ## and $$ are differential-mode and common-mode voltage gains, respectively $# and #$ exhibit the contribution of the common-mode and differential-mode of the input; that is, !%$ and !%# in their corresponding components in the output voltage, respectively In an ideal differential op amp with a fully symmetrical structure, we have $# but in reality, due to #$ the device mismatches in the path of each input to two other outputs, this is not the case In this situation, CMRR is defined as the ratio of the differential voltage gain ## to the common-mode to differential-mode voltage gain $# as & ''() * ++ ,+ * (1.3) where & ''() denotes the fully differential CMRR To measure the & ''() , we might exploit the circuit illustrated in Figure 1.2 The fully differential op amp is configured as a unity voltage gain amplifier in a negative-feedback loop The internal common-feedback circuit and the external negative-feedback cause the output common-mode voltage and also the dc level of each output to be kept on the common-mode reference voltage denoted by -$ Representing the voltages at the inverting and noninverting inputs of the op amp as ! / and ! , respectively, we can easily find these voltages as follows !/ !" ! !"/ -$ -$ -$0 (1.4a) -$0 (1.4b) From the above relations, the input differential-mode and common-mode voltages are obtained !%$ !%# ! ! !/ !/ !"$ !"# -$ www.TechnicalBooksPDF.com (1.5a) -$0 (1.5b) 184 CMOS Reference Generators I1 I1=f(I2) I2 = I1 I0 I2 I0 Figure 7.18 Equilibrium points of a twin-loop current mirror with a series resistor substituting W W W into (7.29), the circuit current is given by W ỈÅ F d‡ G (7.30) where } o p o p and ° hY "V o p The current W is independent of the threshold voltage and the main process parameter that affects W is the gate oxide thickness The current W changes with temperature because carrier mobility in ° is dependent on temperature as ã / The supply voltage affects W if the channel length modulation for the transistors is taken into account In practice, the threshold voltage of M2 is greater than that of M1 due to the body effect in an n-well process This can cause an extra error To eliminate this error the source degenerative resistor can be added to the source of the PMOS current mirror, as depicted in Figure 7.19 VDD R + VSG3 - + VSG4 M4 M3 I0 M2 M1 : Figure 7.19 Twin-loop current mirror with a source degenerative resistor in a PMOS current mirror 7.2 CMOS Current Reference Generators 185 VDD : M4 M3 I1 I2 R M1 - + VGS1 M2 + VGS2 - Figure 7.20 Another structure for the current reference-eliminating body effect Another option is to use the circuit of Figure 7.20 By simple analysis we can prove that the same relationship is applied for W Now let an MOS transistor be biased by the current generated from this kind of current reference In the relationship of X0 • ° W , by replacing W with (7.30) we obtain X0 d‡ (7.31) Here X0 is nearly independent of biasing current or process parameters, hence this kind of current reference is also known as a gm-constant circuit When body effect is taken into account (| Ö ) supply variation can change the reference current through the limited drain-source resistance of M3 One approach to reduce this effect is to choose M3 and M4 with a long channel length to lower | Another way is to use an op amp to force M3 and M4 to have equal drain-source voltages, as VDD M3 M4 - + R I0 M1 Figure 7.21 Gm-constant circuit using an op amp M2 186 CMOS Reference Generators illustrated in Figure 7.21 This circuit consists of two different positive- and negative-feedback loops The op amp and the common-source stage amplifier formed by M2 and M4 constitute the negative-feedback loop and the other one similarly formed through M1 and M3 except that the open loop voltage gain of the latter is much lower than that of the first one Therefore the negative feedback is stronger and it guarantees the stable operation of the circuit The gm-constant circuit has two main drawbacks First, its current depends on temperature because of the presence of the carrier mobility parameter h, which changes with temperature as h ã h ã ã / Second, it depends inversely on the square of resistance Thus the current of W can change greatly in a given process due to the large absolute variation of resistance in that process 7.2.2 Fully Integrated Precision CMOS Current Reference In a gm-constant circuit the current has a positive temperature coefficient due to the term of h that appears in the denominator of (7.30) One idea to make a current nearly independent of temperature is to combine two currents with opposite temperature coefficients in such a way that the total current is almost independent of temperature The main idea can be described with the aid of a new circuit shown in Figure 7.22 [6] In this circuit the op amp forces the drain-source voltage of M1 to be equal to - The reference voltage of - is produced by a bandgap voltage generator whose temperature coefficient is deliberately made positive Supposing - is less than the saturation voltage of M1, we put M1 in the triode region with the following drain current VDD M4 : M5 M6 Iout Vr + - M3 M1 M2 : Figure 7.22 Architecture of a new current reference 7.2 CMOS Current Reference Generators W) ° j -fD 42 -e - l 187 (7.32) The diode-connected M2 works in saturation and we can write W) Ỉ2 -fD From (7.32) and (7.33) and noting that -fD and W) can be derived as follows: W) ° ỗât {:2 ặ2 -e (7.33) -fD , the relationship between W) 42 - ¬è (7.34) The PMOS current mirror M4-M5 forces the drain current of M1 and M2 to be equal In this situation the circuit equilibrium point can be found by the intersection of the corresponding curve of (7.34) and the bisector of the Cartesian coordinate system, as plotted in Figure 7.23 As can be seen, the circuit has two different stable points in which only the one with the larger current level is considered as a suitable operating point Substituting W) W) W into (7.34) yields the following equation: W F G ° - W ỈÅ Ỉ2 F ÆÅ G (7.35) Solutions of (7.35) give the current W If we have ° ° , the first quadrant bisector will be tangent to the curve in Figure 7.23 and thus two operating points become coincident and the current will be W ° - In this case for ID1 ID 1= ID ID1=f(ID2) Figure 7.23 Equilibrium points of a new current reference ID2 188 CMOS Reference Generators ° hY "V o p the ratio of W o p becomes hY "V- As was proved in Chapter 2, a rough estimation that shows an MOS transistor works in the subthreshold region is that the ratio of W) o p is less than hY "V q¦ , thus for - q¦ , M1 and M2 work in the subthreshold and none of the above relationships are applicable, a condition that is quite possible to occur because of the small value of - But for ° Ö ° we can shift the circuit to our desirable operating point with the aid of an appropriate startup circuit At the new operating point with a higher current level, all aforementioned equations are valid As an example, for ° ° , (7.35) gives two solutions: W ỈÅ C> d (7.36) In which the bigger solution guarantees the validity of the derived equations In order to have an output current with approximately zero temperature coefficient, we set W ·W ·ã for the term with a plus sign in (7.36), which results in z4 ze zỈÅ ÆÅ ze (7.37) Using h ã h ã ã / in ° hY "V o p by manipulating (7.37), we can obtain the desired relative variation of - with respect to temperature as z4 ze Œ e (7.38) where ã C › œ Therefore, the temperature coefficient of - should be around /Ž =‹ ›œ This means that in order to have a reference current with a nearzero temperature coefficient it is enough to use a low-voltage bandgap voltage with a positive temperature coefficient of = ‹ /Ž ›œ Note that - is a bandgap voltage and there is no resistance parameter in (7.36) We see that the only process parameter that can mainly affect W is the gate oxide thickness n"V, which appears in ° hY o p "V with "V m"V n"V Thus it can be claimed that this circuit has minimum variations with process in addition to a nearzero temperature coefficient 7.2.3 CMOS Current Reference without Resistors There is another current reference architecture that is very similar to the gmconstant circuit But in this circuit, instead of a resistor an MOS transistor working in the triode region has been used The circuit is shown in Figure 7.24 [7] By choosing a large aspect ratio for M1 and M2 and taking a low-level drain current for them, these transistors would work in the subthreshold region Therefore, their gate-source voltages can be written as 7.2 CMOS Current Reference Generators 189 VDD M3 M7 : M4 : I1 I1 I2 n:1 M1 M6 M2 M5 : m Figure 7.24 CMOS current reference without a resistor -fD -fD We can also write -eY -eY -fD qƯ ã H qƯ ã H -fD { {Å ² ³ {v F G -)D Using (7.39), (7.40), and (7.41), and surmising -eY -)D ² ³ Å {v F G qƯ c ã I I -eY , we obtain (7.39) (7.40) (7.41) (7.42) Equation (7.42) shows that the M5 drain-source voltage is a small voltage and therefore this transistor operates in the triode region with the following relation for its drain current: W ° F-fD -eY 4:ké G -)D (7.43) Diode-connected M6 works in saturation with W °ê -fDê -eY Since -fD -fDê , we can replace the term of -fD -eY in (7.43) with • W °ê, which 190 CMOS Reference Generators yields W ât ặ W & { 4Ơ BC Y qƯ c ã (7.44) The current mirror M3-M7 forces W to be equal to W , thus the circuit operating point will be the intersection of the curve represented by (7.44) and the straight line of W W By definitions W W W and ! qƯ c ã and noting that &ờ , the equation from which the current W can be calculated will be °! W Ç ° !Ç (7.45) Two solutions of (7.45) are given by W > •02 /0 0/ ° qƯ c ã (7.46) In (7.46) the current of W depends on temperature because of the presence of ° and -q¦ For h ã h ã ã / we can conclude from (7.46) that W J ã In this architecture our current reference mainly depends on the gate oxide thickness like the previous one but its variation with temperature is not negligible The circuit has two stable equilibrium points A and B that are the same as shown in Figure 7.23 If the circuit places in point A the current level at this point is too small and therefore it needs to be transferred to the other stable point B This can be carried out by adding an appropriate startup circuit Assume the circuit of Figure 7.24 initially operates in the operating point of A The startup circuit should act in such a way that it can temporarily increase the drain current of M1 When this current increases the M6 current also increases through the current mirror M3-M7, which causes the gate-source voltage of M6 and M5 to rise This increases the drain current of M5 and M1 By repeating the above mechanism, which acts as a positive feedback, the operating point of the circuit quickly moves toward point B Figure 7.25 shows the increase path in W and W that is initiated by the startup circuit and continues through the positive-feedback mechanism I1 = I2 I1 I1=f(I2) B A I2 Figure 7.25 Transfer path from point A to point B by a startup circuit 7.2 CMOS Current Reference Generators 191 In an n-well process the body effect causes M1 and M2 to have different threshold voltages This difference adds an error term of 3-eY -eY -eY to (7.42) Since this term changes with process and temperature the reference current will have more variation in comparison to what is predicted by (7.46) To solve this issue the circuit can be replaced by its dual circuit, as depicted in Figure 7.26 The substrate terminal of M2 is tied to its source This eliminates the body effect in M2 Design Example In this example a current reference circuit is to be designed with W \¶ in a 0.25- m CMOS technology The chosen structure is based on the architecture of Figure 7.26 In order to make sure that M1 and M2 work in the subthreshold, their aspect ratio should satisfy the following inequality: {: ² ³ Å F G hR "V qƯ (7.47) For W) \ả, in the given process, with hì "V = \ả [ , T and from (7.47) we should have o p B = In practice an MOS transistor passes through the moderate inversion before entering the subthreshold region that is equivalent to the weak inversion under the gate Taking into account the moderate inversion region and in order to be sure that the transistors work in the subthreshold in all process corners, it needs to make the ratio much more than what the inequality of (7.47) predicts Here we choose o p < For • we have o p In this circuit the difference between the drain-source voltage of M1 and that of M2, as well as the difference between the drain-source voltage of M4 and M3 and that of M7 is large Thus the nonzero value of | in these transistors significantly affects their current levels In order to minimize the short-channel effects the channel lengths of M1 and M2 are chosen p H = \Š that yields o C \Š and o < \Š From (7.46) for W \¶ and & , the size of M5 can be obtained as o p ; We choose p = h& Figure 7.26 Current reference circuit without a body effect error 192 CMOS Reference Generators Table 7.1 Output Reference Current in Different Process Corners Process Corner W \¶ (Figure 7.26, p = \Š) W \¶ (Figure 7.27, p = \Š) Slow-Slow Typical-Typical Fast-Fast Slow-Fast Fast-Slow 1.021 1.117 1.234 1.142 1.094 1.030 1.089 1.150 1.115 1.063 and o = \Š So the size of M6 becomes pê = \Š and oê = \Š M3, M4, and M7 are current mirrors with the size ratio of one To save chip area and minimize the channel modulation effect, oŽHÇHŒ pŽHÇHŒ = \Š are selected Data obtained from the simulations in the different process corners at ã =A are summarized in Table 7.1 The most change in W is related to the transition from the typical-typical (TT) to the fast-fast (FF) corner with =- variation In the given process the maximum relative variation from TT to FF or slow-slow (SS) due to the gate oxide thickness variation is about 5.