Design of CMOS receivers and building blocks for ultra wideband radio

DESIGN OF CMOS RECEIVERS AND BUILDING BLOCKS FOR ULTRA-WIDEBAND RADIO TONG YAN (B. Eng. , Zhejiang University) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2006 i Name: TONG YAN Degree: Master of Engineering Department: Electrical and Computer Engineering, NUS Thesis Title: Design of CMOS Receivers and Building Blocks for Ultra-Wideband Radio Abstract In this thesis, receiver systems and CMOS integrated circuits design for Ultra-Wideband (UWB) communication are proposed. Several building blocks for the receivers are designed in a 0.18-µm CMOS technology. Cross-coupled transistors with source followers are used to implement the multiplier. Inductor peaking technique is employed to enhance multiplier bandwidth with more than 7 GHz bandwidth. A continuous-time negative feedback loop is employed in the VGA to suppress DC-offset by 15 dB while obtaining 45 dB dynamic range. The integrator employs Gm − C − OTA structure to obtain a unit gain frequency of around 1 GHz and low -3 dB bandwidth of less than 1MHz. Two UWB receiver architectures are proposed and implemented using the proposed building blocks. The coherent receiver achieves simulated transmission rate of 100 MHz and sensitivity of -80 MHz, and the non-coherent receiver achieves measured transmission rate of 50 MHz and sensitivity of -65 dBm. Keywords: ultra-wideband, receiver, DC-offset, multiplier, variable gain amplifier, integrator. ii Acknowledgements I would like to express my deepest gratitude to my supervisor, Dr. Zheng Yuanjin, for the opportunity to work on an interesting research topic and his encouragement, guidance and many invaluable ideas during the research. I am also extremely grateful to my associate supervisor, Assoc. Prof Xu Yong Ping, for his guidance and patience. His invaluable comments has made breakthrough to the whole research project. I would also like to take this opportunity to thank the Institute of Microelectronics for the award of a research scholarship under Joint Microelectronics Laboratory with National University of Singapore and Integrated Circuits and System Laboratory for providing excellent facilities, without which the present work would not have been possible. Thanks also go to the National University of Singapore for giving me the opportunity to pursue postgraduate study. I am grateful to Mr. Wong Sheng Jau, and Mr. Oh Boon Hwee for their numerous extended discussions, clear thoughts and generous assistance provided throughout the project. iii I would like to thank my friends Cao Rui, Zhou Qiaoer, Yan Jiangnan and Yang Liu, Wei Xiaoqian and Cao Mingzheng who are working together with me in IME. The relaxed and inspiring team atmosphere with them is very helpful to the completion of this work. I want to express my gratitude to my colleagues Zhou Lei, Chen Jianzhong, Pu Yu, Yu Rui, Yu Jianghong, Gu Jun, Hu Yingpin, He Ying, Wei Ying, Wu Hong Lei and M. Umashankar at the NUS Signal Processing and VLSI Design laboratory for creating a relaxed and pleasant working atmosphere. Finally, I am deeply indebted to my family for their unconditional love, encouragement and support. They have been extremely important not only in making me who I am, but also in helping me through the highs and lows that have accompanied my academic endeavor. iv Table of Contents Abstract ............................................................................................................... ii Acknowledgements............................................................................................. iii Table of Contents................................................................................................. v Summary .......................................................................................................... viii List of Tables ....................................................................................................... x List of Figures .................................................................................................... xi List of Symbols and Abbreviations ................................................................... xiv Chapter 1 Introduction ......................................................................................... 1 1.1 Background and Motivation .................................................................... 1 1.1.1 Overview of Ultra-Wideband System............................................. 1 1.1.2 Motivation..................................................................................... 4 1.2 Organization of the Thesis....................................................................... 5 Chapter 2 UWB Receiver Architectures ............................................................... 7 2.1 Overview of Receiver Architectures ........................................................ 7 2.1.1 An Overview of Direct Conversion Receiver Architecture ............. 7 2.2.2 DS-UWB Receiver Architectures in the Literature........................11 2.2 Proposed UWB Modulation Schemes and Receiver Architectures ......... 14 2.2.1 Antipodal Modulation and Coherent Receiver Architecture.......... 14 2.2.2 On-Off Keying Modulation and Non-Coherent Receiver Architecture ......................................................................................... 21 Chapter 3 UWB Receiver Building Blocks Design ............................................ 25 3.1 Multiplier .............................................................................................. 26 v 3.1.1 CMOS Transconductance Analog Multiplier................................ 26 3.1.2 Proposed Multiplier for Ultra-Wideband Receiver ....................... 33 3.2 Variable Gain Amplifier ........................................................................ 39 3.2.1 General Consideration ................................................................. 39 3.2.2 Existing Gain Varying Techniques ............................................... 40 3.2.3 DC-Offset Cancellation Techniques ............................................. 42 3.2.4 Proposed VGA Circuits with DC-offset Suppression Loop and Simulated Performance ........................................................................ 45 3.3 Integrator .............................................................................................. 51 3.3.1 Integrators in the Literature.......................................................... 51 3.3.2 Proposed Integrator Structure ...................................................... 55 3.3.3 Circuits implementation and Performance.................................... 61 3.4 Comparator ........................................................................................... 66 3.5 A Brief Overview of Other Receiver Building Blocks............................ 68 3.5.1 Low Noise Amplifier ................................................................... 68 3.5.2 Pulse Generator ........................................................................... 69 3.5.3 Demodulation Drive Amplifier .................................................... 70 3.5.4 Low Pass Filter............................................................................ 71 Chapter 4 UWB Receiver Integration and Performance ..................................... 72 4.1 Coherent Receiver Implementation and Performance ............................ 72 4.1.1 Coherent Receiver Integration ..................................................... 72 4.1.2 Simulated Performance of the Coherent Receiver ........................ 74 4.2 Non-Coherent Receiver Implementation and Performance .................... 76 4.2.1 Non-Coherent Receiver Integration ............................................. 76 4.2.2 Measured Performance of the Non-Coherent Receiver................. 76 4.3 Layout Considerations........................................................................... 79 Chapter 5 Conclusions and Future Directions..................................................... 81 5.1 Conclusions........................................................................................... 81 5.2 Future Directions................................................................................... 82 Bibliography...................................................................................................... 83 vi Appendix A Layout of the Coherent Receiver Chip............................................ 94 Appendix B Die Micrograph of the Non-Coherent Receiver chip....................... 95 Appendix C Publications ................................................................................... 96 vii Summary This thesis focuses on receiver systems and CMOS integrated circuits design for Ultra-Wideband (UWB) communication. Two modulation schemes for UWB communication and corresponding receiver architectures are proposed. They are the correlator based BPSK coherent receiver capable of high transmission rate and good sensitivity, and the pulse OOK non-coherent receiver with low complexity due to elimination of synchronization. Several building blocks including multiplier, VGA, integrator and comparator for UWB receiver are proposed and implemented in a 0.18-µm CMOS technology. The multiplier has achieved a -3 dB bandwidth larger than 7 GHz and maximum gain larger than 13 dB. With a DC-offset suppression feedback loop, the VGA has more than 15 dB offset suppression, 45 dB gain variation range, and 178 MHz -3 dB bandwidth. The integrator employs Gm − C − OTA structure to obtain unit gain frequency of around 1 GHz and low -3 dB bandwidth of less than 1 MHz. It can perform the integration on narrow pulses within 1ns and hold for 10 ns with less than 3% discharge error. A comparator with 90 mV hysteresis and 400 ps propagational delay is designed. viii Based on the proposed receiver architectures and building blocks as well as a low noise amplifier, a demodulation drive amplifier, a lowpass filter and a local pulse generator designed by group members, a coherent and a non-coherent UWB receivers are implemented. The coherent receiver achieves 100 MHz data transmission rate, 80 dB gain and -80 dBm sensitivity in simulation. The non-coherent receiver has a measured transmission rate up to 50 MHz, 70 dB gain and -65 dBm sensitivity. ix List of Tables Table 1: Summary of Simulated Coherent Receiver Performance................ 75 Table 2: Summary of Non-Coherent Receiver Performance......................... 79 x List of Figures Fig. 1. 1: FCC Spectral Mask for UWB Communication Systems ................. 2 Fig. 1. 2: Typical UWB monocycle pulse signal. ........................................... 4 Fig. 2.1: Direct Conversion Receiver Architecture………………………... 8 Fig. 2.2: Generation of DC-offsets in Direct Conversion Receiver………... 10 Fig. 2.3: A simple DS-UWB receiver architecture…………………………. 11 Fig. 2.4: DS-UWB receiver architecture employing correlators and RAKE. 12 Fig. 2.5: Autocorrelation DS-UWB receiver architecture………………….. 13 Fig. 2.6: DS-UWB receiver architecture employing matched filter………... 14 Fig. 2.7: Antipodal (BPSK) Modulation for DS-UWB…………………….. 15 Fig. 2.8: Structure of an analog UWB correlator…………………………... 15 Fig. 2.9: Output SNR degradation (dB) when the timing error becomes larger……………………………………………………………………17 Fig. 2.10: The relation of the correlation function and the correlation time.. 18 Fig. 2.11: Sinusoidal template overlapped with the Gaussian impulse…….. 19 Fig. 2.12: System architecture of coherent UWB receiver for BPSK modulation……………………………………………………………...19 Fig. 2.13: Non-coherent transceiver system with pulse OOK modulation… 22 Fig. 2.14: Modulation and Demodulation: (a) Binary modulation signal (b) UWB pulse train (c) Modulated signal (d) Squared signal (e) Lowpass filtered signal…………………………………………………………... 22 xi Fig. 3.1: Principle of transconductance multiplier........................................ 27 Fig. 3.2: Four-quadrant multiplier architecture using single-quadrant multipliers. .......................................................................................... 27 Fig. 3.3: Four-quadrant multiplier architecture using square-law devices..... 28 Fig. 3.4: Type I transconductance multiplier topology. ................................ 30 Fig. 3.5: Type II transconductance multiplier topology. ............................... 30 Fig. 3.6: Type III transconductance multiplier topology. .............................. 31 Fig. 3.7: Proposed multiplier for UWB receiver. ......................................... 33 Fig. 3.8: Bandwidth and gain of the multiplier from RF input to output....... 36 Fig. 3.9: DC transfer characteristic of the multiplier from RF input to output. ............................................................................................................ 36 Fig. 3.10: Bandwidth and gain of the multiplier from LO input to output. ... 37 Fig. 3.11: DC transfer characteristic of the multiplier from LO input to output. ............................................................................................................ 37 Fig. 3.12: Transient simulation of the multiplier. ......................................... 38 Fig. 3.13: Measured multiplier performance................................................ 38 Fig. 3.14: Gain control by vary loading or bias current. ............................... 41 Fig. 3.15: AC-coupling to block DC-offset. ................................................. 43 Fig. 3.16: DC-offset subtraction technique. ................................................. 43 Fig. 3.17: Analog feedback technique: (a) Conceptual diagram. (b) Frequency response. ............................................................................ 45 Fig. 3.18: Block Diagram of the VGA. ........................................................ 46 Fig. 3.19: Schematic of VGA core circuits. ................................................. 46 Fig. 3.20: VGA core circuits with DC-offset suppression loop. ................... 48 Fig. 3.21: Frequency response of the VGA.................................................. 50 Fig. 3.22: Frequency response of an integrator. (a) ideal case. (b) practical implementation.................................................................................... 52 Fig. 3.23: Five common integrator structures. ............................................. 53 Fig. 3.24: Two types of capacitor connection............................................... 55 xii Fig. 3.25: The chosen integrator structure: Gm − C − OTA structure. .......... 58 Fig. 3.26: Equivalent model of the Gm − C − OTA integrator structure....... 59 Fig. 3.27: Proposed integrator structure with feedforward path.................... 61 Fig. 3.28: The schematic of transconductor used in the integrator................ 62 Fig. 3.29: The schematic of OTA used in the integrator. .............................. 63 Fig. 3.30: Frequency response of the integrator. .......................................... 65 Fig. 3.31: Transient Simulation of the integrator.......................................... 65 Fig. 3.32: The measured integrator response to a pulse input. ...................... 66 Fig. 3.33: Schematic of the comparator. ...................................................... 67 Fig. 3.34: The hysteresis characteristic of the comparator. ........................... 67 Fig. 3.35: Schematic of the UWB LNA. ...................................................... 69 Fig. 3.36: Schematic of the differential pulse generator without buffers....... 69 Fig. 3.37: Schematic of the demodulation drive amplifier............................ 70 Fig. 3.38: Schematic of the low pass filter. .................................................. 71 Fig. 4.1: The implemented coherent UWB receiver. .................................... 73 Fig. 4.2: Timing of clocks for pulse generator and integrator. ...................... 73 Fig. 4.3: Transient simulation results of the coherent receiver...................... 74 Fig. 4.4: The implemented coherent UWB receiver. .................................... 76 Fig. 4.5: Measured real time waveforms of data patterns. (Above: transmitted data pattern, Middle: modulated pulse signal, Below: demodulated and recovered pattern)................................................................................ 78 xiii List of Symbols and Abbreviations Symbols v1 (t ) Input of multiplier v2 (t ) Input of multiplier Id Bias current of MOSFET X, Y Bias of multiplier input x, y Small signal at multiplier input Vgs Gate-source voltage of MOSFET VT Threshold voltage of MOSFET Vds Drain-source voltage of MOSFET K Transconductance parameter of MOSFET µ0 Mobility of MOSFET Cox Unit gate capacitance of MOSFET W Width of MOSFET L Length of MOSFET Io Output current xiv Vout Output voltage Z out Output impedance VCtrl Control voltage Av Voltage gain Gs Transconductance of circuits Rd Load impedance gm Transconductance of MOSFET ω− sdB _ VGA Bandwidth of the VGA RL Load resistor ω− sdB _ FB Bandwidth of the feedback loop g ma , g mb Transconductance of MOSFETs in VGA Q Quality factor of low pass filter ωT Unit gain frequency of the VGA core ADC DC gain of amplifier ω0 -3dB bandwidth of amplifier ωu Unit gain frequency of the integrator ω−3dB -3dB band width of amplifier AGm DC gain of transconductor Gm _ Gm Transconductance of transconductor Ro _ Gm Output resistance of transconductor Gm _ OTA Transconductance of OTA AOTA DC gain of OTA xv C2 , C1 Equivalent miller capacitors in integrator C p _ Gm Parasitic capacitance of transconductor C p _ OTA Parasitic capacitance of OTA C gm Equivalent capacitor in transconductor COTA Equivalent capacitor in integrator CCM Capacitor in common mode feedback loop RCM Resistor in common mode feedback loop Abbreviations ADS Advanced Design System AC Alternating Current BER Bit Error Rate BPSK Bi-Phase Shift Keying CDMA Code-Division Multiple Access CMOS Complementary Metal-oxide semiconductor COB Chip-On-Board CSM Chartered Semiconductor Manufacturing DA Driver Amplifier DAC Digital-to-Analog Converter DC Direct Current xvi DCR Direct Conversion Receiver DDA Demodulation Driving Amplifier DS-UWB Direct-Sequence UWB DSP Digital Signal Processing ESD Electrostatic Discharge GSG Ground Signal Ground FCC Federal Communication Committee IF Intermediate Frequency I/Q In-phase/Quadrature LNA Low Noise Amplifier LO Local Oscillator LPF Lowpass Filter MOS Metallic Oxide Semiconductor MOSFET Metallic Oxide Semiconductor Field Effect Transistor MAC Media Access Control NMOS N-type MOS OOK On-Off Keying OTA Operational Transconductance Amplifier PG Pulse Generator PLL Phase Locked Loop PPM Pulse Position Modulation PSRR Power Supply Rejection Ratio xvii RAKE RAKE receiver RF Radio Frequency RX Receiver SAW Surface Acoustic Wave device SFDR Spurious-Free Dynamic Range SNR Signal to Noise Ratio SRD Step Recovery Diodes THD Total Harmonic Distortion UWB Ultra-Wide Band VGA Variable Gain Amplifier WPAN Wireless Personal Area Network xviii Chapter 1 Introduction 1.1 Background and Motivation 1.1.1 Overview of Ultra-Wideband System Ultra wideband (UWB) systems are a new wireless technology capable of transmitting data over a wide frequency spectrum with very low power and high data rates. Among the possible applications, UWB technology may be used for high speed data communication systems, vehicular and ground penetrating radars, and imaging systems. One of its most promising application areas is Wireless Personal Area Network (WPAN), in which UWB technology is envisioned to replace almost every cable at home or in an office with a wireless connection that features hundreds of megabits of data per second [1]. Although the UWB standard for high data rate communication (IEEE 802.15.3a [2]) has not been completely defined, most of the proposed applications are allowed to transmit in a band between 3.1 – 10.6 GHz. The federal 1 Communication Committee (FCC) has defined the spectral mask for UWB indoor communication systems, as shown in Fig.1.1. According to FCC’s regulation [3], UWB transmission is defined as the occupied fraction bandwidth > 20 % or larger than 500 MHz of absolute bandwidth. The benefit of UWB can be explained by Shannon’s channel capacity formula as follow: Capacity = BW ⋅ log 2 (1 + SNR ) (1.1) It shows that the capacity increases with the bandwidth linearly, but with signal power only logarithmically. Thus the UWB systems operating with very low signal power level can offer much more capacity compared to conventional narrowband systems. Fig. 1.1: FCC Spectral Mask for UWB Communication Systems [4]. 2 There are two main categories of UWB signaling schemes: Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) [4] based scheme and Direct-Sequence UWB (DS-UWB) [5] [6] [7] based scheme. The former divides the whole UWB spectrum into sub-bands with bandwidth of several hundred of Megahertz, and in each band a conventional carrier based approach is used. The latter is a carrier-less impulse radio based system in nature, in which either very narrow impulse signals occupying the whole UWB frequency band (3.1 – 10.6 GHz) can be used, or alternatively several types of impulse signals with different widths can be used, each occupying a sub-band of the whole UWB spectrum [2]. In this thesis, only impulse radio type UWB (DS-UWB) communication system is discussed. The typical UWB impulse signal is a Gaussian monocycle pulse, which is the second order derivative of Gaussian function as shown in Fig.1.2. The Gaussian monocycle pulse signal can be expressed mathematically as [8]: 2 2  t    t   PG ( t ) = AG 1 −  − 0.35   exp  −0.5  − 0.35     σ     σ  (1.2), where σ is a coefficient related to the pulse’s width, and AG is a amplitude scaling factor. 3 Fig. 1. 2: Typical UWB monocycle pulse signal. 1.1.2 Motivation Implementation of low cost UWB transceiver integrated circuits is a key success factor for UWB communication systems to be widely adopted. The UWB receiver chip design is particularly challenging in that it must provide sensitivity lower than -80 dBm and consume low power to enable longer battery life. The impulse radio type UWB receiver is quite different from conventional carrier based wireless receivers. Building blocks which are common in carrier based receiver system, such as local oscillators and channel select bandpass filters, are not present in an impulse radio type UWB (DS-UWB) receiver, and almost all of conventional receiver architectures can not be directly applied to DS-UWB receivers. As a result, innovations on novel system architecture as well as new circuits techniques are needed. In this thesis various key building blocks of impulse radio type UWB wireless 4 receivers such as multiplier, integrator, VGA and comparator are investigated and two UWB receiver systems are built in 0.18 µm CMOS technology based on the proposed building blocks and some other available circuit blocks. The two receivers achieve transmission rates of 100 Mbps and 50 Mbps respectively, and sensitivity of -85 dBm and -65 dBm respectively. The goal is to solve several critical problems in DS-UWB receiver design such as correlator design and DC-offset suppression, and to use simulation and experimental results to verify the feasibility of integrated UWB receiver solution in low cost CMOS technology. 1.2 Organization of the Thesis In chapter 2, conventional receiver architectures are briefly reviewed. The modulation schemes for UWB impulse radio such as Pulse Position Modulation (PPM), pulse On-Off Keying (OOK) Modulation and Bi-Phase Shift Keying (BPSK) Modulation are discussed. Based on the adopted BPSK and Pulse OOK modulation schemes, the correlator based coherent UWB receiver architecture and the self-synchronized non-coherent UWB receiver architecture are proposed. Chapter 3 concentrates on design of UWB receiver building blocks for ultra-wideband application and their performance. Blocks including multiplier, integrator, VGA and comparator are discussed. Blocks designed by group members are briefly introduced. In chapter 4, a coherent UWB receiver and its simulation results are described. The measurement of a non-coherent UWB receiver integrated by other team 5 member is performed and the results are presented. The two versions of receiver ICs are based on building blocks described in Chapter 3. Conclusions from this work are given in Chapter 5 along with suggestions for future work. Appendix of Chapter One: Publication List P1: Yuanjin Zheng, Yan Tong, Yongping Xu, Wooi Gan Yeoh, "A CMOS UWB Transceiver for WPAN,” IEEE Radio Frequency Integrated Circuits Symposium, Long Beach, CA. United States, June 2005. P2: Yan Tong, Yuanjin Zheng, Yongping Xu, "A Coherent UWB Receiver IC System for WPAN IEEE Application,” International Ultra-Wideband, Zurich, Switzerland, September 2005. 6 Conference on Chapter 2 UWB Receiver Architectures This chapter deals with UWB receiver architectures. The first section briefly reviews the direct conversion receiver architecture for conventional wireless communication systems. The second section proposes two DS-UWB modulation schemes together with their corresponding receiver architectures used in this project. 2.1 Overview of Receiver Architectures 2.1.1 An Overview of Direct Conversion Receiver Architecture A radio receiver architecture strongly depends on its modulation scheme and system requirements such as carrier frequency, sensitivity, selectivity, linearity, noise, as well as constraints of power consumption and numbers of off-chip components. Since the modulation scheme of an impulse based UWB system is significantly different from the conventional systems, the architecture for 7 DS-UWB receiver should also be different. However, in DS-UWB systems, modulated Gaussian pulse signals are correlated and demodulated like in direct conversion receivers, since in both cases multiplication of two signals in the same or nearby frequency range are involved [9]. As a result, the direct conversion receiver is discussed for better understanding of UWB receiver architecture and related design issues. The typical block diagram for a Direct Conversion Receiver (DCR) is shown in Fig. 2.1. In this architecture, both IF and image-rejection filters are eliminated compared to superheterodyne architecture. The entire RF spectrum is translated directly to the baseband since LO and RF signals are at the same frequency. Compared to the commonly used superheterodyne receivers, direct conversion receivers are more suitable for the high level integration due to the elimination of IF SAW filters [10]. Besides, the problem of image rejection is circumvented since the IF is zero [11]. However, a direct conversion receiver has several drawbacks which either do not exist or are not as serious in other receivers. Fig. 2.1: Direct Conversion Receiver Architecture. 8 z DC-offsets Perhaps this is the most serious problem in direct conversion receiver. Because of capacitive and substrate coupling and, the leakage signal of LO appears at inputs of the LNA and the mixer. This leakage is mixed with the LO signal, thus producing a DC component at the output of the mixer (shown in Fig. 2.2 (a)). Similarly, a large interferer may leak from LNA or mixer inputs to LO thus also producing a DC component (shown in Fig. 2.2 (b)). This DC-offset signal can be amplified by a following VGA to considerably large amplitude (if direct connections are used between cascaded stages) and thus corrupt the desired signal and saturate the following stages [12]. Since the downconverted signal is in the baseband near DC, it is much more difficult to remove the offset component from the desired signal using a bandpass filter in the direct conversion receiver than in superheterodyne receiver. Various DC-offset canceling techniques have been employed in integrated direct conversion receiver designs [12] [13]. (a) 9 (b) Fig. 2.2: Generation of DC-offsets in Direct Conversion Receiver. (a) LO leakage. (b) Interferer leakage. z I/Q-Mismatch In a direct conversion receiver the I/Q paths separate at a much higher frequency than that in a superheterodyne receiver, the 90 degree phase shift of the LO is subjected to a severe phase error problem [12]. However, in a DS-UWB receiver quadrature demodulation is not used, so this problem does not exit. z Flicker Noise Since the downconverted spectrum is located around zero frequency and the signal level at the output of mixer is in the range of only tens of microvolts due to the limited gain provided by the LNA and mixer, the flicker noise of the devices substantially corrupts the desired signal, a severe problem in MOS implementations. z Even Order Distortion Since in a direct conversion receiver the desired signal after the mixer is around zero frequency, any two adjacent strong RF interferers will generate a low 10 frequency distortion to the desired signal in the presence of even-order distortion. z LO leakage In addition to introducing DC offsets, leakage of the LO signal to the antenna radiates and thus creates interference in the band of other receivers. To avoid such interference, the signal level of the radiated LO leakage should be kept as low as -50 to -80 dBm. 2.2.2 DS-UWB Receiver Architectures in the Literature Compared with carrier-based receiver system, architectures for DS-UWB receivers are much simpler. Fig. 2.3 shows a simple DS-UWB receiver architecture [16], which consists of only four blocks including baseband. No matter what modulation scheme is adopted, the received signals are amplified by the LNA and VGA and converted to the digital domain by the ADC, and then the demodulation is performed in the baseband. Despite the simple architecture, however, the ADC should be able to sample and digitize the received signal at least at the Nyquist rate of several Gigahertz, which is beyond 10 GHz and is not feasible for IC implementation. Fig. 2.3: A simple DS-UWB receiver architecture. Some more complicated DS-UWB receiver architectures also appear in the literature. Fig. 2.4 shows a UWB receiver employing correlators and RAKE 11 receiver [17]. In this architecture each RAKE branch correlates the receiver pulse and a template pulse with different delay. An adaptive algorithm is used to determine the optimum values for coefficients c1 , c 2 …etc, in order to mitigate the multipath effects and obtain maximum SNR. This architecture has much better performance than the one shown in Fig. 2.3, however, at the cost of significantly higher system complexity. ∫ •dt vm (t − τ 1 ) ∫ •dt r (t ) vm (t − τ 2 ) ∑ ym ∫ •dt vm (t − τ L ) Fig. 2.4: DS-UWB receiver architecture employing correlators and RAKE. In order to reduce the system complexity and to avoid an ADC sampling rate beyond 10 GHz, receiver architectures without RAKE, template generator and timing circuits are explored [20] [21]. Fig. 2.5 shows an Autocorrelation Receiver for DS-UWB [20]. In this architecture, two pulses per symbol are received with a chosen delay τ between them. The receiver delays the first pulse by the delay τ , multiplies it with the second pulse and integrates the result over one delay length, 12 which in fact correlates the two pulses. Using a NRZ modulation, the information can be encoded as the polarity of the second pulse, which determines the polarity of the correlation value. Alternatively, it is also possible to use the pulse for the previous symbol as the reference and send only one pulse for each symbol, resulting in differential coding. Although this architecture is quite simple, however, it is very difficult to implement a delay cell with high linearity, constant phase delay over the whole UWB band, low phase noise and accurate delay time. Fig. 2. 5: Autocorrelation DS-UWB receiver architecture. Another DS-UWB receiver architecture with low system complexity is shown in Fig. 2.6 [21]. In this architecture, a matched filter is used and its sampled output is exactly the value obtained using the optimal receiver approach. The frequency response of this matched filter is designed to match the conjugate of the frequency spectrum of the impulse signal. Since the exact pulse location is unknown, in each period a square-law device and a integrator average the matched filter output so that the averaged correlation value can be sampled at a fixed time point. The problem of this architecture is that, the matched filter design is a great challenge to circuit implementation. 13 ∫ Fig. 2.6: DS-UWB receiver architecture employing matched filter. 2.2 Proposed UWB Modulation Schemes and Receiver Architectures In general, the impulse radio UWB system directly modulates an impulse-like waveform with sharp rising and falling edges, which occupies several GHz of bandwidth. The information can be modulated by several different techniques: the pulse can be modulated with ±1 amplitude variations (BPSK or antipodal signaling) or ±M variations (M-ary pulse amplitude modulations or M-PAM), or turning the pulse on and off (known as on/off keying or OOK), or dithering the pulse position (known as pulse position modulation or PPM). 2.2.1 Antipodal Modulation and Coherent Receiver Architecture z Modulation Scheme Antipodal (BPSK) is perhaps the most straightforward modulation scheme for impulse radio type UWB wireless communication systems. The digital 14 information +1 and -1 are represented by Gaussian pulses with positive and negative polarities respectively, as shown in Fig. 2.7. In each time period one Gaussian pulse is sent so that one information bit is transmitted. Fig. 2.7: Antipodal (BPSK) Modulation for DS-UWB The demodulation of BPSK modulated signal involves an analog UWB correlator. The UWB correlator consists of an analog multiplier and a time-domain integrator, as shown in Fig. 2.8. Fig. 2.8: Structure of an analog UWB correlator. The correlator generates the correlation value between the received impulse signals and a local template signals in each time period. The template signal is a perfect Gaussian impulse signal generated by the receiver. The output of a UWB correlator can be described mathematically as: 15 Vout (τ ) = K ⋅ ( n +1)T ∫ r (t ) ⋅ v(t − τ )dt = K ⋅ Rrv (τ ) (2.1) nT where K is a gain factor, r (t ) is the received signal, v(t ) is the template signal, τ is the timing error between the received signal and the template, and T is the time period (chip duration). The output correlation value is sampled and reset to zero at t = nT , t = (n + 1)T , etc. The noise at the input of the correlator, which can be considered as white and Gaussian and with variance of N 0 [14], is also correlated with the template signal. The noise component of the correlator output is a zero-mean Gaussian random variable N , with a variance of E ( N 2 ) = N 0 ⋅ Rvv (0) (2.2) where Rvv (τ ) is the auto-correlation of the template signal v(t ) . Therefore the signal-to-noise ratio of the correlator output is Vout 2 (τ ) K 2 Rrv 2 (τ ) = SNR = E( N 2 ) N 0 Rvv (0) (2.3) which is a function of time error τ . When the timing error is zero, the maximum SNR can be obtained [14]. If the incoming signal is a scaled version of template, which can be expressed as r (t ) = h ⋅ v(t ) , (2.4) (in most practical cases h  1 ), then the maximum SNR can be expressed as SNRMAX = K 2 h2 ⋅ Rvv (0) . N0 (2.5) The output SNR normalized by the noise and signal power versus timing error is plotted in Fig. 2.9 (Gaussian impulses covering the whole UWB band 3.1 ~ 10.6 16 GHz are used to plot this curve). It is clear that accurate alignment between the incoming signal and the template signal is crucial for successful reception in this modulation scheme [14]. Fig. 2. 9: Output SNR degradation (dB) when the timing error becomes larger. Fig. 2.10 shows the normalized output correlation versus the correlation time, assuming that the timing alignment is ideally achieved. The correlator requires at least 0.6 ns to perform the correlation operation, for pulses occupying the whole UWB band. The correlation time is a fundamental limit to the maximum chip rate or the minimum period adopted, which should be much more than the required correlation time. The current proposals for IEEE 802.15a.3 standard set the maximum date rage as 480 Mbps, which translates to a time period of approximately 2.08 ns. 17 Fig. 2.10: The relation of the correlation function and the correlation time. Some other demodulation schemes employ sinusoidal template signals to correlate with incoming signals. As shown in Fig. 2.11, if the peak of a Gaussian impulse aligns accurately with the peak of a sinusoidal signal at the appropriate frequency, a maximum correlation value can also be attained. The advantage is that the sinusoidal LO signal is much easier to generate than the impulse templates, however, timing is a much more severe problem in such schemes and the correlation function is very sensitive to the LO frequency. Direct-Sequence Code-Division Multiple Access technique can be employed to further spread the spectrum of impulse signals as a mean of multiple accesses. In this case, certain set of orthogonal CDMA codes are used to modulate the pulse train. 18 Fig. 2.11: Sinusoidal template overlapped with the Gaussian impulse. z Coherent Receiver Architecture The proposed UWB receiver architecture for the antipodal/BPSK modulation scheme is shown in Fig. 2.12, which is a coherent receiver in nature. This type of UWB receiver requires accurate synchronization between transmitter and receiver clocks. [15] [16]. Fig. 2.12: System architecture of coherent UWB receiver for BPSK modulation. The receiver consists of a low noise amplifier (LNA), an analog demodulator (correlator), and an Analog-to-Digital Converter (ADC). The weak received pulses 19 are a BPSK modulated pulse train. The LNA amplifies the incoming pulses and subsequently the pulses are correlated with the local pulse templates in the multiplier and integrator. The integrator outputs a constant correlation level in each period for A/D conversion. A discharging clock sets the integrator output to zero at the end of each period, so that the output correlation values in the adjacent periods do not affect with each other. The variable gain amplifier (VGA) is inserted between the multiplier and the integrator to maintain a large dynamic range. To address the DC-offset associated with the direct-conversion-like architecture, the VGA gain stage employs a feedback loop to suppress the offset. The ADC is operating under a symbol-by-symbol sampling rate. The clocks for the integrator, ADC and local pulse generator are provided by a clock generator (PLL). In this project a 100 Mbps transmission rate is adopted for the coherent receiver system, so all the clocks are at the frequency of 100 MHz. Synchronization is implemented with a specific function block. Control signals for various blocks such as VGA, PLL and integrator as well as various backend DSP operations such as equalization, de-spreading and decoding are provided by the baseband processor. In this receiver architecture the most severe problem is the DC-offsets. The coherent UWB receiver architecture is similar to direct conversion receiver [9], in that the analog multiplier in the correlator multiplies two identical impulse signals so that the output of mixer has significant DC and low frequency components. As a result, similar to the case in the direct conversion receiver, DC-offsets due to 20 leakage and self-mixing overlap with the desired signals. Besides, various stages are connected with each other directly without coupling capacitors, so mismatch between differential paths in each stage also contributes to the DC-offset. Since the integrator has a very large DC gain, a small amount of DC-offset at the multiplier output can be amplified to a significant level thus blocking the ADC sampling circuits. 2.2.2 On-Off Keying Modulation and Non-Coherent Receiver Architecture Although coherent demodulation can achieve very high transmission rates, it needs precise timing synchronization between transmitter and receiver, which is a challenge and greatly increases the system complexity [18]. An alternative solution is non-coherent demodulation, which usually needs the special devices such as Step Recovery Diodes (SRD) to generate pulses and detect the pulses [19]. A lot of effort has been devoted to non-coherent demodulation techniques for impulse based UWB system [20] [21], however, the system complexities of these architectures are still not low enough to enable low power implementations. In this project, a pulse On-Off Keying (OOK) modulation and non-coherent demodulation schemes are proposed, as shown in Fig. 2.13 and Fig. 2.14. Although no synchronization system and no special diode devices are required for this architecture, a considerably high data rate transmission can still be attained. 21 Fig. 2.13: Non-coherent transceiver system with pulse OOK modulation. Fig. 2.14: Modulation and Demodulation: (a) Binary modulation signal (b) UWB pulse train (c) Modulated signal (d) Squared signal (e) Lowpass filtered signal Fig. 2.13 shows the block diagram of the proposed impulse based UWB transmitter and receiver. The transmitter consists of a pulse generator, a pulse 22 modulator, and a driver amplifier (DA). The receiver consists of a low noise amplifier (LNA), a multiplier, a demodulation driving amplifier (DDA), a variable gain amplifier (VGA), and a lowpass filter (LPF). The baseband processor provides control signals to various blocks including clock generator circuits, and it performs various other functions such as Media Access Control (MAC), coding and decoding. The transmitter generates on-off amplitude modulated signal (Fig. 2.14c) by multiplying a UWB monocycle pulse train (Fig. 2.14b) with a binary information data waveform (Fig. 2.14a). The modulated signal is emitted by the antenna after it is amplified by the DA. The UWB pulse used in this system occupies the FCC low band (3.1 ~ 6 GHz) spectrum and repeats in a frequency >200 MHz. The binary data rate is up to 50 Mbps. To ensure the reliable demodulation in the receiver, the pulse repetition rate is much higher than the binary data rate (>4:1). This scheme uses UWB pulses to over-sample the modulation data. In other wordd, the oversampled pulse sequence is in an ultra wide RF frequency band, thus it can be emitted by the antenna directly and transmitted in a very low power density. The received weak pulse sequence is amplified by the LNA and subsequently fed to the two input ports of a multiplier concurrently, resulting in a squared operation (Fig. 2.14d). This square operation de-spreads the pulse and thus has a high processing gain. The squared output is then amplified by the DDA to further improve the demodulation signal to noise ratio (SNR). The VGA is used to 23 maintain a large dynamic range. The LPF is used to extract the envelope of the squared signal. The extracted envelope can be regarded as the recovery of the transmitted information data (Fig. 2.14e). This demodulation is non-coherent since it recovers the data only through the received pulse sequence itself, so that complex synchronization circuits are avoided. In this architecture since the weak signal from LNA multiplies with itself in the multiplier, it is desired that LNA and multiplier have a large gain. However, it is difficult for the LNA to achieve more than 20 dB gain with acceptable noise figure in ultra-wideband application. Besides, the multiplier usually has little gain for a weak signal such as the signal at the LNA output. As a result, the sensitivity of the non-coherent receiver is worse than that of a coherent UWB receiver described in the previous section. Besides, since the timing is achieved with multiplication of the same incoming signals in two different paths, it is crucial that the phase delays in these two paths are exactly the same. Otherwise, the SNR of the demodulated signal and the shape of exacted envelope signal will be significantly deteriorated. 24 Chapter 3 UWB Receiver Building Blocks Design Once the architecture has been specified, the receiver system must be realized in a circuits form. In this chapter, the design of several building blocks for impulse based UWB receiver is proposed, including a multiplier, a VGA, an integrator, a lowpass filter and a comparator. Besides, other building blocks necessary to the receiver implementation are briefly reviewed. In this thesis, circuits are implemented for an impulse radio type UWB receiver operating in the low band of UWB spectrum, i.e. 3.1 – 6 GHz. The circuit simulation is performed in Agilent Advanced Design System (ADS) environment and is based on 0.18 µm CMOS device models provided by the Chartered Semiconductor Manufacturing (CSM) and developed in-house at the Institute of Microelectronics, Singapore (IME). The supply voltage for all circuits is 1.8V. 25 3.1 Multiplier 3.1.1 CMOS Transconductance Analog Multiplier The analog multiplier is one of the most common building blocks for analog signal processing and is extensively explored in the literature [24] - [31]. Analog multipliers used in RF system are also widely reported [32] - [35], including in UWB system [33]. Many kinds of multiplier topologies in the literature, including conventional four-transistor multipliers and Gilbert cell based multipliers, can be categorized into transconductance multipliers [22] [23]. Since UWB correlation operates with large bandwidth, high conversion gain and small mismatch are required, a suitable CMOS transconductance multiplier topology should be selected to meet these requirements. CMOS transconductance multipliers have been extensively studied in the literature since 1980s. Reference [23] provides a detailed list of papers on CMOS transconductance multipliers. The principle of transconductance multipliers is shown in Fig.3.1. In this type of analog multiplier, two input signals, v1 (t ) and v2 (t ) are applied to a nonlinear device, which can be characterized by a high order polynomial function. This polynomial function generates terms like v12 (t ) , v22 (t ) v13 (t ) , v23 (t ) , v12 (t )v2 (t ) , v1 (t )v22 (t ) and many others besides the desired component v1 (t )v2 (t ) . After the input stage, terms other than the desired terms are cancelled using a nonlinearity cancellation circuits, thus only the desired term v1 (t )v2 (t ) appears at the multiplier output. 26 vi (t ) = v1 (t ) + v2 (t ) io (t ) = kv1 (t )v2 (t ) io = a + bvi + cvi 2 + dvi 3 + ... Fig. 3. 1: Principle of transconductance multiplier. Among many reported circuits in the literature, only two nonlinearity cancellation methods for the four-quadrant multipliers are proposed. In both cancellation schemes, differential input and output signal are employed to obtain good linearity and power supply rejection ratio (PSRR). ∑ ∑ Fig. 3.2: Four-quadrant multiplier architecture using single-quadrant multipliers. The first cancellation scheme is shown in Fig. 3.2. In this scheme, each input device is a single-quadrant multiplier. This topology achieves signal multiplication and high-order and common mode components cancellation simultaneously based on the following equation: 27 [( X + x)(Y + y ) + ( X − x)(Y − y )] − [( X − x)(Y + y ) + ( X + x)(Y − y )] = 4 xy (3.1) where X, Y represent the common mode levels of two inputs and x, y represent the small input signals. x+ y −x + y −x − y x− y (.) 2 x 2 + 2 xy + y 2 (.) 2 x 2 − 2 xy + y 2 (.) 2 x 2 + 2 xy + y 2 (.) 2 x 2 − 2 xy + y 2 ∑ 4xy ∑ Fig. 3.3: Four-quadrant multiplier architecture using square-law devices. Another cancellation scheme uses square-law devices as the nonlinear input stages (Fig. 3.3). It is based on the equation: (.) 2 {[( X + x) + (Y + y )]2 + [( X − x) + (Y − y )]2 } −{[( X − x) + (Y + y )]2 + [( X + x) + (Y − y )]2 } = 8 xy (3.2) MOS devices can be used to implement the four-quadrant multipliers based on (3.1) or (3.2). The simple MOS transistor model is expressed as I d = K [Vgs − VT − Vds V2 ]Vds = K [VgsVds − VTVds − ds ] , 2 2 for Vgs > VT , Vds < Vgs − VT Id = (3.3) K K [Vgs − VT ]2 = [Vgs2 − 2VT Vgs − VT2 ] , 2 2 for Vgs > VT , Vds > Vgs − VT 28 (3.4) for NMOS transistor in its linear and saturation regions, respectively. K = µ0Cox W and VT are the conventional notation for the transconductance and L the threshold voltage of the MOS transistor, respectively. The terms VgsVds in (3.3) can be used to implement the product terms in (3.1), and Vds2 in (3.3) or Vgs2 in (3.4) can be used to implement square terms in (3.2). Among various possible implementations of CMOS four-quadrant transconductance multipliers according to (3.1) and (3.2), several topologies have significantly superior performance than others in terms of gain, linearity, noise and mismatch sensitivity [26]. These topologies are shown in Fig. 3.4, Fig. 3.5 and Fig. 3.6, referred as type I, type II and type III multiplier in this thesis, respectively. In the type I topology shown in Fig. 3.4, the term VgsVds is used to implement the multiplication. The transistor M 1 operates in linear region while M 2 operates in the saturation region when proper bias voltage X and Y are provided [24]. Among these three types of multipliers, this topology has lowest gain, moderate mismatch sensitivity, lowest power consumption and good linearity. Besides, it is much more suitable to low voltage operation than the other two types of multipliers [23]. 29 Fig. 3.4: Type I transconductance multiplier topology. In the type II topology shown in Fig. 3.5, the term Vgs2 is used to implement the multiplication. All the transistors operate in the saturation region. Source followers M s are used to inject input signal to the source terminals of square-law function devices M 1 . Among these three types of multipliers, this topology has largest gain, best mismatch sensitivity and good linearity [23]. Fig. 3.5: Type II transconductance multiplier topology. In the type III topology shown in Fig. 3.6, the term Vgs2 is also used to implement the multiplication. This topology is similar to type II except that a separate source follower is provided to each cross-coupled transistor and each 30 source follower shares the same tail current with its corresponding cross-coupled transistor. Among these three types of multipliers, this topology has moderate gain, moderate mismatch sensitivity and worst linearity [23] [25]. Besides, the power consumption of this type of multiplier is significantly larger than the other two topologies [23]. Fig. 3.6: Type III transconductance multiplier topology. A comparison can be made regarding to the suitability of these three multiplier topologies to the UWB correlation application. In a UWB receiver system, it is highly desired that the multiplier has large conversion gain to amplify the very weak desired signal and to overcome the noise, especially in the non-coherent UWB receiver system [20] [21]. Linearity is also of importance since it has impacts on bit error rate (BER) as well as the accuracy and speed of synchronization in the coherent receiver system. Because of the large gain required in the whole receive path, the mismatch induced DC-offset is a critical problem. In fact, because of the low duty cycle of the impulse radio system, the mismatch-induced DC-offset may be even more severe than that induced by 31 self-mixing. As a result, mismatch sensitivity is also one of the most important issues. According to these criteria, the type II topology is the most suitable choice to implement the multiplier in UWB receiver. Although circuits with low power consumption (like type I multiplier) are always desired, however, there is a trade-off here between power consumption and other requirements. Since the multiplier is not the most power-hungry block in the receiver system, it is still reasonable to choose a topology with mediate power consumption while achieving best performance in other criteria. Besides, although the type I topology can operate under lower supply voltage, which translates to larger voltage headroom and signal swing under the same supply voltage, it is not a major consideration for the multiplier in UWB receiver since both its input and output signals do not have very large amplitude (in fact the RF and downconverted signals are very weak). The multiplier in a UWB receiver should also have very large bandwidth. It should be able to cope with two input signals occupying from 3.1 to 6 GHz spectrum or even higher and generate an output signal with a spectrum from DC to several Gigahertz, which is in sharp contrast to the conventional mixer whose output is centered at a narrow frequency band. The type I, II and III topologies have similar bandwidths because of the similar topologies and parasitic effects in the signal paths and similar dominant poles contributed by the output nodes. As a result of above discussion, type II transconductance multiplier is chosen for the UWB receiver. 32 3.1.2 Proposed Multiplier for Ultra-Wideband Receiver The proposed multiplier is shown in Fig. 3.7. It is a type II multiplier with a resistor and an inductor in series as load impedance in each output terminal. Conventional inductor peaking technique is used to enhance the bandwidth. Fig. 3.7: Proposed multiplier for UWB receiver. In the coherent architecture, the incoming pulses from the LNA are applied at the RF port, and the local pulse templates are applied at the LO port. (In this thesis, conventional term “LO” is used to refer the terminals for local generated impulses, although there is no “local oscillator” in the UWB receiver.) In the non-coherent architecture, the signals from the LNA are applied at both the RF and the LO ports. 33 The multiplier core consists of transistors M 1 to M 6 . According to the square law of MOS devices, the output current can be expressed as I o1 = K (Vgs1 + x − VT )2 + K (Vgs 3 − x − VT )2 and I o 2 = K (Vgs 2 − x − VT )2 + K (Vgs 4 + x − VT )2 (3.5) (3.6) Here x and y refer to the notations in Fig. 3.5. The differential output voltage can be expressed as Vout = Z out ( I o1 − I o 2 ) (3.7) Since Vgs1 = Vgs 2 , Vgs 3 = Vgs 4 and M 1 and M 3 share the same gate terminal, from (3.5), (3.6) and (3.7) the output voltage can be derived as Vout = 4 Kx(Vgs1 − VT ) − 4 Kx(Vgs 3 − VT ) = 4 Kx(Vgs1 − Vgs 3 ) = 4 Kx(Vs 3 − Vs1 ) (3.8) Because the two transistors M 5 and M 6 act as source followers, if ideal level shifts are performed, the signal variations at the gates of M 5 and M 6 should be the same as that at the sources. Since Vs1 = Vs 5 and Vs 3 = Vs 6 , the input voltage of y terminal is given by 2 y = Vs 6 − Vs 5 = Vs 3 − Vs1 (3.9) From (3.8) and (3.9), the output is expressed as Vout = 4 Kxy 34 (3.10) The inductors are added to resonate with the parasitic capacitors at the output nodes to increase the bandwidth [36]. In other words, a zero is created by adding the inductors and it cancels with the dominant pole. Extensive simulation is performed in Advanced Design System (ADS) to arrive at the optimal inductor value of 5.1 nH to obtain the largest possible bandwidth while avoiding severe overshoots at high frequency. This technique boosts the multiplier bandwidth from around 1 GHz (without inductors) to beyond 7 GHz (with inductors). If the inductors are not used, approximately 3 times more bias current should be used to achieve the same bandwidth. As a result, since the use of an inductor greatly increases the die area of the multiplier, there is a trade-off between die area (or cost) and power consumption in view of bandwidth requirement. As shown in Fig. 3.8, the -3 dB bandwidth from RF input ports to the output ports is 7.1 GHz, with conversion gain of 10.43 dB when 500 mV differential DC input is applied at LO input ports. The DC transfer characteristic of the RF input is shown in Fig. 3.9. The total harmonic distortion (THD) at 4 GHz for RF input is less than 0.7 % for a linear range of ± 70 mV, which is more than enough since the amplitude of LNA output is around 10 ~ 20 mV. 35 Fig. 3.8: Bandwidth and gain of the multiplier from RF input to output. Fig. 3.9: DC transfer characteristic of the multiplier from RF input to output. As shown in Fig. 3.10, the -3 dB bandwidth from LO input ports to the output ports is 8.4 GHz, with conversion gain of 13.6 dB when a 150 mV differential DC input is applied at RF input ports. The DC transfer characteristic of LO input is shown in Fig. 3.9. The total harmonic distortion (THD) at 4 GHz for LO input is better than 1% for a linear range of ± 325 mV, which is enough to deal with local impulses with peak amplitude of at most 310 mV (The amplitude of local impulse 36 depends on frequency and amplitude of the triggering clock) in the coherent receiver. Fig.3.10: Bandwidth and gain of the multiplier from LO input to output. Fig. 3.11: DC transfer characteristic of the multiplier from LO input to output. The transient simulation of the multiplier is shown in Fig. 3.12. RF pulse signals with peak amplitude of 16 mV and LO pulse signals with peak amplitude of 310 mV are applied to the inputs. The output signals show that the function of multiplication is correctly performed without significant distortion. 37 Fig. 3.12: Transient simulation of the multiplier. Fig. 3.13: Measured multiplier performance. The measured signals at multiplier output are shown at Fig. 3.13, together with its two inputs, which are output pulses of LNA. The amplitudes of two multiplier inputs are more than 20mV and the output has a swing larger than 60 mV. From Fig. 4.5, significant DC and low frequency components are extracted at the 38 multiplier output. However, from the figure, the measured bandwidth of the multiplier is not as large as the simulated one. The gates of two source followers are chosen as LO because the linear range of these two ports is much better than that at gates of the four cross-coupled transistors, while a LO signal has much larger swing than that of a RF signal. Another reason for this choice is that the source follower gates have much better LO isolation to the output ports than that of the cross-coupled transistors. The total current consumed by the multiplier is 5.8 mA. The bandwidth of the multiplier is over-designed to meet requirements of any DS-UWB system operating below 7 GHz. Depending on the specific bandwidth of input pulses, the power consumption can be further optimized. Since the load of the multiplier is the gate capacitance of input transistors of the following stage, the inductor value can be further adjusted in conjugation with the specific load value to achieve comparable performance to that without load. 3.2 Variable Gain Amplifier A variable gain amplifier (VGA) is discussed in this section. A DC-offset suppression loop is proposed to minimize the DC-offset at the VGA output. 3.2.1 General Consideration The sensitivity of the UWB receivers is around -65 ~ -80 dBm [37] [38], and most proposed UWB receivers have a receiver gain in the range of 50 ~ 80dB [39] 39 [40]. In this project, 80 dB dynamic range requirement is set for the receiver, which is much larger than the maximum input dynamic range of the ADC. In the case of UWB receiver, the optimal ADC resolution is 4 ~ 6 bits [41] [42], which translates to an input dynamic range of around 24 ~ 36 dB. If a UWB LNA with more than 15 dB switchable gain is employed as in [43] [44], the VGA is required to provide 45 dB additional gain control range to accommodate the ADC input to a suitable level thus facilitating the sampling. Although the spectrum of a signal at the multiplier spans from DC to more than one Gigahertz, however, in this project with the impulses occupying from 3.1 ~ 6 GHz range, most energy of the multiplier output is concentrated within the 150 MHz bandwidth. As a result, the VGA should have bandwidth from DC to at least 150 MHz. 3.2.2 Existing Gain Varying Techniques The gain varying techniques reported in the literature can be categorized into two classes: one is to use a programmable attenuator following a fixed gain amplifier [45] ~ [47], and the other one is to directly vary the gain of an amplifier. In this first method, although the fixed gain amplifier can be optimized for higher gain, however, for a gain varying range of 45 dB in the targeted design, an insertion loss of 45 dB will directly degrade the noise figure by the same extent. This degradation in noise figure corrupts the desired signal and decreases the dynamics range, thus is obviously not acceptable. As a result, the second method 40 is adopted in this design. There are several methods to vary the gain of an amplifier. As shown in Fig. 3.14, the two simplest methods are to vary either the bias current or the loading. Firstly, by tuning the loading of RL1 and RL 2 the gain is varied, but its common mode output voltage is also changed and thus affects the bias for the next stage. Besides, continuous control in gain variation is also difficult to achieve. The second method of gain varying is to tune the bias current I b [48] ~ [50]. However, when the signal is large, the bias should be set to a small value to obtain a small gain, so swing of the input devices is also reduced. This is opposite to the requirement of a VGA [51]. In addition, the common-mode output also depends on the gain. Since a MOSFET is a square law device, the bias current has to be varied as a square function of the gain, so this technique typically entails large power consumption [52]. Fig. 3.14: Gain control by vary loading or bias current. Thirdly, four-quadrant analog multipliers are widely used to implement gain variation [53] ~ [55]. This method usually has high gain and it does not have the 41 problem of common mode voltage variation. Thus it is well suited to application requiring large dynamic range and low noise. As the fourth approach, variable source degeneration is also commonly used to implement gain variation of an amplifier [56]. Since the source degeneration does not consume any additional current, no change in the bias current is necessary to achieve the gain variation if differential topology is used [45]. Besides, a differential pair degenerated by a MOSFET resistor operating in triode region has the advantage of good linearity [55]. 3.2.3 DC-Offset Cancellation Techniques As discussed in Chapter 2, DC-offset is a serious problem for UWB receiver and the VGA should suppress the DC-offset to avoid distortion and saturation. There are several DC-offset cancellation techniques in the literature. (1) AC-Coupling As shown in Fig. 3.15, the most straight forward method is to use AC-coupling between cascaded stages to block DC-offset [57] [58]. However, the coupling capacitors are usually of very large values and are not easy to integrate on-chip [59]. Besides, for signals with significant low frequency and DC energy, the useful signal is also attenuated to some extent [60], depending on the value of the coupling capacitor. 42 Fig. 3.15: AC-coupling to block DC-offset. (2) Baseband DSP Correction Another method to remove the DC offsets is to use digital signal processing (DSP) algorithms to cancel the offset in the digital domain after sampling and analog-to-digital conversion (ADC) [61] [62]. However, in this technique the stage before the ADC must have sufficient spurious-free dynamic range (SFDR) in order to accommodate the large DC offset. If the receiver chain is saturated by the offsets, this technique does not work. Besides, the additional algorithms implemented in the baseband processor significantly increase the overall die area and power consumption, compared with an analog DC-offset cancellation approach. Fig. 3.16: DC-offset subtraction technique. (3) Offsets Subtraction In the DC-offset subtraction approach (shown in Fig. 3.16), the offset is extracted by the baseband processor, temporarily stored and then subsequently subtracted from the baseband path [63]. Since the DC-offset is detected digitally, 43 this approach has certain SFDR requirements as in the DSP correction approach. It also requires an additional digital-to-analog converter (DAC), a device with considerable die size and power consumption. (4) Auto-Zero Technique This technique uses idle time between data bursts to measure the unloaded receiver intrinsic DC offset and subtract the measured value during the reception of the next burst. [48] [51]. However, this approach only works when the offset can be assumed relatively constant or to vary very slowly with time. Besides, measuring of the offset during idle time usually can not be accurate [63]. (5) Sub-Harmonic Mixers In this mixer topology, an out-of-band LO is used to reduce the LO radiation and to increase the isolation between RF and LO signal, thus reducing the DC-offset [52] [64]. (6) Analog Feedback Configuration This cancellation scheme use an analog feedback loop on the dc-coupled stages with as depicted in Fig. 3.17 (a) [65 [66]. The DC extractor block, which is essentially a g m − C integrator, proportionally converts the output offset voltage into offset current fed into the capacitor through a g m block. The parallel resistor represents the finite output resistance in the g m block. The integrated error voltage is subtracted from the input signal in the summer. The frequency response of the DC-offset cancellation scheme is shown in Fig. 3.17 (b). The advantage of this approach is that it does not incur any in-band loss for narrow band systems. 44 Another advantage is that varying the values of the resistor or MOS capacitor can easily alter and optimize the corner frequency of the high pass filter characteristics, which is directly related with the SNR degradation and settling time. However, in the prior art this technique usually involves sampling and switching circuits [67], which will introduce the problems of large noise, clock feedthrough and charge injection, and cannot operate continuously, thus are not suitable for high frequency application. Besides, in this technique additional calibration periods are needed [68], which would reduce the overall speed. Fig. 3.17: Analog feedback technique: (a) Conceptual diagram. (b) Frequency response. 3.2.4 Proposed VGA Circuits with DC-offset Suppression Loop and Simulated Performance The proposed variable gain amplifier consists of two identical VGA core 45 circuits directly connected together, as depicted as Fig. 3.18. The gain of each cell can be varied from 0 dB to 25 dB by adjusting the control voltage VCtrl . To achieve a minimum overall noise figure, when a small gain is desired, the gain of the second stage should be decreased first. However, in the case of large input signal and thus small gain, the noise requirement of the VGA is relatively relaxed, so for the simplicity one common controlled voltage is shared in this design. Fig. 3.18: Block Diagram of the VGA. ' VCtrl Fig. 3.19: Schematic of VGA core circuits. The VGA core is based on [56]. The schematic is shown in Fig. 3.19. 46 Source-degeneration is used to realize variable gain. M 3 and M 4 form the linear transconductance pair. M 5 and M 6 act as the active load to provide high gain. M 7 and M 8 are used to improve the linearity [56]. The common-mode feedback circuit consists of R1 , R2 and M 10 ~ M 13 . The gain of the VGA can be adjusted continuously from 0 dB to 17 dB through the source degeneration transistor M 14 . The gain of the VGA can be expressed as: Av = −Gs Rd gm g m + Gs (3.11) where g m , Gs and Rd represent the transconductance of the input transistor, the conductance of source degeneration transistor, and the load resistance, respectively. The conductance of source degeneration transistor can be expressed as: W Gs = µnCox  L   Vgs14 − VT 14 ( ) (3.12) Obviously, if g m >> Gs , Av can be rewritten as Av = −Gs Rd gm g m + Gs (3.13) W ≈ − µnCox  L   Vgs14 − VT Rd . 14 ( ) Therefore, Av is a linear function of Vgs14 , and the gain of the VGA can be linearly controlled by the gate voltage of M 14 . However, since the condition g m >> Gs does not perfectly hold, the gain control is not ideally linear. 47 Fig. 3.20: VGA core circuits with DC-offset suppression loop. The cascaded amplifiers have the effect of bandwidth shrinkage [36]. For the two stage amplifier, the shrinkage coefficient is n = 0.643 . To achieve a overall bandwidth of 178 MHz, each VGA stage should have a bandwidth of around 270 MHz. Taking possible process variation into consideration, the bandwidth for each stage is over designed as 280 MHz. A continuous time negative feedback loop [68] with a lowpass filter is designed together with the core circuits to suppress the DC offset while avoiding the undesired effects caused by sampling and switching circuits. As shown in Fig. 3.20, transistors M 1 and M 2 are working in triode region as two resistors. These two resistors together with C1 and C2 form two low-pass filters to pass DC and low frequency only so that the VGA gain in most of signal band is not affected except the gain at DC and very low frequency. As a result, the DC-offset is suppressed. Transistors M 3 and M 4 are used to convert the voltage feedback 48 signal to current, which is added to the source and drain nodes of the source degeneration transistor in the VGA core. The VGA without offset cancellation can be approximately modeled by a single-pole low-pass function as: A( jω ) = 1+ g ma RL jω (3.14) ω−3dB _ VGA The feedback path can also be modeled by a lowpass function with DC gain of one: B ( jω ) = 1+ 1 jω (3.15) ω−3 dB _ FB where ω −3dB _ VGA and ω−3 dB _ FB , are the -3 dB frequencies of the VGA core and the feedback path, respectively, and g ma is the transconductance of two input MOS transistors in VGA core. With the offset cancellation, the close-loop overall transfer function can be derived to be [68]: ω0 = (1 + g mb RL )ω−3dB _ VGAω−3dB _ FB ≈ ωT ω−3dB _ FB Q= (1 + g mb RL )ω−3dB _ VGAω−3dB _ FB ω−3 dB _ VGA + ω−3dB _ FB (3.16) (3.17) (3.18) where ωT is the unit-gain frequency of the main amplifier, RL is the load impedance at the output nodes, and g mb is transconductance of M 3 and M 4 . It is clear from (3.16) that the closed loop one stage VGA has a bandpass frequency 49 response. Fig. 3.21: Frequency response of the VGA. The frequency response of the VGA is shown in Fig. 3.21. The lower highpass cutoff frequency for DC offset rejection is 100 Hz with a transition band from 100 Hz to 20k Hz, and the higher lowpass cut off frequency is 178 MHz. The two-stage VGA is used to achieve large gain dynamic range from 0 dB to 45 dB. The DC-offset suppression relative to the signal gain is range from 5 to 15 dB, with lower DC-offset suppression for smaller signal gain. However, when the signal gain is small, the absolute DC gain is even smaller thus the output DC-offset is in fact better reduced. Besides, in the case of large input signal and thus smaller gain, the SNR is large so that the DC-offset problem is further relaxed. The circuits consume 2.02 mA DC current. 50 Although the DC and nearby low frequency components are also useful signals at the output of multiplier, most of the signal energy is preserved after the DC-offset rejection scheme since only a band of less than 20 kHz is suppressed. Besides, since the major energy of the suppressed signal is below 1 kHz, in the time domain its impact requires a time of microsecond scale to manifest itself. However, in this UWB receiver the data rate is set to 100 Mbps, which means the analog baseband is reset every 10 ns, so that the impact of reduction of useful signal can be neglected. 3.3 Integrator In this section, an integrator for coherent UWB receiver is proposed, together with the affiliated discharging and compensation circuitry. 3.3.1 Integrators in the Literature In the literature, various kinds of integrators are proposed. Most of these integrators are designed as building blocks for continuous time active filters [69] ~ [73]. As shown in Fig. 3.22 (a), the normalized transfer function for an ideal integrator can be given as H (s) = 1 s (3.19) which indicates that an ideal integrator has infinite DC gain and a dominant pole at DC, and its phase shift at unit gain frequency is exactly 90° . However, as 51 shown in Fig. 3.22 (b), the practical implemented integrators always have finite gain and non-zero bandwidth. A practical integrator may also have one or more non-dominant poles in the high frequency. The finite DC gain causes phase lead at the unity-gain frequency and the non-dominant poles result in excess phase shift. In filter design, the phase errors of integrators at unit gain frequency are required to be minimized because these phase errors can significantly distort a filter’s frequency response [71]. However, in UWB integrator design this requirement is relatively relaxed. (a) (b) Fig.3. 22: Frequency response of an integrator. (a) ideal case. (b) practical implementation. 52 Fig. 3.23: Five common integrator structures. As shown in Fig. 3.23, there are several common architectures to implement an integrator [69]. In the popular Gm − C integrator structure (Fig. 3.23 (a)), the outputs of a transconductor are directed connected with grounded capacitors [74] [76]. Since a transconductor does not need a output stage with low output resistance, it has the advantage of low complexity and superior high-frequency performance than its counterpart opamp. However, in this structure the parasitic capacitances at the transconductor outputs are directly added to the integrator capacitor, thus causing degradation in the accuracy of the integrator. 53 In Fig. 3.23 (b), the Gm − C − Opamp structure is shown [77] [78]. This structure uses a local feedback to create virtual ground at the transconductor outputs, thus alleviating the effect of parasitic capacitances. Besides, the Miller equivalent capacitors at the transconductor outputs are much larger than the parasitic capacitances, so that the sensitivity to parasitic capacitance is further reduced. This structure also has the advantage of large DC gain since there are two gain stages cascaded at DC. The Gm − C − OTA structure is shown in Fig. 3.23 (c) [79]. It is similar to the Gm − C − Opamp structure except that an Operational Transconductance Amplifier (OTA) is used instead of an opamp. When the load of the integrator is of high impedance or capacitive, the output stage of the opamp is not necessary thus an OTA is employed. The elimination of the output stage simplifies the circuits and achieves better high frequency performance than that of an opamp. However, since the outputs of this structure are not low impedance nodes, if the load capacitance is too large, the frequency performance can also be affected. As depicted in Fig. 3.23 (d), the MOSFET − C − Opamp uses MOS transistors working in triode region as linear resistors to provide voltage-to-current conversion [80] - [82]. This approach achieves much more linear V-I conversion than that in previous three structures. However, the MOS transistors used for V-I conversion exhibit a significant parasitic distributed capacitance so that it is not suitable to use as a resistor at high frequency. The MOSFET − C − OTA structure shown in Fig. 3.23 (e) uses an OTA to 54 replace the opamp in MOSFET − C − Opamp structure [83]. The underlying principle is exactly the same as the replacement of the opamp with an OTA in the Gm − C − OTA structure. (a) (b) Fig. 3.24: Two types of capacitor connection. In the integrator structures discussed above, differential signal paths are employed. Shown in Fig. 3.24 and taking the Gm − C integrator for example, there are two types of methods to connect capacitors to differential output nodes. The connection type (b) avoids back-plate parasitics and thus the two output branches are more symmetric [70]. In high frequency applications which are sensitive to parasitics, type (b) connection is often employed, however, at the cost of a total capacitor area four times as large as that in type (a). 3.3.2 Proposed Integrator Structure In the coherent UWB receiver design, the integrator is required to perform time domain integration on pulse signals from the multiplier output. Since the signal at the multiplier is still weak, sufficient gain should be provided by the integrator. Because the period of data transmission is only 10 ns and the pulse is 55 narrow, the integrator should operate in very high speed, i.e. the integration time should be less than 1 ns. The output value is sampled at the middle of each period, so that the integration output should hold for about half a period without significant discharging before the sampling. Ideally, the output of an integrator in response to a narrow pulse should be a step signal. For a nonideal integrator with finite DC gain, the response to a pulse will be a step signal first, then decreases exponentially to zero due to discharging. If the input pulse is approximately modeled by an ideal impulse (Dirac function) δ (t ) , and the nonideal integrator is modeled by a single pole system as H (s) = ADC , s 1+ (3.24) ωo then the integrator’s response to the impulse is h(t ) = ADC ⋅ ωo ⋅ e−ωot u (t ) . (3.25) where ADC and ω0 are the DC gain and the dominant pole of the integrator, respectively, and u (t ) represents the unit step signal. From (3.25), the amplitude of the response is proportional to the quantity ωu = ADC ⋅ ωo , which is the unit gain frequency of the integrator. The discharging time constant is determined by the dominant pole. As a result, to increase the amplitude and holding time of the integrator output, the integrator’s unit gain frequency should be maximized and the dominant pole should be minimized. Besides, the requirement of high speed translates to high slew rate and fast settling behavior, which means the integrator should be able to output large current and the non-dominant poles should be as 56 large as possible. Among integrator structures reviewed in the previous section, Gm − C − Opamp and MOSFET − C − Opamp structures employ operational amplifiers with output stage, which consumes additional power and is not necessary since integrators in the UWB receivers do not need to drive small resistive load. MOSFET − C − OTA integrators can not provide large DC gain and its high frequency performance is sensitive to the distributed parasitics in the MOS transistors in triode region. In the Gm − C integrator structure, the unit gain frequency is ωu = Gm / C and the -3 dB bandwidth is ω−3 dB = 1 , where Gm and RL are the RL C transconductance and load resistance of the transconductor respectively, and C is the load capacitor. According the design requirements, it is desired to increase ωu = Gm / C to obtain high output amplitude and to decrease ω−3dB = 1 to RL C increase the holding time constant, so Gm and RL should be as large as possible. However, they are contradicting objectives when choosing the bias current. Further more, the choice of load capacitor C brings another trade-off. As a result, for the Gm − C integrator structure it is difficult to achieve both large time constant and large unit gain frequency simultaneously. To achieve the required performance, the Gm − C − OTA structure is chosen, as shown in Fig. 3.25. Besides the advantage of less effect of paracitics, the Gm − C − OTA structure relaxes the requirement and trade-offs for building block 57 circuits design. Since the transconductor output is connected to virtual ground, its output swing can be small. The load capacitance increases due to the Miller effect, so that the output impedance of the transconductor need not be very large to achieve a low -3 dB bandwidth. Fig. 3.25: The chosen integrator structure: Gm − C − OTA structure. To analyze the gain and bandwidth issues mathematically, both the transconductor and the OTA are modeled as first order low-pass systems here. The transconductance and output impedance of the transconductor are represented as Gm _ Gm and Ro _ Gm , respectively. The transconductance and output impedance of the OTA are represented as Gm _ OTA and Ro _ OTA , respectively. Here Ro _ OTA > Ro _ Gm . The DC gain of the two blocks are given as and AGm = Gm _ Gm ⋅ Ro _ Gm (3.26) AOTA = Gm _ OTA ⋅ Ro _ OTA . (3.27) Using Miller theorem, the capacitors C can be approximately replaced by the equivalent capacitors C1 and C2 at outputs of the transconductor and the OTA, respectively. The two transistors are C1 ≈ AOTA ⋅ C and C2 ≈ C . Taking the 58 parasitic capacitances at the output of transconductor and OTA C p _ Gm and C p _ OTA into account, the total capacitance at these two nodes are CGm = C1 + C p _ Gm ≈ C1 and COTA = C2 + C p _ OTA ≈ C2 , respectively. The equivalent circuit is shown in Fig. 3.26. Fig. 3.26: Equivalent model of the Gm − C − OTA integrator structure. The transfer function of the integrator is given as H ( s) = = ≈ Vout Vin Gm _ Gm ⋅ Ro _ Gm ⋅ Ro _ OTA ⋅ (Gm _ OTA − sC ) ( s ⋅ Ro _ Gm ⋅ Ro _ OTA ⋅ C p _ OTA ⋅ C p _ Gm + s ⋅ Gm _ OTA ⋅ Ro _ Gm ⋅ Ro _ OTA ⋅ C + 1 2 Gm _ Gm ⋅ Ro _ Gm Ro _ OTA ⋅ (Gm _ OTA − sC ) s ⋅ C p _ OTA ⋅ C p _ Gm ( s ⋅ Gm _ OTA ⋅ Ro _ Gm ⋅ Ro _ OTA ⋅ C + 1) ⋅ ( Gm _ OTA ⋅ C (3.28) + 1) From the transfer function derived above, the overall DC gain of the integrator is AGm ⋅ AOTA = Gm _ Gm ⋅ Ro _ Gm ⋅ Gm _ OTA ⋅ Ro _ OTA , the dominant pole is located at p1 = p2 = 1 1 , and the second pole is located at ≈ Gm _ OTA Ro _ Gm Ro _ OTAC Ro _ Gm ⋅ C ⋅ AOTA Gm _ OTA ⋅ C C p _ OTA ⋅ C p _ Gm . If AOTA is sufficiently large, then p1 1 should 3 be satisfied [96]. This ratio determines the depth of the positive feedback and thus the amplitude of the hysteresis characteristic, which is 90 mV in this case (shown in Fig. 3.34). A large inverter is added after the comparator core to drive the load. This whole comparator consumes 0.6 mA DC current. The propagational delay is less than 400 ps for a 70 fF load, which is the typical value for parasitic capacitance of a pad. Fig. 3.33: Schematic of the comparator. Fig. 3.34: The hysteresis characteristic of the comparator. 67 3.5 A Brief Overview of Other Receiver Building Blocks Besides the building blocks described in previous sections, a Low Noise Amplifier (LNA), a Pulse Generator (PG), a Demodulation Drive Amplifier (DDA) and a Low-Pass Filter (LPF) are also employed in the UWB receivers in this project. These building blocks are designed by several other group members. They are briefly reviewed here, for better understanding of the next chapter on receiver system integration and for the completeness of receiver description in this thesis. 3.5.1 Low Noise Amplifier The schematic of LNA used in both the coherent and the non-coherent receivers is shown in Fig. 3.35. It is a two-stage cascaded LNA with inductor peaking shunt feedback for bandwidth expansion. Source follower M2 and R1 is used to provide DC bias for M1. LC loading L1 and C1 are tuned to boost the gain. The LNA has a measured power gain of 18 dB, NF of 4.6 dB, and -3 dB bandwidth around 7 GHz [98]. 68 Fig. 3.35: Schematic of the UWB LNA. 3.5.2 Pulse Generator The schematic of the differential pulse generator (PG) used in the coherent UWB receiver is shown in Fig. 3.36. The input to the PG is a clock signal, and each rising edge of the clock triggers a pulse at the output. The PG consists of three cascaded stages that realize the square (R1 and M1), exponential (M3 and M4) and second-order derivative functions (L1, C1, L2 and C2). The detailed working principle can be found in [97] [98]. Fig. 3.36: Schematic of the differential pulse generator without buffers. 69 The measured pulse width is 0.6 ns with swing around 35 mV. The RMS error relative to the ideal one is within 3%. The pulse generator consumes 2.7 mW power. Buffers are added after the pulse generator to obtain output swing larger than 200 mV [97] [98]. 3.5.3 Demodulation Drive Amplifier The schematic of the demodulation drive amplifier (DDA) used in the non-coherent UWB receiver is shown in Fig. 3.37. L1 and L2 function as inductive degeneration at the source of M1 and M2. The output LC tanks (C1, L3 and C2, L4) are used to boast the gain in a wide frequency range of 0.1 - 2 GHz, using inductors with Q less than 3. A power gain of 10 dB is obtained in the above mentioned bandwidth with a good IIP3 of -4dBm and low NF of 4.5 dB. C3 and L5, resonates around 1 GHz, which improves the output impedance of the current source and the balance of the differential current outputs [99]. Fig. 3.37: Schematic of the demodulation drive amplifier. 70 3.5.4 Low Pass Filter The schematic of the low pass filter used in the non-coherent UWB receiver is shown in Fig. 3.38. A differential gm-C active LPF is shown in Fig. 9. Transistors M1 – M20 work as a linear V-I converter [90], together with an on-chip capacitors, a simple gm-C LPF is realized. It achieves a -3 dB bandwidth of 50 MHz and gain of 5 dB [99]. Fig. 3.38: Schematic of the low pass filter. 71 Chapter 4 UWB Receiver Integration and Performance In this chapter the integrated coherent and non-coherent UWB receivers implemented in CSM’s 0.18-µm CMOS technology are described. The modulation schemes and receiver system issues are as described as in Chapter 2. The receivers are constructed using the circuits described in Chapter 3. 4.1 Coherent Receiver Implementation and Performance 4.1.1 Coherent Receiver Integration The block diagram of the implemented coherent receiver is as shown in Fig. 4.1. The Analog-to-Digital Converter (ADC) is replaced by a comparator to simplify the circuits and to test the receiver front-end, as mentioned in Chapter 3. Fig. 4.1: The implemented coherent UWB receiver. The single ended LNA output is applied to the multiplier positive input, and the negative input of the multiplier is connected to a DC reference voltage together with a large grounded capacitor (10pF) to obtain an AC ground thereby performing single-ended to differential conversion. Fig. 4.2: Timing of clocks for pulse generator and integrator. Clocks for pulse generator and integrator are provided outside the receiver chip, as shown in Fig. 4.2. For 100 Mbps transmission rate, the period of the clock is 10 ns. If synchronization is achieved, the rising edges of pulse generator triggering clock align with the multiplier output signals. The integrator clock is slightly ahead of the local pulse generator triggering clock to make sure that the 73 whole multiplied pulse is integrated. 4.1.2 Simulated Performance of the Coherent Receiver The transient simulation results of the whole coherent receiver with a comparator are shown in Fig. 4.3. Fig. 4.3: Transient simulation results of the coherent receiver. The received pulse sequence is assumed to be information bits “101010…” at the rate of 100 Mbps and that the receiver clock is synchronized with transmitter clock. The peak-to-peak amplitude of received pulses is approximately 1.5 mV. The LNA amplifies the pulse sequence to obtain 15 mV peak to peak amplitude. The local pulse generator generates a template pulse sequence with more than 300 74 mV amplitude. The multiplier multiplies the amplified pulses and the local template pulses to obtain the pulses with DC components whose polarities are determined by the information bits carried in the received pulse sequence. This multiplied pulse sequence is amplified by the VGA and integrated by the integrator to obtain a fixed level of voltage output (with possible positive or negative polarities). The discharging circuits reset the integrator output values correctly in each period. The comparator converts integrator outputs directly to the demodulated information bits, which have a delay of less than 3ns compared to the original transmitted bits. Table 1 summarizes the receiver performance. The receiver gain is calculated from the LNA input to the integrator output, and the sensitivity is calculated as the average power in a 10ns period when the amplitude of detectable impulses has its minimum value. The layout of the coherent receiver front-end is shown in Appendix A. Table 1: Summary of Simulated Coherent Receiver Performance Parameters Values Parameters Values RX Noise Figure 8.5 dB Pulse Width 600 ps VGA Gain Range 0 ~ 45 dB Bandwidth 3.1 - 6 GHz RX Gain 80 dB RX Rate 100 Mbps Sensitivity -80 dBm RX Power Consumption 99 mW 75 4.2 Non-Coherent Receiver Implementation and Performance 4.2.1 Non-Coherent Receiver Integration The block diagram of the implemented non-coherent receiver is as shown in Fig. 4.4. As in the coherent receiver case, the ADC is replaced with a comparator. Fig. 4.4: The implemented coherent UWB receiver. As in the non-coherent receiver, single-ended to differential conversion is performed using DC reference voltage and large grounded capacitor for negative multiplier input. 4.2.2 Measured Performance of the Non-Coherent Receiver To measure the fabricated non-coherent receiver, the chip was mounted to a Rogers PCB by Chip-On-Board (COB) bonding in order to reduce parasitics of bonding wires and package. Weak modulated impulse signals are applied at LNA input from a verified UWB transmitter chip. To obtain amplitude below 10 mV, an 20 dB attenuator is used following the transmitter output. Alternatively, the 76 modulated signal can be transmitted between transmitter and the receiver at a distance of 40 cm through a pair of ultra-wideband antennas so that the received pulses are also attenuated by the same extent. The control voltage of VGA is adjusted manually from 0.7 ~ 1.5 V. The UWB pulse repetition rate is 200 MHz. The measured demodulated data patterns by the non-coherent receiver are shown in Fig. 4.5, for data rates of 1 Mbps and 20 Mbps. The transmission rate is up to 50 Mbps. The binary data pattern are demodulated and recovered almost without symbol error. The peak-peak amplitude of demodulated signal is around 200 mV and 100 mV respectively. (a) Data rate=1 Mbps 77 (b) Data rate=20 Mbps Fig. 4.5: Measured real time waveforms of data patterns. (Above: transmitted data pattern, Middle: modulated pulse signal, Below: demodulated and recovered pattern) The measured receiver performance is summarized in Table 2. As in the coherent receiver case, the receiver gain is measured from the LNA input to the integrator output, and the sensitivity is measured as the average power in a 10 ns period when the amplitude of detectable impulses has its minimum value. The die micrograph of the non-coherent receiver front-end is shown in Appendix B. This testing environment is for research purpose only and is not practical enough for real-world application. To ensure that the chips can work in real application, the circuits should be further improved to achieve better performance in sensitivity, noise figure and linearity. The testing method should also be improved using longer transmitting distance and with presence of in-band strong interferences at inputs. 78 Table 2: Summary of Non-Coherent Receiver Performance Specification Performance RX Noise Figure 7.5 dB VGA Gain Range 0 ~ 45 dB RX Gain 80 dB Sensitivity -60 dBm RX Current Consumption 18 mA RX Die Size 2.18 × 1.75 mm 2 4.3 Layout Considerations In order to minimize the non-ideal effects of process such as mismatch, substrate noise coupling and high frequency signal coupling, great efforts have been made in the layout design. Here is a list of major considerations involved in the layout design for both coherent and non-coherent UWB receivers. z Common-centroid technique and geometrically symmetric layout is used for all the differential pairs and four-transistor cross-coupled pairs. z Dummy poly is used at both ends of transistor arrays. z Guard rings with taps are used for all the front-end circuits to block substrate coupled noise and to avoid latch-up. z Lengths of high-frequency wires are minimized by careful floor planning and optimal choice of pad order. 79 z Ground-Signal-Ground (GSG) patterns are used for high frequency input signal. z Electrostatic Discharge (ESD) protection circuits are used with all the pads. z Multi-layer metals wires with vias are placed to enclose each high frequency block to avoid interference between blocks. z Metal wires with large width are used for paths with DC current larger than 1mA to ensure reliability. z Large numbers of vias and contacts are used to ensure the electrical connections. 80 Chapter 5 Conclusions and Future Directions 5.1 Conclusions Several building blocks for UWB impulse radio receiver including multiplier, VGA, integrator and comparator for UWB receiver are designed and implemented in a 0.18-µm CMOS technology. In the multiplier cross-coupled transistors and source followers are used to sense and multiply input signals and inductor peaking is employed to enhance bandwidth. With a DC-offset suppression feedback loop, the twp-stage VGA has more than 15 dB offset suppression and 45 dB dynamic range. The integrator employs Gm − C − OTA structure to obtain unit gain frequency of around 1 GHz and low -3 dB bandwidth of less than 1 MHz. Feedforward technique is used to achieve good settling behavior. A comparator with 90 mV hysteresis and 400 ps propagation delay is designed. Two UWB receiver architectures are proposed: the coherent receiver and non-coherent receiver. They are implemented in a 0.18-µm CMOS technology using the proposed circuits. The coherent receiver achieves 100MHz data 81 transmission rate and -80 dBm sensitivity while the non-coherent receiver achieves a transmission rate up to 50 MHz and -65 dBm sensitivity. The measurement results confirm the functions of receiver systems, however, bandwidths and driving capabilities of some blocks like multiplier and integrator are not as good as that in the simulation, which will be improved in the future work. 5.2 Future Directions 1) Ideally a DC-offset suppression scheme should be able to identify and separate the desired DC signal and the DC-offset while avoiding the unwanted effects of switching circuits. One possible solution is the combination of back-end DSP calibration and the proposed continuous-time feedback loop. 2) Speed of the integrator can be further improved by employing transconductor cells with better high frequency performance. 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[99] Yuanjin Zheng, Yan Tong, Yongping Xu, Wooi Gan Yeoh, "A CMOS UWB Transceiver for WPAN,” IEEE Radio Frequency Integrated Circuits Symposium, Long Beach, CA. United States, June 2005. 93 Appendix A Layout of the Coherent Receiver Chip This layout is part of a large chip layout containing both transmitter and receiver. 94 Appendix B Die Micrograph Receiver chip of 95 the Non-Coherent Appendix C Publications P1: Yuanjin Zheng, Yan Tong, Yongping Xu, Wooi Gan Yeoh, "A CMOS UWB Transceiver for WPAN,” IEEE Radio Frequency Integrated Circuits Symposium, Long Beach, CA. United States, June 2005. P2: Yan Tong, Yuanjin Zheng, Yongping Xu, "A Coherent UWB Receiver IC System for WPAN Application,” IEEE International Ultra-Wideband, Zurich, Switzerland, September 2005. 96 Conference on [...]... the adopted BPSK and Pulse OOK modulation schemes, the correlator based coherent UWB receiver architecture and the self-synchronized non-coherent UWB receiver architecture are proposed Chapter 3 concentrates on design of UWB receiver building blocks for ultra- wideband application and their performance Blocks including multiplier, integrator, VGA and comparator are discussed Blocks designed by group... _ VGA Bandwidth of the VGA RL Load resistor ω− sdB _ FB Bandwidth of the feedback loop g ma , g mb Transconductance of MOSFETs in VGA Q Quality factor of low pass filter ωT Unit gain frequency of the VGA core ADC DC gain of amplifier ω0 -3dB bandwidth of amplifier ωu Unit gain frequency of the integrator ω−3dB -3dB band width of amplifier AGm DC gain of transconductor Gm _ Gm Transconductance of transconductor... integrator, VGA and comparator are investigated and two UWB receiver systems are built in 0.18 µm CMOS technology based on the proposed building blocks and some other available circuit blocks The two receivers achieve transmission rates of 100 Mbps and 50 Mbps respectively, and sensitivity of -85 dBm and -65 dBm respectively The goal is to solve several critical problems in DS-UWB receiver design such... Background and Motivation 1.1.1 Overview of Ultra- Wideband System Ultra wideband (UWB) systems are a new wireless technology capable of transmitting data over a wide frequency spectrum with very low power and high data rates Among the possible applications, UWB technology may be used for high speed data communication systems, vehicular and ground penetrating radars, and imaging systems One of its most... narrowband systems Fig 1.1: FCC Spectral Mask for UWB Communication Systems [4] 2 There are two main categories of UWB signaling schemes: Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) [4] based scheme and Direct-Sequence UWB (DS-UWB) [5] [6] [7] based scheme The former divides the whole UWB spectrum into sub-bands with bandwidth of several hundred of Megahertz, and in each band a conventional... correlator design and DC-offset suppression, and to use simulation and experimental results to verify the feasibility of integrated UWB receiver solution in low cost CMOS technology 1.2 Organization of the Thesis In chapter 2, conventional receiver architectures are briefly reviewed The modulation schemes for UWB impulse radio such as Pulse Position Modulation (PPM), pulse On-Off Keying (OOK) Modulation and. .. oscillators and channel select bandpass filters, are not present in an impulse radio type UWB (DS-UWB) receiver, and almost all of conventional receiver architectures can not be directly applied to DS-UWB receivers As a result, innovations on novel system architecture as well as new circuits techniques are needed In this thesis various key building blocks of impulse radio type UWB wireless 4 receivers. .. of the coherent receiver 74 Fig 4.4: The implemented coherent UWB receiver 76 Fig 4.5: Measured real time waveforms of data patterns (Above: transmitted data pattern, Middle: modulated pulse signal, Below: demodulated and recovered pattern) 78 xiii List of Symbols and Abbreviations Symbols v1 (t ) Input of multiplier v2 (t ) Input of multiplier Id Bias current of MOSFET X, Y Bias of. .. Gate-source voltage of MOSFET VT Threshold voltage of MOSFET Vds Drain-source voltage of MOSFET K Transconductance parameter of MOSFET µ0 Mobility of MOSFET Cox Unit gate capacitance of MOSFET W Width of MOSFET L Length of MOSFET Io Output current xiv Vout Output voltage Z out Output impedance VCtrl Control voltage Av Voltage gain Gs Transconductance of circuits Rd Load impedance gm Transconductance of MOSFET... multiplier for UWB receiver 33 Fig 3.8: Bandwidth and gain of the multiplier from RF input to output 36 Fig 3.9: DC transfer characteristic of the multiplier from RF input to output 36 Fig 3.10: Bandwidth and gain of the multiplier from LO input to output 37 Fig 3.11: DC transfer characteristic of the multiplier from LO input to output 37 Fig 3.12: Transient simulation of ... TONG YAN Degree: Master of Engineering Department: Electrical and Computer Engineering, NUS Thesis Title: Design of CMOS Receivers and Building Blocks for Ultra -Wideband Radio Abstract In this... concentrates on design of UWB receiver building blocks for ultra -wideband application and their performance Blocks including multiplier, integrator, VGA and comparator are discussed Blocks designed... receiver systems and CMOS integrated circuits design for Ultra -Wideband (UWB) communication are proposed Several building blocks for the receivers are designed in a 0.18-µm CMOS technology Cross-coupled