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4 Data Conversion in Software Defined Radios Brad Brannon, Chris Cloninger, Dimitrios Efstathiou, Paul Hendriks, Zoran Zvonar Analog Devices Data converters are one of the key enabling technologies for the software defined radio (SDR). Regardless of the interpretation of the definitions – software radio, software defined radio, software based radios – the challenge of moving the analog-digital boundary closer to the antenna is the critical step in establishing the foundation for increasing the content and capability of digital signal processing (DSP) in the radio. SDR technologies have provided the incentives for the breakthrough in converter technologies pushing the state-of-the-art [1]. In this chapter we review the foundations and technologies of data conversion from the perspective of their usage in SDRs, exploring capabilities, constraints, and future potential. 4.1 The Importance of Data Converters in Software Defined Radios The use of converters in SDR depends upon the overall radio architecture. A summary of sampling techniques for the various receiver architectures described in Chapters 2 and 3 is given in Table 4.1. Table 4.1 Summary of sampling strategies for SDR receivers Radio RX architecture Analog output Sampling strategy Direct conversion I/Q baseband Quadrature baseband Superheterodyne I/Q baseband Quadrature baseband IF signal IF sampling Bandpass sigma-delta Low IF IF frequency – quarter of sampling frequency Direct sampling Software Defined Radio Edited by Walter Tuttlebee Copyright q 2002 John Wiley & Sons, Ltd ISBNs: 0-470-84318-7 (Hardback); 0-470-84600-3 (Electronic) Direct sampling (Nyquist sampling) satisfies the conditions of the sampling theorem for bandlimited analog signals, requiring that the sampling rate is at least two times the highest frequency component of the analog signal. In practical realization, direct sampling imple- mentation is closely coupled with anti-alias filtering realizations. Oversampling of the signal usually eases requirements on the anti-alias filter. Special cases of direct sampling are when the carrier signal frequency of the analog signal is 1/4 of the sampling rate, allowing for a simplified digital down-converter implementation [2]. In quadrature sampling the analog input signals are split into in-phase and quadrature components, each occupying only half of the bandwidth of the original signals. Quadrature sampling thus reduces the sampling rate by a factor of two, at the expense of needing two phase-locked analog-to-digital converters (ADC) instead of one [3]. Intermediate frequency (IF) sampling (or subsampling) of the bandpass signal requires the sampling frequency to be at least two times the bandwidth of the signal. With this approach, the bandpass signal content is repeated at integer multiples of the sampling frequency and one of the spectral replicas can be selected. This operation also provides the down-conversion of the signal of interest. 4.1.1 ADCs for SDR Base Stations The realities of the wireless industry have moved the idea of SDR into new applications. Having in mind economics, with direct implication on size, power consumption and complex- ity, SDR concepts are finding initial acceptance and usage primarily in base station applica- tions. Several variations on the SDR theme (or combinations of the solutions listed below) can be identified in current base station designs: † Single carrier base stations with IF sampling and digital downconversion. † Multicarrier base station approach for a single standard. The usual way is to provide multicarrier operation where the whole band of interest is sampled. This approach elim- inates multiple radios (for different carriers) in favor of a single, high-performance, wide- band, radio per antenna, where each carrier is processed in the digital domain. † Multimode solution supports several radio standards, and SDR is the cost- effective way to establish multimode solution. This approach minimizes multiple radio functions (for different standards) in favor of a multimode high performance radio per antenna. The signal for each standard is processed in the digital domain. This type of solution provides the often necessary upgrade capability from legacy systems to new standards. † Reconfigurable base stations provide software and possibly hardware (programmable filters, field programmable gate arrays (FPGAs), systolic arrays) reconfiguration based on the air interface. In all cases, ADC is critical for the system operation. Base station architectures may take into consideration either quadrature baseband sampling or IF sampling. For a given frequency band (dependant on the air interface) the analog front end can be optimized; it is, however, kept fixed, which is more cost effective today than having a frequency agile and bandwidth programmable front end SDR implementation. The system clock is fixed, providing uniform sampling of the analog signal. The analog front end has a direct impact on the ADC dynamic range [4]. Wideband IF Software Defined Radio: Enabling Technologies100 sampling front end linearity is critical for intermodulation generation, and selectivity is significant for blocking attenuation. Requirements of the given wireless air interface signifi- cantly impact ADC specification in terms of dynamic range and spurious free dynamic range (SFDR). Factors influencing the dynamic range of the converter in wireless systems include statistical properties of the input signal, peak to average ratio, level of the interference, frequency of the interfering signal compared to aperture jitter, fading margin, etc. [5]. Selec- tion of the bandwidth to be digitized depends on the maximum sampling rate and dynamic range of an ADC. Approximately one bit of the resolution is lost for every doubling of the sampling rate [1]. Base station designs rely on best available converters in the class with highest resolution and widest operating bandwidth. Available state-of-the-art ADCs for wireless applications are 14-bit resolution devices operating in excess of 100 MHz, but there is an increased demand from base station manufacturers for 16-bit ADCs operating in excess of 120 MHz. These ADCs maintain 100 dB SFDR over the Nyquist band and a typical signal-to-noise ratio is 75 dB. Fourteen-bit ADCs allow weak cellular handset signals to be demodulated in the presence of strong ones. These devices have low sampling jitter in order to allow digitization of IF up to 250 MHz analog input. Dither is used to improve ADCs’ SFDR. In principle, data converters with higher sampling frequencies can capture wider parts of radio frequency (RF) spectrum. Converters with higher bit resolutions can process higher dynamic ranges. Unlike single carrier IF sampling solutions, it is much more difficult to place the spurious content out of the band of interest in a multicarrier solution, because of the large number of carriers. The aliased spurs of one carrier are likely to fold back on the same carrier or another carrier. This occurrence places a greater requirement on the SFDR of the ADC than a single carrier does. Thus, the SFDR is usually the limiting factor for a wideband system. 4.1.2 ADCs for SDR Handsets Following the technological advances in key areas, including RF, converter technology, DSP technology, and programmable hardware approaches, SDR ideas are making their way in terminal designs. Having in mind the strict power limitation of handsets, different approaches have been applied to the design of ADCs for such usage: † bandpass sampling for single standard terminals † reconfigurable converters reusing hardware blocks for multimode terminals. Dual band and tri-band phones for a single wireless standard already exist. In the past one could not find a strong argument to extend the wireless terminal into a fully SDR type device since the commercial mobile systems worldwide fall into a relatively small number of frequency bands and are primarily single mode. However, the introduction of the third generation (3G) wireless standards are increasing the importance of multimode terminals. The focus of design will be on multimode radios with some sort of reconfigurable converter that can provide performance/complexity trade-off. 4.1.3 DACs for SDR Applications While the SDR concept heavily focuses on ADC performance, transmit path requirements are Data Conversion in Software Defined Radios 101 usually given less attention, although the problem is of comparable complexity [6]. High performance digital-to-analog converters (DACs) are specifically used in the transmit (Tx) signal path to reconstruct one or more carriers that have been digitally modulated. More of the signal processing in these new generations of communication equipment is being performed in the digital domain for multiple reasons (i.e. higher spectral efficiency thus higher capacity, improved quality, added services, software programmable, lower power, etc.). Furthermore, many of these DSP functions are being integrated with the DAC itself to enhance its perfor- mance and to enable new transmitter architectures. These DSP functions may range from digital interpolation filters, which reduce the complexity and cost of the required analog reconstruction filter, to complete application specific digital modulators for quadrature or spread spectrum modulation schemes. Synthesizing communication signals in the digital domain typically allows the character- istics of a signal to be precisely controlled. However, in the reconstruction process of a digitally synthesized signal, it is the DAC and its nonideal characteristics which often yield unpredictable results. In some cases, it is the performance of the DAC which actually determines whether a particular modulation scheme or system architecture can meet the specification. Unlike high speed video DACs, the performance of DACs in wireless systems is often analyzed in the frequency domain, with secondary consideration given to the time domain and DC specifications. Selecting the optimum DAC for a given wireless system requires an understanding of how to interpret various specifications and an appreciation of their effects on system performance. Achieving the optimum performance while realizing other system objectives demands careful attention to various analog interface issues. Much design effort has gone into improving the frequency domain and static performance of these devices while meeting other system objectives such as single supply operation, lower power consumption, lower costs, and ease of digital integration. To that extent, several semiconductor vendors realizing the significance of the above stated objectives as well as industry trends have elected to focus much of their effort on designing high -performance DACs on a digital CMOS process. State-of the-art DACs are 14-bit devices with SNR higher than 80 dBc and sampling rate of 400 Msamples/s. Third-order intermodulation distortion is smaller than 280 dBc up to 30 MHz output. Before addressing data converter performance issues in SDR applications, it is important to discuss the most commonly used data converter architectures in order to understand their potential applicability to SDRs. 4.2 Converter Architectures Over the last 20 years there has been a tremendous amount of research and development investment to improve ADCs. Although there are many converters on the market, most are based on one of a few core architectures. As new architectures evolve, there is a trend toward higher integration, lower power, and increased performance. It is essential to understand each of these architectures so that the best converter can be selected for a given communications system. 4.2.1 Flash Converters One of the first data converter architectures was the flash converter. A flash or parallel Software Defined Radio: Enabling Technologies102 converter, as they are often called, consists of 2 N 2 1 comparators, where N is the number of digital output codes. One input of all of the comparators is tied to the analog input via buffers, track-and-hold circuits, or other conditioning elements. The other inputs are tied to successive steps on a resistor ladder. The top and bottom of the ladder are tied to reference voltages that represent the input range of the flash. Therefore, as the input voltage increases, each of the comparator outputs in the chain sequentially goes true, producing what is often called a ‘thermometer code’. Since the normal desired output is binary, the thermometer code must be converted to binary through lookup tables and/or reduction logic. Flash converters have many benefits. Because of the straightforward design, this architec- ture offers extremely fast conversion times. For low resolution applications, premium perfor- mance can be obtained at a minimum cost. This has made flash converters attractive for applications where dynamic range requirements are minimal. The biggest drawback to this architecture is that as the number of bits increases, the size of the chip, costs, and complexity increase at an exponential rate of 2 N . Although not impossible to design and build, in practice there are very few flash ADCs larger than 10 bits because of the relatively large die sizes. Beyond this point they are too big and complex to manufacture efficiently, thus adversely impacting on cost. To overcome the complexity problem, different Data Conversion in Software Defined Radios 103 Figure 4.1 Typical flash ADC architecture architectures have been developed which use fewer comparators such as in folded flash or pipelined architectures. In addition, as the number of comparators increases, the reference voltages get smaller and smaller. As the reference voltage is reduced, the offset voltage of the comparator is approached. Once this happens, the linearity and overall performance of the converter is compromised. Finally, as more comparators are connected to the analog input, the input capacitance increases. With the increased capacitance, the effective signal bandwidth is reduced, defeat- ing the high speed benefit of the parallel converter. In addition to these impediments, there are several anomalies associated with the flash architecture. The first is basic linearity. The overall linearity of a flash converter is determined by the linearity of the resistive ladder. If not properly constructed, the differential nonlinearity (DNL) and integral nonlinearity (INL) requirements of the converter will not be met. Addi- tionally, because comparators have input leakage currents, these additional currents in the ladder can affect both the DNL and INL of even a perfectly constructed ladder. As discussed later, both of these converter parameters can adversely affect the performance of a receiver (Figure 4.1). 4.2.2 Multistage Converters Another popular architecture used in high speed, high resolution ADC is the multistage architecture. One of the key advantages of this architecture is its scalability. The end resolu- tion can be manipulated easily by increasing and decreasing the bit precision of each stage. Obviously there are trade-offs in doing this, but conceptually it is possible to extend this architecture up to 16 bits and beyond. Because of the ability to construct high resolution converters, this is a popular architecture used in many SDR applications. Shown in Figure 4.2 is an ADC suitable for SDR applications which uses three stages and has 14 total bits of resolution. Multistage converters operate by the redigitization of residual signals. The original analog input is presented to the first track-and-hold (TH1). On the first positive clock edge this signal is held. This output is then presented to both the second track-and-hold (TH2) and the first conversion stage. For this example, the first conversion stage consists of a 5-bit ADC (ADC1) Software Defined Radio: Enabling Technologies104 Figure 4.2 Multistage subranging ADC and a 5-bit DAC (DAC1) which requires 16 bits of precision. TH2 remains in track mode until the falling edge of the clock. This held signal is then subtracted from the DAC1 output. The residual signal is then amplified (A2) and fed into TH3. The output of TH3 is digitized by another conversion stage consisting of a 5-bit ADC (ADC2) and a 5-bit DAC (DAC2). DAC2 requires 10 bits of precision so that it will not dominate the precision of the remaining converter stages. The output of the second conversion stage is then subtracted from the output of TH4 and feeds the residual into TH5. The output of TH5 feeds the final 6-bit ADC (ADC3). The output of the three conversion stages is combined and digitally corrected to generate the final 14-bit output word. It should be noted that the total number of bits involved is actually 16. The extra 2 bits (1 bit per error stage) are used to digitally correct for gain and offset errors within the chip. When comparing a multistage ADC with a single stage flash or pipeline ADC, many advantages exist. The main advantage over CMOS pipeline architectures is that very high precision can be achieved without the associated pipeline delays. In the multistage architec- ture above, the output data represents the current analog input after four or fewer clock cycles. A similar precision pipeline ADC would take up to 10 clock cycles. These delays constitute latency, which can be important in many communications applications, especially those that use adaptive techniques in the digital signal processing. In comparison to single stage flash converters, much less die area is used because far fewer comparators are required. This results in a smaller die with improved yield, lower power, and lower overall cost. Although a multistage ADC has many advantages, it does have some very challenging design requirements. As mentioned above, this architecture places strict requirements on the first conversion stage DAC (DAC1). Because this DAC (DAC1) represents the reference for the entire ADC, it must have a resolution greater than the overall number of bits for the entire ADC. With today’s technology, it is possible to achieve up to 16 bits of resolution for this type of DAC. 4.2.3 Sigma-Delta Converters The sigma-delta (also known as delta-sigma) ADC is a highly innovative and relatively new idea in ADC technology. In wireless applications the SD ADC can offer integration with other RF/IF functions to build highly optimized integrated circuit (IC) devices. As shown in Figure 4.3, the SD ADC consists of an analog filter, a quantizer (comparator), a decimation digital filter circuit, and a DAC. An n-bit comparator tells the output voltage in Data Conversion in Software Defined Radios 105 Figure 4.3 Sigma-delta ADC which direction to go, based upon what the input signal is doing. It looks at the input and compares it with its last sample to see if this new sample is bigger or smaller than the previous one. If it is bigger, then it tells the output to keep increasing; if it is smaller, it tells the output to stop increasing and start decreasing. SD modulators work by sampling faster than the Nyquist criterion and making the power spectral density of the noise nearly zero in a narrow band of signal frequencies (quantization noise shaping). Oversampling pushes out the noise, but it does so uniformly – that is, the spectrum is still flat [7]; noise shaping changes that. Noise shaping contours the quantization noise. Conservation still holds, the total noise is the same, but the amount of noise present in the signal band of interest is decreased while simultaneously increasing the out-of-band noise. A series of decimation filters is used to remove any undesirable components (undesirable interferers and/or noise not sufficiently filtered in the analog domain) while simultaneously reducing the data rate in accordance with the target signal’s bandwidth. Depending on the modulation scheme, the complex data rate (hence decimation factor) is set to be at least a factor of two greater than the channel bandwidth, to allow for further postprocessing. There is no one-to-one correspondence between input voltages and output codes, so in this respect SD ADCs are different from Nyquist rate converters. Sigma-delta converters are characterized by their SNR; INL and DNL are not meaningful. SD modulators, regarding their front end analog signal frequency, are categorized either as lowpass or bandpass modulators. A lowpass SD modulator encodes incoming analog signals into a digital sequence of ^1, which is then digitally lowpass filtered. A bandpass modulator converts the analog input signal into a bit-stream. The output is almost equal to the input in the band of interest. A digital filter removes the out-of-band noise and converts the signal to baseband. The simplest form of an SD ADC uses first-order loop filtering and a single-bit comparator. In a second-order SD modulator, doubling the oversampling reduces the noise power by a factor of 32 and increases resolution at a rate of 2.5 bits per octave. To further increase the bandpass/lowpass signal resolution, higher order modulators can be used in an attempt to further improve the noise shaping. An Lth order loop filter further improves the signal to quantization noise in the bandpass/lowpass by improving the high - pass filtering of quantization noise (noise shaping). Stability is not a straightforward issue for higher order loop filters (for L . 2) and stable operation is usually possible only for limited input power. SNR increases at L 1 0.5 bits/octave for an Lth–order noise transfer function (NTF). Stability is a worrisome problem for L . 2, at least in single-bit modulators. The key factors in the development have been low cost and good linearity. One of the advantages of sigma-delta ADCs is that they do not require high precision and accurately trimmed analog components. In fact, the circuitry of a sigma-delta ADC only requires the analog components of a comparator and integrators. As a result, sigma-delta ADCs can be implemented with low cost CMOS circuitry using switched capacitor circuits. Due to their noise shaping behavior, sigma-delta modulators offer an attractive approach to realizing high performance analog-to-digital conversion without relying on the use of high precision and accurately trimmed analog components. In addition, oversampling generally has two advantages. First, the specification of the analog anti-alias filter is reduced from the Nyquist specification (i.e. the sharp cut-off analog filters required with Nyquist DSP systems can be replaced with slow roll-off RC circuits). Second, the n-bit resolution obtained from ADC can be increased to n 1 1 bits by oversampling the signal by a nominal factor of 4 and Software Defined Radio: Enabling Technologies106 subsequently digitally lowpass filtering to the Nyquist rate [8]. The lowpass filtering can require a number of stages of comb filters and multibit finite impulse response (FIR) filters, and is actually an expensive requirement (in digital circuitry terms). The trade-off when using sigma-delta ADC devices is an increase in the digital processing requirements against a reduction in the provision of accurately trimmed analog components and complexity. Sigma-delta ADCs are well suited for use in SDR, either for direct sampling or for bandpass sampling. By employing a bandpass loop filter and feedback around a coarse quantizer, bandpass modulators shape quantization noise away from narrowband signals centered at intermediate frequencies. This approach, first successfully integrated in [9], eliminates the need for dual in-phase/quadrature-phase analog mixers and the separate low pass ADC converters generally used for each quadrature channel. Instead, demodulation is now moved into the digital domain, thereby eliminating the problem of channel mismatch [10]. Furthermore, since the conversion is performed directly on the IF signal before mixing to baseband, the modulator does not suffer the effects of DC offset and low frequency noise problems. 4.2.4 Digital-to-Analog Converters Most high speed CMOS DACs (including bipolar and BiCMOS) employ an architecture based on current segmentation and edge-triggered input data latches to achieve the desirable code independent settling and glitch impulse characteristics that are necessary to maintain low distortion. Figure 4.4 shows a typical segmentation architecture common among many CMOS DACs. Typically, the upper 4 or 5 binary-weighted bits (MSBs) are implemented as thermometer decoded, identical current sources and switches. To optimize DC linearity performance, each of these identical current sources may consist of an array of unit current sources. The middle binary-weighted bits (LSBs) are implemented using a similar current Data Conversion in Software Defined Radios 107 Figure 4.4 Example of a segmented current source architecture used for a 14-bit CMOS DAC segmentation based on these unit current sources. The remaining LSBs consist of binary weighted current sources. Each of the weighted current sources can be switched either directly or indirectly into one of two output nodes using high speed, differential current switches as shown in Figure 4.5. The current sources and differential switches are fabricated with PMOS devices, allowing for both single supply operation and a ground-referenced load. These current sources are regu- lated by an internal control amplifier and may be isolated from the differential current switches via a cascode device to obtain higher output impedance. An external resistor, in combination with both the control amplifier and voltage reference, sets a reference current which is mirrored over to the segmented current sources with the proper scaling factor. The sum of all the currents corresponds to the DAC full scale current, I OUTFS . The I OUTFS of many CMOS DACs may be varied over a 20 dB range (i.e. 2–20 mA) for low power operation or analog gain control. The amount of current appearing at each of the two single ended, complementary current outputs, IOUTA and IOUB, is some fraction of the full scale current, I OUTFS , determined by the digital input code held within the DAC’s internal data register. A digital input code of all ‘0’s produces 0 mA of current at IOUTA, while a code of all ‘1’s produces the full scale current of I OUTFS (minus an LSB). IOUTB, being the complement of IOUTA, has the inverse relationship such that the sum of these two currents will always provide a constant current output whose value is equal to IOUTFS (minus an LSB). Note, the difference between IOUTA and IOUTB also provides a desirable code dependent fraction of I OUTFS providing twice the signal current, and offering several advantages to be discussed shortly. The two current outputs can easily be converted to two single ended or one differential voltage output by using resistive loads, a transformer, or an op amp. Beyond this common architectural approach lie various differences in the actual imple- mentation, affecting a high speed DAC performance and system requirements. For exam- ple, to improve upon their DC linearity performance, many 12- and 14-bit CMOS DACs use some form of factory calibration technique. A typical calibration procedure attempts to trim the current sources of the MSB segmentation to equal each other, and the sum of Software Defined Radio: Enabling Technologies108 Figure 4.5 Differential switches steer current into one of two output nodes allowing for differential or single-ended operation [...]... converters and their applications in radio receivers, IEEE Communications Magazine, Vol 33, No 5, 1995, pp 39–45 [4] Hentschel, T and Fettweis, G., ‘Software Radio Receivers’, in CDMA Techniques for Third Generation Mobile Systems, Kluwer Academic Publishers, 1998, pp 257–283 [5] Efstathiou, D and Zvonar, Z., ‘Enabling technologies and components for multi-standard software radio base stations’, Wireless... Note AN-410, Analog Devices [14] Wilborg, E., Semenov, V and Likharev, K., ‘RSFQ front-end for a software radio receiver’, IEEE Transactions on Applied Superconductivity, Vol 9, No 2, June, 1999, pp 3615–3618 [15] Brock, D., Mukhanov, O and Rosa, J.,‘Superconducting digital RF development for software radio , IEEE Communications Magazine, Vol 39, No 2, February, 2001, pp 174–179 [16] Yamaji, T., Yasuda,... For an Lth order modulator with sinusoidal noise shaping the signal to quantization noise is 1 See Chapter 2 for a more detailed discussion of noise performance design of SDR front ends Software Defined Radio: Enabling Technologies 110 given by [4] SNRQ ¼ 10:8 1 6:02N 1 ð2L 1 1Þ10logOSR 1 20log s 2L 1 1 1 10log ; OSR $ 4 Vpp p2L As in flash converters, the SNR due to quantization increases by 6.02 dB with... cause apparent gain errors to occur, possibly causing improper power estimation of the desired signal (Figure 4.6) Figure 4.6 ADC DNL error and associated gain errors Data Conversion in Software Defined Radios 111 4.3.1.3 Thermal Noise Another source of noise considered is thermal noise Thermal noise is related to the design and process on which the converter is manufactured Thermal noise can be computed... Specifically it is the base to emitter resistance (rb) of these transistors which dominates the overall thermal noise performance 4.3.1.4 Jitter The final contributor to dynamic specification that is vital to radio performance is ADC aperture jitter Aperture jitter is the sample to sample variations in the clock source Clock path jitter includes both internal and external jitter sources anywhere between the... tjitter By analyzing the units, it can be seen that this yields a unit of volts Usually, aperture uncertainty is expressed in seconds rms, and, therefore, the error voltage would be in volts Software Defined Radio: Enabling Technologies 112 Figure 4.7 Aperture jitter errors rms Additional analysis of this equation shows that as analog input frequency increases, the rms error voltage also increases in direct... considering overall converter performance, a more generalized equation may be used This equation builds on the previous equation and includes the effects of thermal noise Data Conversion in Software Defined Radios " SNR ¼ 1:76 2 20log  113 !2 #1=2 pffiffi 2  1 1 e 2 2 2vnoiserms 2pFanalog tjrms 1 1 2N 2N where Fanalog is the analog IF frequency, tjrms is the aperture uncertainty, e is the average DNL of the... the ADC, the gain of the ADC can be assumed to be 1 if the digital output is normalized to the input If another range is used, the gain should be consistent with the numeric range used Software Defined Radio: Enabling Technologies 114 4.3.2.2 Effective Number of Bits (ENOB) It is often convenient to express the relative performance of a data converter not by SNR, but by the effective number of bits that... function can represent INL In addition to various numerical techniques, great insight into converter spurious performance can be obtained by observation of the transfer Data Conversion in Software Defined Radios 115 function For example, if the transfer has a simple bow, a second-order error, a second harmonic is indicated If the transfer function has a step at midscale, or one-quarter and three-quarter... impulse Since multiplication in time is convolution in the frequency domain, the ideal sampling process yields the familiar repetition around multiples of the Figure 4.8 Aperture error Software Defined Radio: Enabling Technologies 116 sample clock However, the triangular sampling pulse leads to additional artifacts that not only repeat around multiples of the sample clock but also cause spurious products . software defined radio (SDR). Regardless of the interpretation of the definitions – software radio, software defined radio, software based radios – the challenge. Importance of Data Converters in Software Defined Radios The use of converters in SDR depends upon the overall radio architecture. A summary of sampling techniques