EE141 1 © Digital Integrated Circuits 2nd Timing Issues Digital Integrated Digital Integrated Circuits Circuits A Design Perspective A Design Perspective Timing Issues Timing Issues Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić January 2003 EE141 2 © Digital Integrated Circuits 2nd Timing Issues Synchronous Timing Synchronous Timing Combinational Logic R 1 R 2 C in C out Out In CLK EE141 3 © Digital Integrated Circuits 2nd Timing Issues Timing Timing Definitions Definitions EE141 4 © Digital Integrated Circuits 2nd Timing Issues Latch Parameters Latch Parameters D Clk Q D Q Clk t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T EE141 5 © Digital Integrated Circuits 2nd Timing Issues Register Parameters Register Parameters D Clk Q D Q Clk t c-q t hold T t su Delays can be different for rising and falling data transitions EE141 6 © Digital Integrated Circuits 2nd Timing Issues Clock Uncertainties Clock Uncertainties 2 4 3 Power Supply Interconnect 5 Temperature 6 Capacitive Load 7 Coupling to Adjacent Lines 1 Clock Generation Devices Sources of clock uncertainty EE141 7 © Digital Integrated Circuits 2nd Timing Issues Clock Nonidealities Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width Important for level sensitive clocking EE141 8 © Digital Integrated Circuits 2nd Timing Issues Clock Skew and Jitter Clock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race margin Clk Clk t SK t JS EE141 9 © Digital Integrated Circuits 2nd Timing Issues Clock Skew Clock Skew # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal – δ /2 Latest occurrence of Clk edge Nominal + δ /2 δ EE141 10 © Digital Integrated Circuits 2nd Timing Issues Positive and Negative Skew Positive and Negative Skew R1 In (a) Positive skew Combinational Logic D Q t CLK1 CLK delay t CLK2 R2 D Q Combinational Logic t CLK3 R3 • • • D Q delay R1 In (b) Negative skew Combinational Logic D Q t CLK1 delay t CLK2 R2 D Q Combinational Logic t CLK3 R3 • • • D Q [...]... 27 Timing Issues Clock Distribution H-tree CLK Clock is distributed in a tree-like fashion EE141 © Digital Integrated Circuits2nd 28 Timing Issues More realistic H-tree [Restle98] EE141 © Digital Integrated Circuits2nd 29 Timing Issues The Grid System G CL K D r iv e r D riv e r D r iv e r G C LK GC LK •No rc-matching •Large power D r iv e r G CL K EE141 © Digital Integrated Circuits2nd 30 Timing Issues. .. Integrated Circuits2nd 22 Timing Issues Latch timing When data arrives to transparent latch tD-Q D Q Latch is a ‘soft’ barrier Clk tClk-Q When data arrives to closed latch Data has to be ‘re-launched’ EE141 © Digital Integrated Circuits2nd 23 Timing Issues Single-Phase Clock with Latches φ Latch Logic Tskl Tskl Tskt Tskt Clk PW P EE141 © Digital Integrated Circuits2nd 24 Timing Issues Latch-Based Design... Timing Issues How to counter Clock Skew? REG In φ φ REG φ REG REG Negative Skew log Out φ Positive Skew Clock Distribution Data and Clock Routing EE141 © Digital Integrated Circuits2nd 20 Timing Issues Flip-Flop – Based Timing Skew φ Flip-flop delay Logic delay TSU Flip -flop φ=0 TClk-Q φ=1 Logic Representation after M Horowitz, VLSI Circuits 1996 EE141 © Digital Integrated Circuits2nd 21 Timing Issues. .. Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation 32 Timing Issues Clock Drivers EE141 © Digital Integrated Circuits2nd 33 Timing Issues Clock Skew in Alpha Processor EE141 © Digital Integrated Circuits2nd 34 Timing Issues EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS tcycle= 1.67ns trise = 0.35ns Global clock waveform tskew... L2 Latch Logic EE141 © Digital Integrated Circuits2nd 25 Timing Issues Slack-borrowing In L1 D Q CLB_A t p d,A a b CLK1 CLK1 L2 D Q CLK2 CLB_B t p d,B c L1 d D Q e CLK1 TC LK CLK2 slack passed to next stage t pd,A a valid EE141 © Digital Integrated Circuits2nd tD Q tpd,B b valid c valid t DQ e valid d valid 26 Timing Issues Latch-Based Timing Skew Static logic φ L1 Latch Logic L2 latch φ=1 L2... + CLK1 CLK2 TCLK 1 2 4 + th Launching edge arrives before the receiving edge EE141 © Digital Integrated Circuits2nd 11 Timing Issues Negative Skew TCLK + 1 CLK1 CLK2 2 TCLK 3 4 Receiving edge arrives before the launching edge EE141 © Digital Integrated Circuits2nd 12 Timing Issues Timing Constraints In R1 D Q Combinational Logic tCLK1 CLK tc − q tc − q, cd tsu, thold R2 D Q tCLK2 t tlogic Minimum cycle... (positive δ) EE141 © Digital Integrated Circuits2nd 13 Timing Issues Timing Constraints In R1 D Q Combinational Logic tCLK1 CLK tc − q tc − q, cd tsu, thold R2 D Q tCLK2 t tlogic Hold time constraint: t(c-q, cd) + t(logic, cd) > thold + δ Worst case is when receiving edge arrives late Race between data and clock EE141 © Digital Integrated Circuits2nd 14 Timing Issues Impact of Jitter CLK TC LK t j... width PLL EE141 © Digital Integrated Circuits2nd Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking 35 Timing Issues 21264 Clocking EE141 © Digital Integrated Circuits2nd 36 Timing Issues ... thold tjitter EE141 © Digital Integrated Circuits2nd Combinational Logic REGS cd t log ic t log ic, cd 15 Timing Issues Longest Logic Path in Edge-Triggered Systems TSU Clk TClk-Q TJI + δ TLM T Latest point of launching EE141 © Digital Integrated Circuits2nd Earliest arrival of next cycle 16 Timing Issues Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early,... TLM + TSU + δ + 2 TJI < can Skew T be either positive or negative EE141 © Digital Integrated Circuits2nd 17 Timing Issues Shortest Path Earliest point of launching Clk Clk TClk-Q TLm TH Nominal clock edge EE141 © Digital Integrated Circuits2nd Data must not arrive before this time 18 Timing Issues Clock Constraints in Edge-Triggered Systems If launching edge is early and receiving edge is late: Tc-q . Circuits 2nd Timing Issues Digital Integrated Digital Integrated Circuits Circuits A Design Perspective A Design Perspective Timing Issues Timing Issues Jan. 2nd Timing Issues Synchronous Timing Synchronous Timing Combinational Logic R 1 R 2 C in C out Out In CLK EE141 3 © Digital Integrated Circuits 2nd Timing