MSI MS 9826 rev 1 0 схема

5 MSI D CPU: MS-9826 Ver:1.0 Title AMD M2 Athlon 64 System Chipset: ATI RS690T ATI SB600 On Board Chipset: WINBOND Super I/O W83627DHG LAN*2 MARVELL 88E8056 BIOS SPI ROM 8M Block Diagram SB600 GPIO Config AMD M2 940 4,5,6 SYSTEM Memory DDR Terminations ATI RS690T 9-11 12 ATI SB600 13-16 PCI-Express X 1,PCI SLOT1 17 LAN*2 MARVELL 88E8056 18,19 LPC SUPER I/O& COM PORT 20 Main Memory: DDR * (Max 2GB) FAN/KB&MS/GPIO 21 HD Audio - ALC888 22 Expansion Slots: USB connectors 23 TV-OUT & VGA Connector & LVDS 24 ATX Connector / Front Panel /EMI 25 MS-6 ACPI Controller & MS-6+ 26 MS- 11 DDR2 1.8V POWER 27 PWM - ISL6312CR 28 RESERVE 29 MANUAL PARTS 30 RESERVE 31-33 34 GPIO&JUMPER/Option Part 34 POWER OK MAP 35 POWER MAP 36 RESET MAP 37 History 38 PCI 2.2 Slot X PWM: Controller Intersil ISL6312CR Phase Clock Generator: Controller ICS951464AGLFT Page Cover Sheet CLOCK Generator ICS 951464 C B D C B A A Micro Star Restricted Secret Title Rev Cover Sheet Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A Last Revision Date: Monday, February 25, 2008 Sheet 34 of MS-9826 128bit AMD M2 EXTERNAL CLOCK GENERATOR ICS951464 M2 SOCKET VGA PINHEAD IN OUT D DDRII 400,533,667,800 ECC UNBUFFERED DDRII DIMM1 DDRII 400,533,667,800 ECC UNBUFFERED DDRII DIMM2 D 16x16 HyperTransport ATI NB - RS690T HyperTransport LINK0 CPU I/F INTEGRATED GRAPHICS DDR2 MEMORY (X16) CRT VGA CONN LVDS/TVOUT/HDMI X4 PCIE I/F WITH SB X1 PCIE INTERFACE C Gb LAN MARVELL 88E8056 X1 PCIE I/F Gb LAN MARVELL 88E8056 C VER:A12 PCIE X4 rear IO USB#3 USB#2 USB#1 USB#0 ATI SB - SB600 USB2.0 (10) USB 2.0 SATA II (2 PORTS) pinhead USB#5 AZALIA HD AUDIO USB#4 ATA 66/100/133 SPI I/F reserverd SPI ROM SATA II I/F LPC I/F SPI I/F SATA#0 SATA#1 ACPI 1.1 INT RTC B ATA 66/100/133 I/F HW MONITOR IDE CONNECTOR B PCI/PCI BDGE PCI SLOT PCI BUS VER:A21 Winbond LPC SIO W83627DHG A A PWM SMART FAN*2 KBD MOUSE COM PORT *1 Micro Star Restricted Secret Title Block Diagram Rev 0A Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Friday, January 25, 2008 Sheet 34 of D C B A SB600 GPM Config SB600 GPIO Config GPIO Pin Type SSMUXSEL /SATA_IS3#/GPIO0 I/OD(3.3V) ROM_CS#/ GPIO1 I/O(3.3V) SPKR/ GPIO2 I/O(3.3V) FANOUT0/ GPIO3 I/O(3.3V) SMARTVOLT/SATA_IS2#/GPIO4 I/O(3.3V) SHUTDOWN#/ GPIO5 I/O(3.3V) GHI# /SATA_IS1#/GPIO6 I/OD(3.3V) WD_PWRGD/ GPIO7 I/O(3.3V) DDC1_SDA/ GPIO8 I/O(3.3V) DDC1_SCL/GPIO9 I/O(3.3V) SATA_IS0#/ GPIO10 I/O(3.3V) SPI_DO /GPIO11 I/O(S5_3.3V) SPI_DI /GPIO12 I/O(S5_3.3V) LAN_RST# /GPIO13 O(3.3V) ROM_RST# /GPIO14 I/O(3.3V) IDE_D[0 15] /GPIO[15 30] I/O(3.3V) SPI_HOLD# /GPIO31 I/O(S5_3.3V) SPI_CS# /GPIO32 I/O(S5_3.3V) INTE# /GPIO33 I/O(3.3V) INTF# /GPIO34 I/O(3.3V) INTG# /GPIO35 I/O(3.3V) INTH# /GPIO36 I/O(3.3V) DPSLP_OD# /GPIO37 I/O(3.3V) AC_BITCLK /GPIO38 I/O(3.3V) AC_SDOUT /GPIO39 I/O(3.3V) AC_SYNC /GPIO40 I/O(3.3V) SPDIF_OUT /PCICLK7/GPIO41 I/O(3.3V) ACZ_SDIN0 /GPIO42 I/O(S5_3.3V) ACZ_SDIN1 /GPIO43 I/O(S5_3.3V) ACZ_SDIN2 /GPIO44 I/O(S5_3.3V) AC_RST# /GPIO45 I/O(S5_3.3V) AC_SDIN3 /GPIO46 I/O(S5_3.3V) SPI_CLK /GPIO47 I/O(S5_3.3V) I/O(3.3V) FANOUT1/ GPIO48 I/O(3.3V) FANOUT2/ GPIO49 I/O(3.3V) FANIN0/ GPIO50 I/O(3.3V) FANIN1/ GPIO51 I/O(3.3V) FANIN2/ GPIO52 I/O(3.3V) VIN[0 7]/GPIO[53 60] I/O(3.3V) TEMPIN0/ GPIO61 I/O(3.3V) TEMPIN1/ GPIO62 I/O(3.3V) TEMPIN2/ GPIO63 I/O(3.3V) TEMPIN3/TALERT#/ GPIO64 I/O(3.3V) BMREQ#/REQ5#/GPIO65 I/O(S5_3.3V) LLB#/ GPIO66 SATA_ACT# /GPIO67 OD(3.3V) I/O(3.3V) LDRQ1#/GNT5#/ GPIO68 RTC_IRQ#/GPIO69 I/O(S5_3.3V)/VBAT REQ3# /GPIO70 I/O(3.3V) REQ4# /GPIO71 I/O(3.3V) GNT3# /GPIO72 I/O(3.3V) GNT4# /GPIO73 I/O(3.3V) Default Output(Low) by Strapping Input(TS) Input(PU) Input(TS) Input(TS) Output(TS) by Strapping Input(TS) Input(TS) Input(TS) Output(PD) Output(PD) Output(Low) Output(Low) Output(High) Input(PU) Input(PU) Input(PU) Input(PU) Input(PU) Input(PU) Input(TS) Input(PD) Output(Low) Output(Low) Output(Low) Input(PD) Input(PD) Input(PD) Output(Low) Input(PD) Input(PD) Input(PU) Input(PU) Input(TS) Input(TS) Input(TS) Input(TS) Input(TS) Input(TS) Input(TS) Input(TS) Input(TS) Input(PU) Output(TS) Input(PU) Input(PU) Input(PU) Input(PU) Output(TS) Output(TS) Power Main Main Main Main Main Main Main Main Main Main Main Standby Standby Main Main Main Standby Standby Main Main Main Main Main Main Main Main Main Standby Standby Standby Standby Standby Standby Main Main Main Main Main Main Main Main Main Main Main Standby Main Main Standby Main Main Main Main Default Power GPM Pin Type Function Function Standby USB OverCurrent for PORT0,1,2,3 Input(PU) USB_OC0#/ GPM#0 I/O(S5_3.3V) NC Standby USB OverCurrent for PORT0,1,2,3 Input(PU) I/O(S5_3.3V) USB_OC1#/ GPM#1 NC Standby USB OverCurrent for PORT0,1,2,3 Input(PU) I/O(S5_3.3V) USB_OC2#/ GPM#2 NC Standby USB OverCurrent for PORT0,1,2,3 Input(PU) I/O(S5_3.3V) USB_OC3#/ GPM#3 NC Output(Low) Standby USB OverCurrent for PORT4,5 I/O(S5_3.3V) USB_OC4#/ GPM#4 NC Standby USB OverCurrent for PORT4,5 I/O/OD(S5_3.3V) Input(PU) USB_OC5#/DDR3_RST#/GPM#5 NC Standby GPM6# Input(PU) I/O(S5_3.3V) BLINK/ GPM#6 NC Standby SYS_RESET# (Not Default) Input(PU) I/O(S5_3.3V) SYS_RESET#/GPM#7 NC Standby NC Input(PU) GPM#8 I/O(S5_3.3V) USB_OC8#/AZ_DOCK_RST#/ (Not Default) AUXGPIO_DIR2 Standby NC Input(PD) GPM#9 I/O(S5_3.3V) USB_OC9#/SLP_S2#/ (Not Default) IDE Detect AUXGPIO_DIR1 (Not Default) SB600 GPOC Config SPI_DO Default Power GPOC Pin Type Function SPI_DI Main Input(TS) SMBUS1 (Not Default) I/O(3.3V) SCL0/ GPOC0# NC (Not Default) Input(TS) Main SMBUS1 SDA0/GPOC1# I/O(3.3V) NC (Not Default) Input(TS) Standby GPOC2# SMBUS2 SCL1/ I/O(S5_3.3V) IDE_D[0 15] Standby SMBUS2 (Not Default) SDA1/GPOC3# I/O(S5_3.3V) Input(TS) SPI_HOLD# SPI_CS# INTE# SB600 EXTEVENT & GEVENT Config INTF# Default Power GPM Pin Type Function Standby Input(PU) INTG# I/O(S5_3.3V) NC RI#/ EXTEVENT0# Main Input(PU) INTH# I/O(3.3V) LPC_SMI#/ EXTEVENT1# NC Standby THRMTRIP# (Reserved) Input(PU) I/O(S5_3.3V) SMBALERT#/ THRMTRIP#/GEVENT2# NC Standby LPC_PME# (Not Default) Input(PU) I/O(S5_3.3V) LPC_PME#/ GEVENT3# NC Standby PCI_PME# (Not Default) Input(PU) PIN Straps I/O(S5_3.3V) PCI_PME#/ GEVENT4# by Strapping Standby I/O(S5_3.3V) S3_STATE/ GEVENT5# NC NC Standby Input(PU) I/O(S5_3.3V) USB_OC6#/ GEVENT6# NC NC Standby Input(PU) NC I/O(S5_3.3V) USB_OC7#/ GEVENT7# NC Standby PCIE_WAKE# (Not Default) Input(PU) I/O(S5_3.3V) WAKE#/ GEVENT8# NC NC PCI Config NC GPIO46 SPI_CLK CLOCK REQ# GNT# IDSEL INTA# INTB# INTC# INTD# AMP_GAIN0 (Program to Output) AMP_GAIN0 (Program to Output) IEEE 1394 AMP_EN GIGA LAN NC (Program to Output) NC (Program to Output) PCI1 NC (Program to Output) NC (Program to Output) PCI2 NC (Program to Output) NC (Program to Output) Super I/O TALERT# (Not Default) BMREQ# (Not Default) NC SATA_ACT# NC NC NC NC NC NC Micro Star Restricted Secret Title B A 0A MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw C Rev GPIO Document Number D Last Revision Date: Monday, December 24, 2007 Sheet 34 of VCC_1V2 HT_CADIN_H[15 0] HT_CADIN_H[15 0] HT_CADIN_L[15 0] HT_CADIN_L[15 0] HT_CADOUT_H[15 0] HT_CADOUT_H[15 0] C247 HT_CADOUT_L[15 0] HT_CADOUT_L[15 0] C221 C222 X_C180P50N0402 X_C180P50N0402 C180P50N0402 VDDA_25 VDDA25 D D 300mA VCC_1V2 C220 VDDA25 at least 15mil CLOSE TO VLDT PIN C248 80S/0805 L8 C4.7U10Y0805 C251 C219 C245 C141 C180P50N0402 X_C180P50N0402 C4.7U10Y0805 12 CPU_CLK C139 C143 R93 C142 C3900P25X C4.7U10Y0805 0.22u_10V_0402 0.22u_10V_0402 169R1%0402 0.22u_10V_0402 12 CPU1A HYPERTRANSPORT VCC_1V2 R125 R127 9 C N6 P6 N3 N2 HT_CLKIN_H1 HT_CLKIN_L1 HT_CLKIN_H0 HT_CLKIN_L0 51R1%0402 51R1%0402 V4 V5 U1 V1 HT_CTLIN_H0 HT_CTLIN_L0 HT_CADIN_H15 HT_CADIN_L15 HT_CADIN_H14 HT_CADIN_L14 HT_CADIN_H13 HT_CADIN_L13 HT_CADIN_H12 HT_CADIN_L12 HT_CADIN_H11 HT_CADIN_L11 HT_CADIN_H10 HT_CADIN_L10 HT_CADIN_H9 HT_CADIN_L9 HT_CADIN_H8 HT_CADIN_L8 U6 V6 T4 T5 R6 T6 P4 P5 M4 M5 L6 M6 K4 K5 J6 K6 HT_CADIN_H7 HT_CADIN_L7 HT_CADIN_H6 HT_CADIN_L6 HT_CADIN_H5 HT_CADIN_L5 HT_CADIN_H4 HT_CADIN_L4 HT_CADIN_H3 HT_CADIN_L3 HT_CADIN_H2 HT_CADIN_L2 HT_CADIN_H1 HT_CADIN_L1 HT_CADIN_H0 HT_CADIN_L0 U3 U2 R1 T1 R3 R2 N1 P1 L1 M1 L3 L2 J1 K1 J3 J2 L0_CLKIN_H(1) L0_CLKIN_L(1) L0_CLKIN_H(0) L0_CLKIN_L(0) L0_CTLIN_H(1) L0_CTLIN_L(1) L0_CTLIN_H(0) L0_CTLIN_L(0) L0_CADIN_H(15) L0_CADIN_L(15) L0_CADIN_H(14) L0_CADIN_L(14) L0_CADIN_H(13) L0_CADIN_L(13) L0_CADIN_H(12) L0_CADIN_L(12) L0_CADIN_H(11) L0_CADIN_L(11) L0_CADIN_H(10) L0_CADIN_L(10) L0_CADIN_H(9) L0_CADIN_L(9) L0_CADIN_H(8) L0_CADIN_L(8) L0_CLKOUT_H(1) L0_CLKOUT_L(1) L0_CLKOUT_H(0) L0_CLKOUT_L(0) AD5 AD4 AD1 AC1 L0_CTLOUT_H(1) L0_CTLOUT_L(1) L0_CTLOUT_H(0) L0_CTLOUT_L(0) Y6 W6 W2 W3 L0_CADOUT_H(15) L0_CADOUT_L(15) L0_CADOUT_H(14) L0_CADOUT_L(14) L0_CADOUT_H(13) L0_CADOUT_L(13) L0_CADOUT_H(12) L0_CADOUT_L(12) L0_CADOUT_H(11) L0_CADOUT_L(11) L0_CADOUT_H(10) L0_CADOUT_L(10) L0_CADOUT_H(9) L0_CADOUT_L(9) L0_CADOUT_H(8) L0_CADOUT_L(8) L0_CADIN_H(7) L0_CADIN_L(7) L0_CADIN_H(6) L0_CADIN_L(6) L0_CADIN_H(5) L0_CADIN_L(5) L0_CADIN_H(4) L0_CADIN_L(4) L0_CADIN_H(3) L0_CADIN_L(3) L0_CADIN_H(2) L0_CADIN_L(2) L0_CADIN_H(1) L0_CADIN_L(1) L0_CADIN_H(0) L0_CADIN_L(0) L0_CADOUT_H(7) L0_CADOUT_L(7) L0_CADOUT_H(6) L0_CADOUT_L(6) L0_CADOUT_H(5) L0_CADOUT_L(5) L0_CADOUT_H(4) L0_CADOUT_L(4) L0_CADOUT_H(3) L0_CADOUT_L(3) L0_CADOUT_H(2) L0_CADOUT_L(2) L0_CADOUT_H(1) L0_CADOUT_L(1) L0_CADOUT_H(0) L0_CADOUT_L(0) Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4 Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1 HT_CLKOUT_H1 HT_CLKOUT_L1 HT_CLKOUT_H0 HT_CLKOUT_L0 CPUCLKIN CPUCLKIN# CPU_CLK# VCC_DDR 9 9 C3900P25X TP26 TP27 13 13 HT_CTLOUT_H0 HT_CTLOUT_L0 LDT_PWRGD CPU_LDTSTOP# LDT_RST# LDT_RST# R141 300/4 C204 X_1000P/50V/X7R/4 AL6 AK6 VCC_DDR 27 27 TP17 TP20 TP23 TP16 CPU_TDI CPU_TRST_L CPU_TCK CPU_TMS TP10 CPU_DBREQ_L A5 COREFB+ COREFB- G2 G1 COREFB+ COREFBTP34 R153 39.2R1%0402 CPU_VTT_SENSE AL10 AJ10 AH10 AL9 E12 F12 AH11 AJ11 R137 39.2R1%0402 R91 R90 R180,R170 TO CPU LESS THAN 1000MIL TP5 TP6 TP7 TP8 TP24 20 THERMDC_CPU 20 THERMDA_CPU B CPU_TEST25_H CPU_TEST25_L 300/4 300/4 27 VDDA1 VDDA2 PWROK LDTSTOP_L RESET_L CPU_PRESENT_L SIC SID VID(5) VID(4) VID(3) VID(2) VID(1) VID(0) THERMTRIP_L PROCHOT_L TDI TRST_L TCK TMS TDO D2 D1 C1 E3 E2 E1 VID5 VID4 VID3 VID2 VID1 VID0 R152 AK7 AL7 CPU_THRIP_L# PROCHOT_L AK10 CPU_TDO R143 300/4 DBRDY VDDIO_FB_H VDDIO_FB_L CPU_THRIP# TP19 M_VREF M_ZN M_ZP TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 D6 E7 F8 C5 AH9 TEST17 TEST16 TEST15 TEST14 TEST12 E5 AJ5 AG9 AG8 AH7 AJ6 TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 R144 300/4 14 PROCHOT_L 20 TP11 B6 CPU_DBRDY AK11 AL11 CPU_VDDIOFB_H CPU_VDDIOFB_L PSI_L F1 HTREF1 HTREF0 V8 V7 VTT_SENSE A10 B10 F10 E9 AJ7 F6 VCC_DDR 4.7K/4 Q20 N-MMBT3904_NL_SOT23 From SIO for System-Initiated throttling DBREQ_L VDD_FB_H VDD_FB_L VCC_DDR VCC_DDR R89 300/4 CLKIN_H CLKIN_L C R138 VCC_DDR 300/4 CPU_PSI_L TP9 VCC_1V2 R131 44.2KR1%0402 CPU_M_VREF M_ZN M_ZP HT_CADOUT_H7 HT_CADOUT_L7 HT_CADOUT_H6 HT_CADOUT_L6 HT_CADOUT_H5 HT_CADOUT_L5 HT_CADOUT_H4 HT_CADOUT_L4 HT_CADOUT_H3 HT_CADOUT_L3 HT_CADOUT_H2 HT_CADOUT_L2 HT_CADOUT_H1 HT_CADOUT_L1 HT_CADOUT_H0 HT_CADOUT_L0 C9 D8 C7 CPU_PRESENT_L AL3 CPU_SIC CPU_SID HT_CADOUT_H15 HT_CADOUT_L15 HT_CADOUT_H14 HT_CADOUT_L14 HT_CADOUT_H13 HT_CADOUT_L13 HT_CADOUT_H12 HT_CADOUT_L12 HT_CADOUT_H11 HT_CADOUT_L11 HT_CADOUT_H10 HT_CADOUT_L10 HT_CADOUT_H9 HT_CADOUT_L9 HT_CADOUT_H8 HT_CADOUT_L8 C10 D10 VID[0 5] VCC_DDR MISC A8 B8 13 LDT_PWRGD 13 R142 X_300/4 CPU1D 3300P/50V/4 C140 9 9 Required for compatibility with future processors C246 TEST29_H TEST29_L C11 D11 HTREF1 HTREF0 R129 44.2KR1%0402 TEST29H TEST29L C212 1000P/50V/X7R/4 C207 1000P/50V/X7R/4 R92 80.6R1%0402 TEST24 TEST23 TEST22 TEST21 TEST20 AK8 AH8 AJ9 AL8 AJ8 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 J10 H9 AK9 AK5 G7 D4 TP21 TP25 TP18 TEST29_L and TEST29_H should be routed as a differential pair with 80 Ohm impedance TP22 R145 300/4 VCC_DDR R140 300/4 B ZIF-SOCKET940 ZIF-SOCKET940 VCC_DDR VCC_DDR CPU_M_VREF R83 16.9 1% CPU_PRESENT_L CPU_TEST25_H R139 R88 1K/4 1% 510R CPU_TEST25_L R87 510R U25 10,13 LDT_STOP# LDT_STOP# 680 R309 D6 BAT54S9 R307 OE A GND VCC +1.8V_S0 R82 Y CPU_LDTSTOP# 16.9 1% C118 0.1u/10V/4 C117 1000P/50V/X7R/4 SN74LVC1G17 8.87K/4 C467 47p A A LDT_RST# LDT_PWRGD R126 R128 680 680 Micro Star Restricted Secret Title Rev M2 HT I/F CTRL & DEBUG Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Friday, February 22, 2008 Sheet of 34 0A MEM_MB_DQS_L[8 0] MEM_MA_DQS_L[8 0] MEM_MB_DQS_H[8 0] MEM_MA_DQS_H[8 0] MEM_MB_DM[8 0] MEM_MA_DM[8 0] D D CPU1B 7,8 7,8 7,8 7,8 MEM_MA0_CLK_H2 MEM_MA0_CLK_L2 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 7,8 MEM_MA0_CLK_H0 7,8 MEM_MA0_CLK_L0 7,8 MEM_MA0_CS_L1 7,8 MEM_MA0_CS_L0 7,8 MEM_MA0_ODT0 MEM_MA0_CLK_H2 AG21 MEM_MA0_CLK_L2 AG20 MEM_MA0_CLK_H1 G19 MEM_MA0_CLK_L1 H19 MEM_MA0_CLK_H0 U27 MEM_MA0_CLK_L0 U26 MEM_MA0_CS_L1 MEM_MA0_CS_L0 AC25 AA24 MA0_CS_L(1) MA0_CS_L(0) MEM_MA0_ODT0 AC28 MA0_ODT(0) remove MEM_MA1_CS_L0,L1, MA1_ODT0,MA_CKE1 C 7,8 MEM_MA_CAS_L 7,8 MEM_MA_WE_L 7,8 MEM_MA_RAS_L 7,8 MEM_MA_BANK2 7,8 MEM_MA_BANK1 7,8 MEM_MA_BANK0 7,8 MEM_MA_CKE0 7,8 MEM_MA_ADD[15 0] B MEMORY INTERFACE A MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0) AE20 AE19 G20 G21 V27 W27 MA1_CLK_H(2) MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0) AD27 AA25 MA1_CS_L(1) MA1_CS_L(0) AC27 MA1_ODT(0) MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L AB25 AB27 AA26 MA_CAS_L MA_WE_L MA_RAS_L MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0 N25 Y27 AA27 MA_BANK(2) MA_BANK(1) MA_BANK(0) MEM_MA_CKE0 L27 M25 MA_CKE(1) MA_CKE(0) MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0 M27 N24 AC26 N26 P25 Y25 N27 R24 P27 R25 R26 R27 T25 U25 T27 W24 MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0) MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0 AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28 D29 C29 C25 D25 E19 F19 F15 G15 MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0) MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0 AF15 AF19 AJ25 AH29 B29 E24 E18 H15 MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0) MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10) MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0) AE14 MEM_MA_DATA63 AG14 MEM_MA_DATA62 AG16 MEM_MA_DATA61 AD17 MEM_MA_DATA60 AD13 MEM_MA_DATA59 AE13 MEM_MA_DATA58 AG15 MEM_MA_DATA57 AE16 MEM_MA_DATA56 AG17 MEM_MA_DATA55 AE18 MEM_MA_DATA54 AD21 MEM_MA_DATA53 AG22 MEM_MA_DATA52 AE17 MEM_MA_DATA51 AF17 MEM_MA_DATA50 AF21 MEM_MA_DATA49 AE21 MEM_MA_DATA48 AF23 MEM_MA_DATA47 AE23 MEM_MA_DATA46 AJ26 MEM_MA_DATA45 AG26 MEM_MA_DATA44 AE22 MEM_MA_DATA43 AG23 MEM_MA_DATA42 AH25 MEM_MA_DATA41 AF25 MEM_MA_DATA40 AJ28 MEM_MA_DATA39 AJ29 MEM_MA_DATA38 AF29 MEM_MA_DATA37 AE26 MEM_MA_DATA36 AJ27 MEM_MA_DATA35 AH27 MEM_MA_DATA34 AG29 MEM_MA_DATA33 AF27 MEM_MA_DATA32 E29 MEM_MA_DATA31 E28 MEM_MA_DATA30 D27 MEM_MA_DATA29 C27 MEM_MA_DATA28 G26 MEM_MA_DATA27 F27 MEM_MA_DATA26 C28 MEM_MA_DATA25 E27 MEM_MA_DATA24 F25 MEM_MA_DATA23 E25 MEM_MA_DATA22 E23 MEM_MA_DATA21 D23 MEM_MA_DATA20 E26 MEM_MA_DATA19 C26 MEM_MA_DATA18 G23 MEM_MA_DATA17 F23 MEM_MA_DATA16 E22 MEM_MA_DATA15 E21 MEM_MA_DATA14 F17 MEM_MA_DATA13 G17 MEM_MA_DATA12 G22 MEM_MA_DATA11 F21 MEM_MA_DATA10 G18 MEM_MA_DATA9 E17 MEM_MA_DATA8 G16 MEM_MA_DATA7 E15 MEM_MA_DATA6 G13 MEM_MA_DATA5 H13 MEM_MA_DATA4 H17 MEM_MA_DATA3 E16 MEM_MA_DATA2 E14 MEM_MA_DATA1 G14 MEM_MA_DATA0 MA_DQS_H(8) MA_DQS_L(8) J28 J27 MEM_MA_DQS_H8 MEM_MA_DQS_L8 MA_DM(8) J25 MEM_MA_DM8 MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0) K25 J26 G28 G27 L24 K27 H29 H27 CPU1C MEM_MA_DATA[63 0] 7,8 7,8 7,8 7,8 MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 7,8 MEM_MB0_CLK_H0 7,8 MEM_MB0_CLK_L0 7,8 MEM_MB0_CS_L1 7,8 MEM_MB0_CS_L0 7,8 MEM_MB0_ODT0 MEM_MB0_CLK_H2 AJ19 MEM_MB0_CLK_L2 AK19 MEM_MB0_CLK_H1 A18 MEM_MB0_CLK_L1 A19 MEM_MB0_CLK_H0 U31 MEM_MB0_CLK_L0 U30 MEM_MB0_CS_L1 MEM_MB0_CS_L0 AE30 AC31 MB0_CS_L(1) MB0_CS_L(0) MEM_MB0_ODT0 AD29 MB0_ODT(0) AL19 AL18 C19 D19 W29 W28 MB1_CLK_H(2) MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0) remove MEM_MB1_CS_L0,L1,MB1_ODT0,MB_CKE1 7,8 MEM_MB_CAS_L 7,8 MEM_MB_WE_L 7,8 MEM_MB_RAS_L 7,8 MEM_MB_BANK2 7,8 MEM_MB_BANK1 7,8 MEM_MB_BANK0 7,8 MEM_MB_CKE0 7,8 MEM_MB_ADD[15 0] AE29 AB31 MB1_CS_L(1) MB1_CS_L(0) AD31 MB1_ODT(0) MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L AC29 AC30 AB29 MB_CAS_L MB_WE_L MB_RAS_L MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0 N31 AA31 AA28 MB_BANK(2) MB_BANK(1) MB_BANK(0) MEM_MB_CKE0 MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0 M31 M29 N28 N29 AE31 N30 P29 AA29 P31 R29 R28 R31 R30 T31 T29 U29 U28 AA30 MEM_MB_DQS_H7 AK13 MEM_MB_DQS_L7 AJ13 MEM_MB_DQS_H6 AK17 MEM_MB_DQS_L6 AJ17 MEM_MB_DQS_H5 AK23 MEM_MB_DQS_L5 AL23 MEM_MB_DQS_H4 AL28 MEM_MB_DQS_L4 AL29 MEM_MB_DQS_H3 D31 MEM_MB_DQS_L3 C31 MEM_MB_DQS_H2 C24 MEM_MB_DQS_L2 C23 MEM_MB_DQS_H1 D17 MEM_MB_DQS_L1 C17 MEM_MB_DQS_H0 C14 MEM_MB_DQS_L0 C13 DDRA_CB7 DDRA_CB6 DDRA_CB5 DDRA_CB4 DDRA_CB3 DDRA_CB2 DDRA_CB1 DDRA_CB0 MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0 ZIF-SOCKET940 MEMORY INTERFACE B MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0) AJ14 AH17 AJ23 AK29 C30 A23 B17 B13 MB_CKE(1) MB_CKE(0) MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0) MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0) MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0) MEM_MB_DATA[63 0] MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10 MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0 MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10) MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0) AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13 MB_DQS_H(8) MB_DQS_L(8) J31 J30 MEM_MB_DQS_H8 MEM_MB_DQS_L8 MB_DM(8) J29 MEM_MB_DM8 MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0) K29 K31 G30 G29 L29 L28 H31 G31 C B DDRB_CB7 DDRB_CB6 DDRB_CB5 DDRB_CB4 DDRB_CB3 DDRB_CB2 DDRB_CB1 DDRB_CB0 ZIF-SOCKET940 DDRB_CB[7:0] A A DDRA_CB[7:0] Micro Star Restricted Secret Title Rev M2 DDR MEMORY I/F Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Friday, February 22, 2008 Sheet of 34 0A VCCP 0.8375~1.6V / 65A A4 A6 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AC4 AC5 AC8 AC10 AD2 AD3 AD7 AD9 AE10 AF7 AF9 AG4 AG5 AG7 AH2 AH3 B3 B5 B7 C2 C4 C6 C8 D3 D5 D7 D9 E4 E6 E8 E10 F5 F7 F9 F11 G6 G8 G10 G12 H7 H11 H23 J8 J12 J14 J16 J18 J20 J22 J24 K7 K9 K11 K13 K15 K17 K19 K21 K23 L4 L5 L8 L10 L12 Y17 Y19 C B VCCP CPU1F VCCP VDD1 D VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD150 VDD151 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS240 VSS241 A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE9 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16 VCC_1V2 CPU1G L14 L16 L18 M2 M3 M7 M9 M11 M13 M15 M17 M19 N8 N10 N12 N14 N16 N18 P7 P9 P11 P13 P15 P17 P19 R4 R5 R8 R10 R12 R14 R16 R18 R20 T2 T3 T7 T9 T11 T13 T15 T17 T19 T21 U8 U10 U12 U14 U16 U18 U20 V9 V11 V13 V15 V17 V19 V21 W4 W5 W8 W10 W12 W14 W16 W18 W20 Y2 Y3 Y7 Y9 Y11 Y13 Y15 Y21 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 CPU1I 500mA CPU1H VDDIO VDD3 VDD2 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18 H22 H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18 AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 AC12 AC14 AC16 AC18 AC20 AC22 AD11 AD23 AE12 AF11 L20 L22 M21 M23 N20 N22 P21 P23 R22 T23 U22 V23 W22 Y23 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 NC1 NC2 NC3 NC4 GND GND GND VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 N17 N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22 VTT_DDR AJ4 AJ3 AJ2 AJ1 VLDT_A1 VLDT_A2 VLDT_A3 VLDT_A4 D12 C12 B12 A12 VTT1 VTT2 VTT3 VTT4 1.75A VCC_DDR 3.6A AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30 AF30 M24 M26 M28 M30 P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29 VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4 VTT5 VTT6 VTT7 VTT8 VTT9 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VLDT_RUN_B H6 H5 H2 H1 C138 VTT_DDR C4.7U10Y0805 AK12 AJ12 AH12 AG12 AL12 D K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15 C ZIF-SOCKET940 VCCP C468 C407 C466 C398 ZIF-SOCKET940 C445 0.01u_16V_0402 0.22u_10V_0402 180P B 0.22u_10V_0402 0.22u_10V_0402 VCCP ZIF-SOCKET940 ZIF-SOCKET940 22u_6V_0805 22u_6V_0805 22u_6V_0805 C423 C443 C408 0.22u 0402 X4 4.7u 0805 X4 1000p 0402 X4 22u_6V_0805 C431 22u_6V_0805 22u_6V_0805 22u_6V_0805 22u_6V_0805 22u_6V_0805 22u_6V_0805 22u_6V_0805 22u_6V_0805 C424 C451 C458 C432 C456 C400 C444 C402 180p 0402 X4 VTT_DDR between CPU and DIMM VCC_DDR VCC_DDR 180p C127 C258 C259 C124 0.22u C4.7U10Y0805 C126 C264 1000P 1000P C144 VCC_DDR 0.22u_10V_0402 C145 C470 180p C4.7U10Y0805 C426 C410 C460 C430 C403 C475 C447 C453 C405 C439 C471 0.22u 180p 0.22u 180p C4.7U10Y0805 180p 0.22u_10V_0402 C4.7U10Y0805 C4.7U10Y0805 C4.7U10Y0805 0.22u_10V_0402 A 22u_6V_0805 22u_6V_0805 22u_6V_0805 C409 C401 C461 VTT_DDR 180p A CPU Bottom VCC_DDR C133 C263 C260 0.22u C4.7U10Y0805 C125 C134 C257 C242 C241 22u_6V_0805 0.22u_10V_0402 22u_6V_0805 C421 22u_6V_0805 Micro Star Restricted Secret 0.01u_16V_0402 C465 C406 180P 180p Title C459 C433 C4.7U10Y0805 0.22u_10V_0402 1000P 1000P 180p 180p C452 Rev AM2 PWR & GND Document Number C427 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A MS-9826 Last Revision Date: Thursday, February 21, 2008 Sheet of 34 A B C D E MEM_MB_DQS_L[8 0] MEM_MB_DATA[63 0] MEM_MA_DATA[63 0] 5 MEM_MB_DQS_H[8 0] MEM_MB_DM[8 0] VCC_DDR DDRA_CB[7:0] 188 183 63 182 61 60 180 58 179 177 70 57 176 196 174 173 WE# CAS# RAS# 73 74 192 DM0/DQS9 NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17# 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165 ODT0 ODT1 CKE0 CKE1 CS0# CS1# VCC_DDR R38 IN MEM_MA_WE_L 5,8 IN MEM_MA_CAS_L 5,8 IN MEM_MA_RAS_L 5,8 MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7 MEM_MA_DM8 MEM_MA0_ODT0 52 171 MEM_MA_CKE0 5,8 193 76 MEM_MA0_CS_L0 5,8 MEM_MA0_CS_L1 5,8 MEM_MA0_CLK_H0 MEM_MA0_CLK_L0 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H2 MEM_MA0_CLK_L2 SCL SDA 120 119 SCL SDA MEM_MA0_CLK_H0 MEM_MA0_CLK_L0 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H2 MEM_MA0_CLK_L2 VCC_DDR C65 C0.1U10X0402 239 240 101 PLACE CLOSE TO DIMM PIN C217 C0.1U10X0402 C215 C0.1U10X0402 EC4 C330U2.5POS-1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DDRB_CB[7:0] 42 43 48 49 161 162 167 168 238 5,8 MEM_MB_BANK[2 0] CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 51 56 62 72 75 78 191 194 181 175 170 53 59 64 197 69 172 187 184 178 189 67 55 18 19 102 68 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15 188 183 63 182 61 60 180 58 179 177 70 57 176 196 174 173 A16/BA2 BA1 BA0 54 190 71 MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0 WE# CAS# RAS# 73 74 192 MEM_MB_WE_L MEM_MB_CAS_L MEM_MB_RAS_L DM0/DQS9 NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17# 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165 MEM_MB_DM0 ODT0 ODT1 195 77 CKE0 CKE1 52 171 CS0# CS1# 193 76 CK0(DU) CK0#(DU) CK1(CK0) CK1#(CK0#) CK2(DU) CK2#(DU) 185 186 137 138 220 221 SCL SDA 120 119 VREF SA0 SA1 SA2 MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H8 MEM_MB_DQS_L8 DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 DQS7# DQS8 DQS8# 100 103 106 109 112 115 118 121 124 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 198 201 204 207 210 213 216 219 222 225 228 231 234 237 ADDRESS: 000 DDRII-240_blue 0xA0 MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15 IN MEM_MB_WE_L 5,8 IN MEM_MB_CAS_L 5,8 IN MEM_MB_RAS_L 5,8 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7 MEM_MB_DM8 MEM_MB0_ODT0 MEM_MB0_ODT0 5,8 MEM_MB_CKE0 5,8 MEM_MB0_CS_L0 5,8 MEM_MB0_CS_L1 5,8 MEM_MB0_CLK_H0 MEM_MB0_CLK_L0 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 MEM_MB0_CLK_H0 MEM_MB0_CLK_L0 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 5,8 5,8 5,8 5,8 5,8 5,8 SCL SDA DIMM_VREF_B 239 240 101 C45 C0.1U10X0402 VCC3 PLACE CLOSE TO DIMM PIN ADDRESS: 001 0xA2 DDRII-240_blue VCC_DDR C173 C2.2U6.3X5 DDR2 DIMM1 49.9R1%0402 DIMM_VREF_A 5,8 5,8 5,8 5,8 5,8 5,8 Layout note: Place capacitors between and near DDR connector if possible DIMM_VREF_A 11 14 17 20 23 26 29 32 35 38 41 44 47 50 65 66 79 82 85 88 91 94 97 MEM_MA0_ODT0 5,8 185 186 137 138 220 221 SA0 SA1 SA2 SDA SCL 195 77 MEM_MA_WE_L MEM_MA_CAS_L MEM_MA_RAS_L CK0(DU) CK0#(DU) CK1(CK0) CK1#(CK0#) CK2(DU) CK2#(DU) VREF 12,14 SDA 12,14 SCL MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0 54 190 71 A16/BA2 BA1 BA0 MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 VDDSPD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15 MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63 MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H8 MEM_MA_DQS_L8 VDD0 VDD1 VDD2 VDD3 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ7 VDDQ8 VDDQ9 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VDDSPD VDD0 VDD1 VDD2 VDD3 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ7 VDDQ8 VDDQ9 RC0 RC1 NC NC/TEST NC 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 100 103 106 109 112 115 118 121 124 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 198 201 204 207 210 213 216 219 222 225 228 231 234 237 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 DQS7# DQS8 DQS8# + 11 14 17 20 23 26 29 32 35 38 41 44 47 50 65 66 79 82 85 88 91 94 97 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 RC0 RC1 NC NC/TEST NC 42 43 48 49 161 162 167 168 238 51 56 62 72 75 78 191 194 181 175 170 53 59 64 197 69 172 187 184 178 189 67 55 18 19 102 68 DIMM2 MEM_MA_DQS_H[8 0] MEM_MA_DM[8 0] MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63 5,8 MEM_MB_ADD[15 0] MEM_MA_DQS_L[8 0] DIMM1 VCC3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC3 VCC_DDR DDRB_CB0 DDRB_CB1 DDRB_CB2 DDRB_CB3 DDRB_CB4 DDRB_CB5 DDRB_CB6 DDRB_CB7 DDRA_CB0 DDRA_CB1 DDRA_CB2 DDRA_CB3 DDRA_CB4 DDRA_CB5 DDRA_CB6 DDRA_CB7 5,8 MEM_MA_BANK[2 0] 5,8 MEM_MA_ADD[15 0] C223 C2.2U6.3X5 C227 C2.2U6.3X5 C174 C2.2U6.3X5 DDR2 DIMM2 VCC_DDR R37 VCC_DDR B Reserve for EMI C234 C0.1U10X0402 C177 C0.1U10X0402 VCC_DDR R23 C0.1U10X0402 EC20 C330U2.5POS-1 AMD design guide just need the caps in page 6, ADD SOME BULK, DECOUPLE CAP, NEED POWER TEAM CONFIRM Layout note: Place capacitors between and near DDR connector if possible A change DIP to SMD, EC39,EC40 (1214) + 49.9R1%0402 49.9R1%0402 DIMM_VREF_B C176 R22 Micro Star Restricted Secret 49.9R1%0402 Title R381,382,385,386 CHANGE TO 49.9R (1217) Document Number Rev MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw C D E Last Revision Date: Friday, February 22, 2008 Sheet of 34 0A 8P4R-47_RN0402 8P4R-47_RN0402 8P4R-47_RN0402 8P4R-47_RN0402 8P4R-47_RN0402 8P4R-47_RN0402 MEM_MA_ADD[15 0] 5,7 MEM_MA_ADD[15 0] MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0 D MEM_MA_ADD15 MEM_MB_BANK2 MEM_MA_ADD14 MEM_MB_ADD2 MEM_MA_ADD1 MEM_MA_ADD5 MEM_MA_ADD2 MEM_MA0_CS_L0 MEM_MB_WE_L MEM_MB0_CS_L0 MEM_MA_WE_L MEM_MB0_ODT0 MEM_MA0_ODT0 MEM_MB_ADD13 MEM_MB0_CS_L1 MEM_MA_BANK[2 0] 5,7 MEM_MA_BANK[2 0] MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0 5,7 MEM_MA_CAS_L 5,7 MEM_MA_WE_L 5,7 MEM_MA_RAS_L 5,7 MEM_MA0_CS_L0 5,7 MEM_MA0_CS_L1 5,7 MEM_MA0_ODT0 MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L MEM_MB_ADD12 MEM_MB_ADD11 MEM_MA_ADD11 MEM_MB_ADD9 MEM_MB_ADD7 MEM_MA_ADD8 MEM_MA_ADD6 MEM_MB_ADD8 8P4R-47_RN0402 8P4R-47_RN0402 MEM_MA0_CS_L0 MEM_MA0_CS_L1 MEM_MA0_ODT0 C 5,7 MEM_MA_CKE0 5,7 MEM_MB_BANK[2 0] after swap (1214) VTT_DDR RN6 7 7 8 8 7 RN8 RN9 RN12 RN16 RN18 MEM_MA_ADD10 MEM_MA_ADD0 RN13 MEM_MA_RAS_L MEM_MB_BANK1 MEM_MB_BANK0 MEM_MB_RAS_L RN15 C170 0.1u_10V_0402 VCC_DDR C180 0.1u_10V_0402 C203 0.1u_10V_0402 VCC_DDR C178 0.1u_10V_0402 C226 0.1u_10V_0402 VCC_DDR C224 0.1u_10V_0402 C199 0.1u_10V_0402 VCC_DDR C182 0.1u_10V_0402 C208 0.1u_10V_0402 VCC_DDR C216 0.1u_10V_0402 C218 0.1u_10V_0402 VCC_DDR C195 0.1u_10V_0402 C188 0.1u_10V_0402 VCC_DDR C261 0.1u_10V_0402 C168 0.1u_10V_0402 VCC_DDR C228 0.1u_10V_0402 MEM_MB_ADD15 MEM_MB_ADD14 MEM_MA_ADD12 MEM_MA_ADD9 MEM_MA_ADD4 MEM_MB_ADD3 MEM_MB_ADD1 MEM_MA_ADD3 B MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L 5,7 MEM_MB_CAS_L 5,7 MEM_MB_WE_L 5,7 MEM_MB_RAS_L MEM_MB0_CS_L0 MEM_MB0_CS_L1 5,7 MEM_MB0_CS_L0 5,7 MEM_MB0_CS_L1 5,7 MEM_MB0_ODT0 MEM_MB0_ODT0 MEM_MA_CKE0 MEM_MA_BANK2 MEM_MB_CKE0 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MA_ADD7 MEM_MB_ADD4 MEM_MA0_CLK_L3 5,7 MEM_MA0_CLK_L0 RN5 RN10 8P4R-47_RN0402 8P4R-47_RN0402 MEM_MA_BANK1 MEM_MA_BANK0 MEM_MB_ADD0 MEM_MB_ADD10 MEM_MB_CAS_L MEM_MA_CAS_L MEM_MA0_CS_L1 MEM_MA_ADD13 RN14 RN17 C197 C1.5P/4 MEM_MB0_CLK_H2 5,7 MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 5,7 MEM_MB0_CLK_L2 C250 C1.5P/4 MEM_MB0_CLK_H1 5,7 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 add for DIMM(1218) C214 0.1u_10V_0402 VCC_DDR C186 0.1u_10V_0402 C235 0.1u_10V_0402 VCC_DDR C239 0.1u_10V_0402 C238 0.1u_10V_0402 VCC_DDR C190 0.1u_10V_0402 C181 0.1u_10V_0402 VCC_DDR C206 0.1u_10V_0402 C192 0.1u_10V_0402 VCC_DDR C243 0.1u_10V_0402 C240 0.1u_10V_0402 VCC_DDR C201 0.1u_10V_0402 C252 0.1u_10V_0402 VCC_DDR C236 0.1u_10V_0402 C184 0.1u_10V_0402 VCC_DDR C213 0.1u_10V_0402 MEM_MB0_CLK_L3 5,7 MEM_MB0_CLK_L0 CN3 MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD11 MEM_MB_BANK2 MEM_MB_ADD9 MEM_MB_ADD12 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD0 MEM_MB_BANK1 MEM_MB_ADD10 MEM_MB_BANK0 MEM_MB_RAS_L MEM_MB_WE_L MEM_MB_CAS_L MEM_MB_ADD13 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_ADD10 MEM_MA_ADD0 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD13 MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L MEM_MA_ADD12 MEM_MA_ADD14 MEM_MA_BANK2 MEM_MA_ADD15 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD11 MEM_MA_ADD9 A CN6 C196 C1.5P/4 VCC_DDR 8P4C-22P50N3 8P4C-22P50N3 8P4C-22P50N3 8P4C-22P50N3 8P4C-22P50N3 8P4C-22P50N3 CN57 CN11 CN13 7 CN9 CN7 CN10 CN87 CN12 CN4 C137 C1.5P/4 MEM_MB0_CLK_H3 5,7 MEM_MB0_CLK_H0 7 C136 C1.5P/4 C VTT_DDR RN7 RN11 D MEM_MA0_CLK_H3 5,7 MEM_MA0_CLK_H0 MEM_MB_CKE0 5,7 MEM_MB_CKE0 MEM_MA0_CLK_L1 5,7 MEM_MA0_CLK_L1 5,7 MEM_MB0_CLK_L1 7 C249 C1.5P/4 MEM_MA0_CLK_H1 5,7 MEM_MA0_CLK_H1 MEM_MB_BANK[2 0] MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0 MEM_MA0_CLK_L2 5,7 MEM_MA0_CLK_L2 MEM_MB_ADD[15 0] MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0 MEM_MA0_CLK_H2 5,7 MEM_MA0_CLK_H2 8P4R-47_RN0402 8P4R-47_RN0402 MEM_MA_CKE0 8P4R-47_RN0402 8P4R-47_RN0402 5,7 MEM_MB_ADD[15 0] B 8P4C-22P50N3 8P4C-22P50N3 8P4C-22P50N3 8P4C-22P50N3 88P4C-22P50N3 A Micro Star Restricted Secret Title Rev DDR Terminatior Document Number MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A MS-9826 Last Revision Date: Wednesday, February 20, 2008 Sheet 34 of HT_CADIN_H[15 0] HT_CADIN_H[15 0] HT_CADIN_L[15 0] HT_CADIN_L[15 0] HT_CADOUT_H[15 0] HT_CADOUT_H[15 0] HT_CADOUT_L[15 0] HT_CADOUT_L[15 0] U7A R19 R18 R21 R22 U22 U21 U18 U19 W19 W20 AC21 AB22 AB20 AA20 AA19 Y19 HT_RXCAD15P HT_RXCAD15N HT_RXCAD14P HT_RXCAD14N HT_RXCAD13P HT_RXCAD13N HT_RXCAD12P HT_RXCAD12N HT_RXCAD11P HT_RXCAD11N HT_RXCAD10P HT_RXCAD10N HT_RXCAD9P HT_RXCAD9N HT_RXCAD8P HT_RXCAD8N HT_CADOUT_H7 HT_CADOUT_L7 HT_CADOUT_H6 HT_CADOUT_L6 HT_CADOUT_H5 HT_CADOUT_L5 HT_CADOUT_H4 HT_CADOUT_L4 HT_CADOUT_H3 HT_CADOUT_L3 HT_CADOUT_H2 HT_CADOUT_L2 HT_CADOUT_H1 HT_CADOUT_L1 HT_CADOUT_H0 HT_CADOUT_L0 T24 R25 U25 U24 V23 U23 V24 V25 AA25 AA24 AB23 AA23 AB24 AB25 AC24 AC25 HT_RXCAD7P HT_RXCAD7N HT_RXCAD6P HT_RXCAD6N HT_RXCAD5P HT_RXCAD5N HT_RXCAD4P HT_RXCAD4N HT_RXCAD3P HT_RXCAD3N HT_RXCAD2P HT_RXCAD2N HT_RXCAD1P HT_RXCAD1N HT_RXCAD0P HT_RXCAD0N HT_CLKOUT_H1 HT_CLKOUT_L1 W21 W22 HT_RXCLK1P HT_RXCLK1N HT_CLKOUT_H0 HT_CLKOUT_L0 Y24 W25 HT_RXCLK0P HT_RXCLK0N HT_CTLOUT_H0 HT_CTLOUT_L0 P24 P25 HT_RXCTLP HT_RXCTLN D C VDDHT_PKG R63 R73 49.9/4 HT_RXCALN A24 49.9/4 HT_RXCALP C24 PART OF HYPER TRANSPORT CPU I/F HT_CADOUT_H15 HT_CADOUT_L15 HT_CADOUT_H14 HT_CADOUT_L14 HT_CADOUT_H13 HT_CADOUT_L13 HT_CADOUT_H12 HT_CADOUT_L12 HT_CADOUT_H11 HT_CADOUT_L11 HT_CADOUT_H10 HT_CADOUT_L10 HT_CADOUT_H9 HT_CADOUT_L9 HT_CADOUT_H8 HT_CADOUT_L8 HT_RXCALP HT_RXCALN HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N P21 P22 P18 P19 M22 M21 M18 M19 L18 L19 G22 G21 J20 J21 F21 F22 HT_CADIN_H15 HT_CADIN_L15 HT_CADIN_H14 HT_CADIN_L14 HT_CADIN_H13 HT_CADIN_L13 HT_CADIN_H12 HT_CADIN_L12 HT_CADIN_H11 HT_CADIN_L11 HT_CADIN_H10 HT_CADIN_L10 HT_CADIN_H9 HT_CADIN_L9 HT_CADIN_H8 HT_CADIN_L8 HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N N24 N25 L25 M24 K25 K24 J23 K23 G25 H24 F25 F24 E23 F23 E24 E25 HT_CADIN_H7 HT_CADIN_L7 HT_CADIN_H6 HT_CADIN_L6 HT_CADIN_H5 HT_CADIN_L5 HT_CADIN_H4 HT_CADIN_L4 HT_CADIN_H3 HT_CADIN_L3 HT_CADIN_H2 HT_CADIN_L2 HT_CADIN_H1 HT_CADIN_L1 HT_CADIN_H0 HT_CADIN_L0 HT_TXCLK1P HT_TXCLK1N L21 L22 HT_CLKIN_H1 HT_CLKIN_L1 HT_TXCLK0P HT_TXCLK0N J24 J25 HT_CLKIN_H0 HT_CLKIN_L0 HT_TXCTLP HT_TXCTLN N23 P23 HT_TXCALP HT_TXCALN C25 D24 D C HT_CTLIN_H0 HT_CTLIN_L0 HT_TXCALP HT_TXCALN R74 4 100/4/1 ATI-216TQA6AVA12FG-A12-RH U7B 13 13 13 13 A_RX2P A_RX2N A_RX3P A_RX3N A_RX3P A_RX3N Y4 Y5 SB_RX2P SB_RX2N W4 W5 SB_RX3P SB_RX3N PART OF GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N J1 H2 K2 K1 K3 L3 L1 L2 N2 N1 P2 P1 P3 R3 R1 R2 AA1 AA2 A_TX2P_C A_TX2N_C C135 C146 0.1u/16V/4 0.1u/16V/4 SB_TX3P SB_TX3N Y2 Y3 A_TX3P_C A_TX3N_C C130 C132 0.1u/16V/4 0.1u/16V/4 SB_TX2P SB_TX2N GPP_RX2P GPP_RX2N GPP_TX2P GPP_TX2N U2 U1 R4 R5 GPP_RX3P GPP_RX3N GPP_TX3P GPP_TX3N V2 V1 GPP_RX0P GPP_RX0N GPP_TX0P GPP_TX0N V3 W3 GPP_TX0P_C GPP_TX0N_C C120 C122 0.1u/16V/4 0.1u/16V/4 GPP_TX1P GPP_TX1N W1 W2 GPP_TX1P_C GPP_TX1N_C C123 C129 0.1u/16V/4 0.1u/16V/4 AC1 AC2 AB1 AB2 A_TX0P_C A_TX0N_C A_TX1P_C A_TX1N_C C148 C150 C147 C149 0.1u/16V/4 0.1u/16V/4 0.1u/16V/4 0.1u/16V/4 GPP_RX0P GPP_RX0N R7 R8 19 19 GPP_RX1P GPP_RX1N GPP_RX1P GPP_RX1N U4 U5 13 13 13 13 A_RX0P A_RX0N A_RX1P A_RX1N PCIE I/F GPP GPP_RX1P GPP_RX1N AB7 AB6 V9 W9 SB_RX0P SB_RX0N SB_RX1P SB_RX1N AC4 AD4 NC1 NC2 PCIE I/F SB SB_TX0P SB_TX0N SB_TX1P SB_TX1N PCE_CALRP PCE_CALRN AE4 R97 AE3 R96 B REMOVE HDMI P4 P5 GPP_RX0P GPP_RX0N 18 18 A A_RX2P A_RX2N GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N PCIE I/F GFX B G5 G4 J8 J7 J4 J5 L8 L7 L4 L5 M8 M7 M4 M5 P8 P7 * * A_TX2P A_TX2N 13 13 A_TX3P A_TX3N 13 13 GPP_TX0P GPP_TX0N 18 18 GPP_TX1P GPP_TX1N 19 19 A_TX0P A_TX0N A_TX1P A_TX1N 13 13 13 13 A 562R1%0402 VDDA12_PKG2 2KR1%0402 Micro Star Restricted Secret Title ATI-216TQA6AVA12FG-A12-RH Rev RS690T-HT LINK/PCIE/HDMI Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A Last Revision Date: Wednesday, February 20, 2008 Sheet of 34 VCC3 CP1 R69 4.7K/4 R64 4.7K/4 R65 4.7K/4 DDC_DATA AVSSQ NOTE: CONNECT TO GND CLOSE TO FIRST CAP VCC3 I2C_CLK 100mA I2C_DATA L20 AVDD C362 2.2u_6V_0603 300L600m D +1.8V_S0 D CP2 AVDDDI U7C C82 B AVSSQ C89 2.2u_6V_0603 X_10u_6V_0603 C516 C515C514 X_10P/4X_10P/4 X_10P/4 REMOVE TV_OUT add for EMI (0221) 23 23 23 23 23 +1.8V_S0 R G B VSYNC# HSYNC# L5 300L300m L21 300L300m 23 2.2u_6V_0603 4.7u_6V_0603 PLLVDD C84 HTPVDD VDDPLL VCC3 50mA R100 4.7K/4 C366 E7 F7 F9 G9 C371 1u_6.3V_0402 4.7u_6V_0603 R103 10K_0402 20 PCI_RST1# 25 NB_PWRGD LDT_STOP_NB# 4,13 LDT_STOP# 13 ALLOW_LDTSTOP 70mA VDDA_1V2 10K/4 12 HTREFCLK 14 PLLVDD12 L6 C86 2.2u_6V_0603 B R281 R282 VCC3 SUS_STAT# R72 4.7K_0402 0/4 SB_CLKP SB_CLKN BMREQ# LVDS I2C_CLK I2C_DATA add pull low for hot plug (1212) BMREQ# I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N C14 B3 C3 A3 TMDS_HPD DDC_DATA TESTMODE STRP_DATA STRP_DATA R286 1KR0402 R68 4.7K/4 TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N A15 B16 C17 C18 B17 A17 A18 B18 TXCLK_LP TXCLK_LN TXCLK_UP TXCLK_UN E15 D15 H15 G15 LPVDD LPVSS D14 E14 LVDDR18D LVDDR18D LVDDR33 LVDDR33 A12 B12 C12 C13 LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR A16 A14 D12 C19 C15 C16 LVSSR LVSSR F14 F15 REMOVE LVDS +1.8V_S0 VCC3 L25 LPVDD 300L300m LVDDR18D L22 +1.8V_S0 L23 LVDDR33 C 300L300m 300L300m HDMI ,LVDS did not implement, power pin should be connected, LPVDD,LVDDR18D,LVDDR33 LVSSR,LPVSS SHOULD BE CONNECT TO GND BY ATI FAE Decoupling capacitors can remove (1214) pull lvssr to GND LVDS_DIGON LVDS_BLON LVDS_BLEN E12 G12 F12 B B2 A2 B4 AD5 AE5 HDMI_HPD B14 B15 B13 A13 H14 G14 D17 E17 MIS DFT_GPIO0 DFT_GPIO1 DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5 D6 D7 C8 C7 B8 A8 DFT_GPIO0 LOAD_ROM# DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5 TP33 TP2 TP32 TP4 TP3 R285 X_1KR0402 ATI-216TQA6AVA12FG-A12-RH RS690 only (NC for RS485) DFT_GPIO0 Memory side port not available DEFAULT TVCLKIN GFX_CLKP GFX_CLKN R67 X_2.2K_0402 I2C Master can load strap values from EEPROM if connected, or use default values if not connected HTTSTCLK HTREFCLK G1 G2 DDC_DATA PULL LOW C23 B23 12 SBLINKCLK 12 SBLINKCLK# HDMI Bypass the loading of EEPROM straps and use Hardware default values SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP OSCIN PLLVDD12 STRP_DATA PULL HIGH (internally pulled high) VDD_PLL VDD_PLL VSS_PLL VSS_PLL F2 E1 R66 10K_0402 A HTPVDD HTPVSS B11 A11 13 RS485/RS690 PLLVDD18 PLLVSS C10 C11 C5 B5 C2 PLLVDD12 VCC3 DFT_GPIO1 DACSCL DACSDA 12 NBSRCCLK 12 NBSRCCLK# 12 NB_OSC_14M 300L300m RSET VDDA_1V2 L24 300L600m +1.8V_S0 Q17 N-MMBT3904_NL_SOT23 RED GREEN BLUE DACVSYNC DACHSYNC B24 B25 C361 1u_6.3V_0402 E19 F19 G19 C6 A5 A10 B10 C85 C360 2.2u_6V_0603 C Y COMP B6 A6 DAC_SCL DAC_SDAT CRT 23 AVDDQ AVSSQ C21 C20 D19 715R RSET B21 R62 150mA C R G B A21 A22 TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N AVDDQ G PART OF 1 300L300m R AVDD AVDD AVSSN AVSSN AVDDDI AVSSDI CRT/TVOUT L4 PLL PWR +1.8V_S0 B22 C22 G17 H17 A20 B20 CLOCKs PM C83 2.2u_6V_0603 Memory side port available DFT_GPIO[4:2] DFT_GPIO5 These pin straps are used to configure PCI-E GPP mode: 111: register defined (register default to Config E) 110: 4-0-0-0-0 Config A 101: 4-4 Config B 100: 4-2-2 Config C 011: 4-2-1-1 Config D 010: 4-1-1-1-1 Config E others: register defined (register default to Config E) DEFAULT Enable debug bus via the memory IO pads, if available in the package A use default values DEFAULT Micro Star Restricted Secret use the memory data bus to output the debug bus Title Rev RS690T-SYSTEM I/F Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw DEFAULT Last Revision Date: Monday, February 25, 2008 Sheet of 10 34 0A A B C D E SATA CONNECTOR PLACE SATA AC COUPLING CAPS CLOSE TO SB600 SATA1 AH20 AJ20 SATA_RX0SATA_RX0+ AH18 AJ18 SATA_TX1+ SATA_TX1- SATA_RX1SATA_RX1+ AH17 AJ17 SATA_RX1SATA_RX1+ AH13 AH14 SATA_TX2+ SATA_TX2- AH16 AJ16 SATA_RX2SATA_RX2+ AJ11 AH11 SATA_TX3+ SATA_TX3- AH12 AJ13 SATA_RX3SATA_RX3+ AF12 SATA_CAL SATA_X1 AD16 SATA_X1 SATA_X2 AD18 SATA_X2 SATA_ACT# AC12 SATA_ACT#/GPIO67 AD14 AJ10 PLLVDD_SATA_1 PLLVDD_SATA_2 XTLVDD_SATA AC16 XTLVDD_SATA AVDD_SATA AE14 AE16 AE18 AE19 AF19 AF21 AG22 AG23 AH22 AH23 AJ12 AJ14 AJ19 AJ22 AJ23 AVDD_SATA_1 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_4 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 AVDD_SATA_8 AVDD_SATA_9 AVDD_SATA_10 AVDD_SATA_11 AVDD_SATA_12 AVDD_SATA_13 AVDD_SATA_14 AVDD_SATA_15 AB14 AB16 AB18 AC14 AC18 AC19 AD12 AD19 AD21 AE12 AE21 AF11 AF14 AF16 AF18 AG11 AG12 AG13 AG14 AG16 AG17 AG18 AG19 AG20 AG21 AH10 AH19 AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20 AVSS_SATA_21 AVSS_SATA_22 AVSS_SATA_23 AVSS_SATA_24 AVSS_SATA_25 AVSS_SATA_26 AVSS_SATA_27 103P/16V/4 103P/16V/4 SATA_RX1-_C SATA_RX1+_C SATA_H C237 SATA_X1 R318 1K/4 1% SATA_CAL 10p_50V_0402 R135 10MR0402 Y2 10p_50V_0402 SATA_X2 C233 25MHZ20P_S-2 24 SATA_ACT# PLLVDD_SATA AVDD_SATA+PLLVDD_SATA MAX =300mA VCC_1V2 PLLVDD_SATA L33 220R_200mA SATA C482 1u/6.3V/4 VCC3 XTLVDD_SATA 220R_200mA L32 C474 1u/6.3V/4 VCC_1V2 AVDD_SATA 220L3A L34 C481 22u_6V_0805 C478 C476 0.1u_10V_0402 1u_6.3V_0402 C477 C480 0.1u_10V_0402 1u_6.3V_0402 IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3# AB29 AA28 AA29 AB27 Y28 AB28 AC27 AC29 AC28 W28 W27 IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30 AD28 AD26 AE29 AF27 AG29 AH28 AJ28 AJ27 AH27 AG27 AG28 AF28 AF29 AE28 AD25 AD29 Part of SATA_TX1+ SATA_TX1- 103P/16V/4 103P/16V/4 C267 C266 SATA_RX1-_C SATA_RX1+_C SATA_RX0SATA_RX0+ SB600 SB 23x23mm ATA 66/100 SATA_TX1+_C SATA_TX1-_C SATA_TX0+ SATA_TX0- PD_IORDY PD_SIRQ PDA_R0 PDA_R1 PDA_R2 PD_DACK# PD_DREQ PD_IOR# PD_IOW# PD_CS#1 PD_CS#3 IDEB1 20 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 HD_RST# 24 PD_LED HD_RST# R274 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 33/4 HDRST#P 11 13 15 17 19 PD_DREQ 21 PD_IOW# 23 PD_IOR# 25 PD_IORDY 27 PD_DACK# 29 PD_SIRQ 31 PDA_R1 33 PDA_R0 35 PD_CS#1 37 PD_LED 39 R275 4.7K/4 10 12 14 16 18 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 22 24 26 28 30 32 34 36 38 40 PD_DET PDA_R2 PD_CS#3 PD_DET 14 R276 100K_0402 BH2X20[20]_BLUE-RH-2 C343 SPI ROM SATA_H 103P/16V/4 103P/16V/4 AH21 AJ21 SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS#/GPIO32 J3 J6 G3 G2 G6 LAN_RST#/GPIO13 ROM_RST#/GPIO14 C23 G5 FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49 M4 T3 V4 FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52 N3 P2 W4 TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64 P5 P7 P8 T8 T7 VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60 V5 L7 M8 V6 M6 P4 M7 V7 HW MONITOR GND HT+ HTGND HRHR+ GND 103P/16V/4 103P/16V/4 SATA_TX0+ SATA_TX0- SERIAL ATA SATA2 SATA_TX0+_C SATA_TX0-_C C232 C231 SATA_RX0-_C SATA_RX0+_C C230 C229 SATA_TX1+_C SATA_TX1-_C C269 C268 SERIAL ATA POWER IDE U10B GND HT+ HTGND HRHR+ GND SPI_DATAIN SPI_DATAOUT SPI_CLK SPI_HOLD#_SB SPI_CS# LAN_RST#_SB TP39 TP15 R308 10K/4 VCC3 TALERT# 20 GPIO 50~63 BOIS need to programming to GPIO output VCC3 AVDD_HWM 220R_200mA AVDD N1 AVSS M1 4700p_25V_0402 VCC3 C457 2.2U/6.3V/6 L31 C450 0.1u/10V HWM_AGND CP8 NS_VIA CONNECTS HWM_AGND TO GND ATI-SB600-218S6ECLA13FG-A13-RH SHOULD BE 8Mb SPI FLASH MEMORY 3VDUAL SPI DEBUG PORT Place close to SPI ROM 3VDUAL 3VDUAL 1 C98 R48 X_1K/4 R47 _10K/4 SPI_CS# SPI_DATAIN SST SPI ROM 0.1u/10V/4 U6 CE# VDD SO HOLD# WP# SCK VSS SI B JSPI1 SPI_DATAIN SPI_CS# SPI_HOLD# SPI_CLK SPI_DATAOUT SST25VF080B-50-4C-S2AF-RH A R71 _10K/4 SPI_HOLD# Micro Star Restricted Secret SPI_DATAOUT SPI_CLK Title H2X5(10)_black-RH MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Part Number : N31-2051451-H06 C Rev SB600-SATA/IDE/SPI Document Number D E Last Revision Date: Friday, February 22, 2008 Sheet of 15 34 0A REQUIRED STRAPS VCC3 U10C D C463 C479 1u_6.3V_0402 1u_6.3V_0402 C473 C412 1u_6.3V_0402 1u_6.3V_0402 REMOVE ONE CHOKE (1212) total VCC_SB 1.1A VCC_1V2 220L3A CORE L30 430mA SB_VDD 1u_6.3V_0402 M13 M17 N12 N15 N18 R13 R17 U12 U15 U18 V13 V17 1u_6.3V_0402 C455 C454 C464 22u_6V_0805 C 3VDUAL C449 1u_6.3V_0402 C462 1u_6.3V_0402 CP5 C415 22u_6V_0805 C397 1.0u/16V/4 C448 1u_6.3V_0402 USB_PHY CP7 70mA C435 77mA C441 C442 0.1u/10V/4 USB_PHY 0.1u/10V/4 C404 22u_6V_0805 C414 C399 C413 1u/6.3V/4 1u/6.3V/4 1u/6.3V/4 C469 CPU_PWR R320 1KR0402 V5_VREF VCC3 total VCC3_S0 VCC3 C472 130mA D8 S-RB521S-30_SOD523 L10 300L300m G4 H1 H2 H3 S5_1.2V_1 S5_1.2V_2 S5_1.2V_3 S5_1.2V_4 L11 300L300m C164 2.2u_6V_0603 TO D01-RB52100-R06 USB_PHY_1.2V_1 USB_PHY_1.2V_2 USB_PHY_1.2V_3 USB_PHY_1.2V_4 USB_PHY_1.2V_5 AA27 CPU_PWR AE11 V5_VREF AVDDCK33V A24 AVDDCK_3.3V AVDDCK12V A22 AVDDCK_1.2V B22 AVSSCK V29 V28 V27 V26 V25 V24 V23 V22 U27 T29 T28 T27 T24 T21 P27 PCIE_VSS_42 PCIE_VSS_41 PCIE_VSS_40 PCIE_VSS_39 PCIE_VSS_38 PCIE_VSS_37 PCIE_VSS_36 PCIE_VSS_35 PCIE_VSS_34 PCIE_VSS_33 PCIE_VSS_32 PCIE_VSS_31 PCIE_VSS_30 PCIE_VSS_29 PCIE_VSS_28 VCC_1V2 1u/6.3V/4 CHANGE D01-BAT54A9-P03 S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 0.1u/10V/4 +1.8V_S0 B VCC5 Part of VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 A2 A7 F1 J5 J7 K1 A18 A19 B19 B20 B21 0.1u/10V/4 CP6 SB600 SB 23x23mmVSS_1 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 C166 2.2u_6V_0603 POWER A25 A28 C29 D24 L9 L21 M5 P3 P9 T5 V9 W2 W6 W21 W29 AA12 AA16 AA19 AC4 AC23 AD27 AE1 AE9 AE23 AH29 AJ2 AJ6 AJ26 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 PCIE_VSS_1 PCIE_VSS_2 PCIE_VSS_3 PCIE_VSS_4 PCIE_VSS_5 PCIE_VSS_6 PCIE_VSS_7 PCIE_VSS_8 PCIE_VSS_9 PCIE_VSS_10 PCIE_VSS_11 PCIE_VSS_12 PCIE_VSS_13 PCIE_VSS_14 PCIE_VSS_15 PCIE_VSS_16 PCIE_VSS_17 PCIE_VSS_18 PCIE_VSS_19 PCIE_VSS_20 PCIE_VSS_21 PCIE_VSS_22 PCIE_VSS_23 PCIE_VSS_24 PCIE_VSS_25 PCIE_VSS_26 PCIE_VSS_27 A1 A20 A21 A29 B1 B7 B25 C21 C22 C24 D6 E24 F2 F23 G1 J1 J8 L6 L8 M9 M12 M15 M18 N13 N17 P1 P6 P21 R12 R15 R18 T6 T9 U13 U17 V3 V8 V12 V15 V18 V21 W1 W9 Y29 AA11 AA14 AA18 AC6 AC24 AD9 AD23 AE3 AE27 AG6 AJ1 AJ25 AJ29 VCC3 3VDUAL R304 X_2.2K/4 VCC3 R292 X_10K/4 VCC3 R310 X_10K/4 VCC3 R123 10K/4 VCC3 R306 10K/4 R119 X_10K/4 R305 X_10K/4 R116 10K/4 D 14 AC_SDATA_OUT 13 RTC_CLK 13 PCI_CLK4 13,17 PCI_CLK6 13,17 PCI_CLK0 13,20 PCI_CLK1 R311 10K/4 PULL HIGH AC_SDOUT RTC_CLK PCI_CLK4 PCI_CLK6 PCI_CLK0 USE DEBUG STRAPS INTERNAL RTC USE INT PLL48 CPU IF=K8 ROM TYPE: DEFAULT DEFAULT PULL LOW IGNORE DEBUG STRAPS EXTERNAL RTC DEFAULT PCI_CLK1 C H, H = PCI ROM H, L = SPI ROM USE EXT 48MHZ CPU IF=P4 DEFAULT L, H = LPC ROM L, L = FWH ROM DEFAULT D27 D28 D29 F26 G23 G24 G25 H27 J23 J26 J28 K27 L22 L23 L24 L27 L28 M21 M24 M27 N27 N28 P22 P23 P24 P25 P26 B SB600 IXP600 A11, LF A A Micro Star Restricted Secret Title Rev SB600-POWER & DECOUPLING Document Number MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A MS-9826 Last Revision Date: Wednesday, February 20, 2008 Sheet 16 34 of 13 AD[31 0] AD[31 0] PCI_CBE#[3 0] 13 PCI_CBE#[3 0] PCI SLOT (PCI VER: 2.2 COMPLY) PCI1 R56 D 4.7K/4 TCK VCC5 13 13 13 13 13 PCI_REQ#2 PCI_GNT#1 PCI_GNT#2 PCI_INTF# PCI_INTH# VCC3 13 PCI_CLK2 13,16 PCI_CLK0 13 PCI_REQ#0 AD31 AD29 AD27 AD25 PCI_CBE#3 AD23 AD21 AD19 AD17 PCI_CBE#2 C 13 PCI_IRDY# PCI_IRDY# PCI_DEVSEL# 13 PCI_DEVSEL# 13 13 PCI_LOCK# PCI_PERR# 13 PCI_SERR# PCI_LOCK# PCI_PERR# PCI_SERR# PCI_CBE#1 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 ACK64# B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT#1 RESERVED PRSNT#2 GND GND RESERVED GND CLK GND REQ# +5V(I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE#3 AD23 GND AD21 AD19 +3.3V AD17 C/BE#2 GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#1 AD14 GND AD12 AD10 GND B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V(I/O) ACK64# +5V +5V B +12V TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V(I/O) RESERVED GND GND RESERVED RST# +5V(I/O) GNT# GND RESERVED AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3 AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 C/BE#0 +3.3V AD6 AD4 GND AD2 AD0 +5V(I/O) REQ64# +5V +5V A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 +12V TRST# R57 4.7K/4 R70 R60 4.7K/4 4.7K/4 D VCC5 C513 _0.1u/25V/4 PCI_INTE# PCI_INTG# 13 13 PCI_CLK6 13,16 PCI_REQ#1 13 REMOVE MINI_PCIE & TPM VCC5 VCC3 3VDUAL PCIRST# 13 PCI_GNT#0 13 PCI_PME# AD30 add C513 IN 1.0 (0219) PCI_PME# 14 AD28 AD26 AD24 ID1 R101 100/4/1 AD18 AD22 AD20 AD18 AD16 C PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_FRAME# 13 PCI_TRDY# 13 PCI_STOP# 13 SDONE R115 SBO# R117 PCI_PAR AD15 PCI_PAR 0R0402 0R0402 SCLK1 SDATA1 14 14 13 AD13 AD11 AD9 PCI_CBE#0 AD6 AD4 AD2 AD0 REQ64# B SLOT-PCI120_white-RH IDSEL = AD18 MASTER = PCI_REQ#0 PCI_GNT#0 PCI PULL-UP / DOWN RESISTORS REQ64# ACK64# R134 R136 8.2KR0402 8.2KR0402 VCC3 PCI SLOT DECOUPLING CAPACITORS VCC5 A VCC3 3VDUAL C111 0.1u/10V/4 C7 0.1u/10V/4 C297 0.1u/10V/4 C131 0.1u/10V/4 C273 X_0.1u/10V/4 C193 0.1u/10V/4 C155 0.1u/10V/4 C158 0.1u/10V/4 C225 0.1u/10V/4 A C119 0.1u/10V/4 C74 _0.1u/25V/4 Micro Star Restricted Secret Title PCI/Mini PCIE/TPM MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Rev 0A Document Number Last Revision Date: Monday, February 25, 2008 Sheet of 17 34 AVDD12 3VDUAL U2 AVDD12 3VDUAL C75 0.1U10V/4 C110 0.1U10V/4 C93 0.1U10V/4 C96 0.1U10V/4 C77 0.1U10V/4 R61 4.7K/4 A0 A1 A2 GND VCC WP SCL SDA 3VDUAL Q12 P-BCP69_SOT223 VPD_CLK VPD_DATA AVDD18 (150mA) AT24C08AN-10SC C64 C69 X_0.01U25V/4 4.7u_10V_0805 C60 X_0.1U16V/4 C59 X_0.1U16V/4 C70 0.1U10V/4 VPD_DATA D R53 D CTRL18 4.7K/4 3VDUAL AVDD12 VCC3 VPD_CLK 52 53 MDIN[2] 27 REFCLKP MDIP[2] 26 GPPCLK0# 56 REFCLKN HSDACN 25 57 AVDDL HSDACP 24 58 VDD 59 LED_ACTn 60 LED_10/100n 61 VDDO_TTL 62 LED_1000n 63 LED_LINKn 64 VDD_25 X1 25MHZ20P_S-2 14,19 PCIE_WAKE_UP# 19,20 PCI_E_RST# C47 22P50V/4 23 AVDDL 22 MDIN[1] 21 MDIP[1] 20 AVDDL 19 MDIN[0] 18 MDIP[0] 17 C90 0.1U C42 0.1U C66 0.1U10V/4 C68 0.1U10V/4 4.7u_10V_0805 R36 4.7K/4 CTRL12 TR1_D3TR1_D3+ TR1_D2TR1_D2+ AVDD18 C67 0.1U10V/4 C 3VDUAL TR1_D1TR1_D1+ TR1_D0TR1_D0+ C107 0.1U10V/4 C97 0.1U10V/4 C78 0.1U10V/4 C108 0.1U10V/4 C87 0.1U10V/4 XTALI RSET 16 15 C40 22u_6V_0805 88E8053 Ver:B0 R12 AVDD12 C48 22P50V/4 C18 25MCLK X_1M/4 AVDD C72 0.1U AVDD18 XTALO XTALO_LAN XTALO_LAN 14 VAUX_AVLBL VDD 13 12 11 SWITCH_VCC LOM_DISABLEn 10 VDDO_TTL_MAIN SWITCH_VAUX VDD GND WAKEn GND 65 EPAD PERSTn LED_LINK1000_1 88E8056 LED_LINK100_1 3VDUAL (290mA) 33 RX_P 55 LED_ACT_1 R26 34 36 54 GPPCLK0 C 25MCLK 35 37 39 38 40 41 43 42 44 45 46 28 CTRL25 GPPCLK0# 29 AVDDL CTRL12 12 TSTPT RX_N GPPCLK0 AVDDL GPP_TX0P 31 30 VDD 12 32 MDIP[3] VDDO_TTL GPP_TX0N AVDDL MDIN[3] AVDD12 C23 X_4.7U10V/4 AVDDL VDD TX_N 51 SPI_DO 50 SPI_DI GPP_RX0N_C SPI_CS 0.1U16V/4 SPI_CLLK C106 VPD_CLK GPP_RX0N VDD VDDO_TTL TX_P VPD_DATA 49 SMCLK GPP_RX0P_C SMDATA 0.1U16V/4 VDD C99 VDDO_TTL GPP_RX0P TESTMODE 48 VDD 47 U5 Close Marvell LAN 4.7K/4 3VDUAL Q9 P-BCP69_SOT223 VMAIN_AVAL CONNECT RX from Yukon to TX on connector, vice versa R54 220R0402 3VDUAL LAN_USB1B 3VDUAL 3VDUAL R51 4.87K/4/1 B R7 LED_LINK_1 19 220R0402 LED_ACT_1 20 YELLOW GREEN ORANGE LED_LINK1000_1 21 B LED_LINK100_1 22 R11 R58 10K/4 3VDUAL 220R0402 16 CTRL12 3VDUAL CTRL18 10 11 12 13 14 15 16 17 18 CONN-RJ45_USBX2_LEDX2_TX-3 AVDD18 R8 10/100-Lan N58-22F0221-S42 N58-22F0061-S42 N58-22F0061-F02 Link Active 1000 100 10 19 20 Green Blinking Orange Green None Link Active 100 10 Yellow Blinking Green None 20 Orange 22 Green 22 LED_LINK_1 C19 LED_ACT_1 C356 C1000P16X0402 LED_LINK1000_1 21 22 21 C16 LED_LINK100_1 Yellow A 21 20 0R TR1_D3+ TR1_D2+ TR1_D1+ TR1_D0+ MSI footprint 19 19 Green TR1_D3TR1_D2TR1_D1TR1_D0- 0.1U10V_0402 Giga-Lan 14 15 16 10 17 11 18 12 Green 13 TR1_D0+ TR1_D0- R46 R45 49.9R/4/1 49.9R/4/1 C54 0.1U10V/4 TR1_D1+ TR1_D1- R44 R43 49.9R/4/1 49.9R/4/1 C53 0.1U10V/4 TR1_D2+ TR1_D2- R40 R39 49.9R/4/1 49.9R/4/1 C50 0.1U10V/4 TR1_D3+ TR1_D3- R42 R41 49.9R/4/1 49.9R/4/1 C51 C1000P16X0402 C22 C1000P16X0402 C21 C1000P16X0402 A Micro Star Restricted Secret 0.1U10V/4 Title Rev MARVELL 88E8056 Document Number 0A MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Wednesday, February 20, 2008 Sheet of 18 34 AVDD12_LAN2 3VDUAL U3 AVDD12_LAN2 3VDUAL C73 0.1U10V/4 C105 0.1U10V/4 C91 0.1U10V/4 C88 0.1U10V/4 C76 0.1U10V/4 R59 4.7K/4 A0 A1 A2 GND VCC WP SCL SDA 3VDUAL Q7 P-BCP69_SOT223 VPD_CLK_2 VPD_DATA_2 AVDD18_LAN2 (150mA) AT24C08AN-10SC C39 C62 0.1U10V/4 4.7u_10V_0805 C41 0.1U10V/4 C63 0.1U10V/4 C58 0.1U10V/4 VPD_DATA_2 D D R10 4.7K/4 CTRL18_2 3VDUAL AVDD12_LAN2 VCC3 VPD_CLK_2 R52 TSTPT 29 RX_N AVDDL 28 54 RX_P MDIN[2] 27 55 REFCLKP MDIP[2] 26 GPPCLK1# 56 REFCLKN HSDACN 25 57 AVDDL HSDACP 24 58 VDD AVDD 23 59 LED_ACTn AVDDL 22 60 LED_10/100n 61 VDDO_TTL 62 LED_1000n 63 LED_LINKn 64 VDD_25 21 MDIP[1] 20 AVDDL 19 MDIN[0] 18 MDIP[0] 17 C43 C81 0.1U C71 0.1U C34 X_0.1U16V/4 C13 X_0.1U16V/4 4.7u_10V_0805 R5 4.7K/4 CTRL12_2 TR2_D3TR2_D3+ TR2_D2TR2_D2+ AVDD18_LAN2 C20 X_0.1U16V/4 C 3VDUAL TR2_D1TR2_D1+ TR2_D0TR2_D0+ C102 0.1U10V/4 C92 0.1U10V/4 C79 0.1U10V/4 C94 0.1U10V/4 C80 0.1U10V/4 C101 RSET XTALI 22u_6V_0805 16 15 VDD MDIN[1] C55 X_0.01U25V/4 AVDD18_LAN2 XTALO 14 13 VAUX_AVLBL 12 11 SWITCH_VCC LOM_DISABLEn 10 VDDO_TTL_MAIN SWITCH_VAUX WAKEn VDD GND GND PERSTn 65 EPAD CTRL25 LED_LINK1000_2 88E8056 LED_LINK100_2 3VDUAL LED_ACT_2 (290mA) C35 X_4.7U10V/8 34 AVDDL GPPCLK1 C AVDD12_LAN2 33 VDD SPI_DO 36 35 38 37 40 39 41 43 42 45 44 47 30 CTRL12 GPPCLK1# MDIP[3] 12 MDIN[3] 31 VDD GPPCLK1 32 VDDO_TTL GPP_TX1P AVDDL TX_P 12 SPI_DI 53 GPP_TX1N SPI_CS 52 VPD_CLK AVDDL SPI_CLLK TX_N 51 Close Marvell LAN VDD 50 VDDO_TTL 49 GPP_RX1N_C VPD_DATA GPP_RX1P_C 0.1U10V/4 SMCLK 0.1U10V/4 C104 SMDATA C103 GPP_RX1N VDD GPP_RX1P VDDO_TTL TESTMODE VDD 48 U4 46 Q8 P-BCP69_SOT223 VMAIN_AVAL CONNECT RX from Yukon to TX on connector, vice versa 4.7K/4 3VDUAL 88E8053 XTALO_LAN_2 Ver:B0 X_1M/4 X2 25MHZ20P_S-2 14,18 PCIE_WAKE_UP# 18,20 PCI_E_RST# C56 22P50V/4 AVDD12_LAN2 C57 22P50V/4 B 25MCLK_2 R30 XTALO_LAN_2 25MCLK_2 R6 220R0402 3VDUAL LAN_USB2B 3VDUAL 3VDUAL R49 4.87K/4/1 R13 LED_LINK_2 19 220R0402 LED_ACT_2 20 YELLOW GREEN ORANGE 21 LED_LINK1000_2 22 LED_LINK100_2 B R9 R55 10K/4 3VDUAL 220R0402 16 CTRL12_2 3VDUAL CTRL18_2 10 11 12 13 14 15 16 17 18 CONN-RJ45_USBX2_LEDX2_TX-3 AVDD18_LAN2 R14 10/100-Lan N58-22F0061-S42 N58-22F0061-F02 Link Active 1000 100 10 19 20 A Green Blinking Orange Green None Orange 22 Green Yellow Blinking Green None 20 20 21 22 C44 LED_LINK_2 C29 C1000P16X0402 LED_ACT_2 C28 C1000P16X0402 C11 C1000P16X0402 C15 C1000P16X0402 LED_LINK1000_2 LED_LINK100_2 Yellow 21 22 TR2_D3+ TR2_D2+ TR2_D1+ TR2_D0+ MSI footprint 19 19 Green 21 Link Active 100 10 0R TR2_D3TR2_D2TR2_D1TR2_D0- 0.1U10V/4 Giga-Lan N58-22F0221-S42 14 15 16 10 17 11 12 Green A 18 13 TR2_D0+ TR2_D0- R29 R31 49.9R/4/1 49.9R/4/1 C61 0.1U10V/4 TR2_D1+ TR2_D1- R28 R27 49.9R/4/1 49.9R/4/1 C46 0.1U10V/4 TR2_D2+ TR2_D2- R35 R34 49.9R/4/1 49.9R/4/1 C52 0.1U10V/4 Title TR2_D3+ TR2_D3- R33 R32 49.9R/4/1 49.9R/4/1 C49 0.1U10V/4 Document Number Micro Star Restricted Secret Rev MARVELL 88E8056 0A MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Wednesday, February 20, 2008 Sheet of 19 34 LRESET# LCLK SERIRQ LDRQ# LFRAME# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 27 26 25 24 LAD0 LAD1 LAD2 LAD3 LPC_AD[3 0] D 21 CPU_FANOUT1 TMP_VREF AUX_TMP THERMDA_CPU THERMDA_CPU THERMDC_CPU RSTOUT1 RSTOUT0 AVCC3 THERMDC_CPU +12VIN +5VIN CPUVCORE X_10u/10V/8 21 CPU_FANPWM 21 CPUFANIN 21 AUXFANIN VBAT R230 CHASSIS RSTOUT2 VCC5_SB TP30 14 24 R219 4.7KR/2 SIO_PSON# 25 SIO_PSON# 14,25,26 SLP_S3# 12 SIO_48M 3VDUAL SIO_48M 118 76 19 89 90 91 92 61 74 VBAT C288 C0.1U16Y2 28 VCC3 WDTO# B C323 C0.1U16Y2 C289 C0.1U16Y2 24 C499 C302 C0.1U16Y2 C0.1U16Y2 RSTOUT4#/GP34 GP36 GP35 GP51/RSMRST# 88 69 87 75 GP61/DCDA# GP66/DSRA# SYSFANOUT GP63/SINA SYSFANIN GP65/RTSA#(HEFRAS) CPUFANOUT_PWM GP62/SOUTA(PENKBC) CPUFANIN GP67/CTSA# AUXFANIN GP64/DTRA#(PENROM) GP60/RIA# BEEP/SI CASEOPEN# GP41/DCDB# SCE#/GP22/PLED/WDTO# GP46/DSRB# GP43/IRRX/SINB RSTOUT3#/GP33/SDA GP45/RTSB# RSTOUT2#/GP32/SCL GP42/IRTX/SOUTB GP31 GP47/CTSB# GP30 GP44/DTRB# GP40/RIB# GP57/PSOUT# GP56/PSIN# GA20M GP37 KBRST GP53/PSON# GP26/KBDATA GP52/SUSB# GP27/KBCLK CLKIN GP24/MSDATA GP25/MSCLK 3VSB AUXFANIN1/SO VBAT SUSLED/GP55 VCC3 GP54/PWROK 56 50 53 51 54 49 52 57 VCC3 VSS1 VCC3 VSS2 WDTO#/GP50(EN_VRM10) PME# SST (FAN_SET)/PLED 20 55 86 117 VREF AUXTIN CPUTIN SYSTIN CPUDRSTOUT1 RSTOUT0# AVCC VIN3 VIN2 VIN1 VIN0 CPU_VCORE 67 68 64 72 73 18 PWRBTIN# PSIN# 42 41 40 39 38 37 36 35 31 32 33 34 43 44 45 46 47 101 102 103 104 105 93 94 95 96 97 98 99 100 116 113 115 112 111 2MR0402 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# SLIN# INIT# ERR# AFD# STB# VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CPUFANOUT1/GP20 CPUFANIN1/GP21 106 107 108 109 110 C509 X_C0.1U16Y2 C 10 11 13 14 15 16 17 121 122 123 124 125 126 127 128 120 119 reserve for 657XHG C508 DRVDEN0 SCK/GP23 INDEX# MOA# OVT#/HM_SMI# DSA# AUXFANOUT_PWM DIR# STEP# WRDATA# WE# TRACK0# WP# RDDATA# HEAD# DSKCHG# 12 48 77 114 PECISB Vtt PECI SIC SID WDTO# SUSLED THERMDC_CPU TALERT# 15 OVT# PROCHOT_L AUX_FANPWM 21 R260 X_0R0402 IS OD OUTPUT D VCC5 R250 330R VCC3 R224 HD_RST# 10 PCI_RST1# 18,19 PCI_E_RST# LPC_FRAME# C321 X_33p_50V_0402 R226 0R/2 RSMRST# RSMRST# 14 DCDA# DSRA# SINA RTSA# SOUTA CTSA# DTRA# RIA# COM PORT C VCC3 U1 MAX3243 C14 C12 C0.1U16Y0402 C0.1U16Y0402 27 RTSA# DTRA# SOUTA 59 60 63 62 66 65 58 SUSLED 24 FAN_SET 24 33R0402 RSTOUT0 33R0402 RSTOUT2 33R0402 RSTOUT1 HD_RST# 84 79 82 80 83 78 81 85 70 71 R249 R240 R246 15 X_4.7KR0402 KBDAT KBCLK MSDAT MSCLK SUSLED R215 A20GATE KBRST# KBDATA KBCLK MSDATA MSCLK 1KR/2 14 13 12 CTSA# RIA# DSRA# SINA DCDA# 14 14 21 21 21 21 VCC3 R192 V+ V- 10K0402 VCC3 T1OUT T2OUT T3OUT T1IN T2IN T3IN 19 18 17 16 15 20 R1OUT R2OUT R3OUT R4OUT R5OUT R20OUT 23 22 21 FORCEON FORCEOFF# INVALID# R1IN R2IN R3IN R4IN R5IN C1+ C1C2+ C2GND C17 26 CONN1B C10 28 24 25 LPC_PME# FAN_SET LPC_PME# VCC3 1KR/2 SOUTA R190 1KR/2 RSMRST# C9 C0.1U16Y0402 NSOUTA NDTRA NRTSA NDCDA CN1 CN2 C311 X_C1U10Y0402-RH JCASE1 AVCC3 X_1KR/2 RTSA# R189 1KR/2 DTRA# VCC3 R268 X_1KR/2 R267 X_1KR/2 R258 FAN_SET +12V 10KR1%/2 H1X2_black-RH C331 C0.1U16Y2 VCC5 +5VIN R261 22KR/2 X_0.082U300m_0603 THERMDC_CPU R264 10KR1%/2 A TMP_VREF Pull-down internally CHASSIS 56KR1%/2 R259 +12VIN THERMDC_CPU CP4 THERMDC_CPU R191 VCCP R263 10KR1%/2 TMP_VREF CPUVCORE R262 10K/4 MSI AUX_TMP RTSA# GP50 SOUTA DTRA# FAN_SET L: CFAD=2E L: TTL LEVEL L: KBC DISABLE L: DISABLE SPI L: CPU0 PWM50% H: CFAD=4E H: GTL LEVEL H: KBC ENABLE H: ENABLE SPI H: CPU0 PWM100% C510 C0.1U16Y2 RT1 10KRT1% MICRO-STAR INt'L CO., LTD Title LPC SUPER I/O & LPC & CONNECTORS THERMDC_CPU Size Document Number Rev MS-9826 THERMDC_CPU Date: B 8P4C-180P50N3 8P4C-180P50N3 Case Open VCC3 L19 A CONN-VGA_COM-3.18mm REMOVE 12V,5V SELECT NSINA NDSRA NRIA NCTSA R225 4.7KR0402 R188 NDSRA NRTSA NCTSA NRIA 34 33 32 31 C0.1U16Y0402 14 CP3 WDTO# 26 27 28 29 30 Winbond APnote Hardware Monitor X_1KR/2 NDCDA NSINA NSOUTA NDTRA NCTSA NRIA NDSRA NSINA NDCDA LPC I/O STRAPPING RESISTOR R235 C0.1U16Y0402 NRTSA 10 NDTRA 11 NSOUTA COM DUAL source 2200p 1KR/2 0R/2 3VDUAL FAN_SET THERMDA_CPU R272 R252 W83627DHG-RH-1 R269 4.7KR/2 Winbond APnote C337 VCC5 INDEX# 22 30 21 23 22 29 20 A_RST# PCI_CLK1 SERIRQ LPC_DRQ#0 LPC_FRAME# 13 INDEX# must be pulled up to 5V oly for A version chip U15 13 A_RST# 13,16 PCI_CLK1 13 SERIRQ 13 LPC_DRQ#0 13 LPC_FRAME# Sheet Monday, February 25, 2008 0A 20 of 34 D D C C CPU FAN PWM MODE +5VDUAL R270 20 CPU_FANOUT1 100/4/1 +12V VCC5 F-MICROSMD110F-RH POLY SWITCH FS1 D9 1N4148S C496 X_C0.1U16Y0402 MEC1 R332 10KR0402 DZ2 R4 X_1K/4 RN1 4.7K/4/8P4R VCC5 NPN-3904LT1-S-SOT23 EC21 10U16V1206 C6 X_0.1u/25V/4 20 MSDATA 20 MSCLK 1N5817 20 KBDATA 20 KBCLK SYS FAN PWM MODE MSDAT# FB3 300-600mA MSCLK# FB1 300-600mA KBDAT# FB4 300-600mA KBCLK# FB2 300-600mA JKBMS1 11 12 16 17 D C E 1KR0402 20 CPUFAN1 BH1X4B_WHITE-RH-2 Q30 B CPUFANIN B Q29 P-SI2303DS_SOT23 20 CPU_FANPWM 100/4/1 C3 220P C4 220P C5 220P CONN-KB-R 10 MS KB 13 14 15 4.7KR0402 G 1KR0402 10KR0402 R329 R333 R326 R336 27K_0402 R327 R330 PS2 KEYBOARD & MOUSE CONNECTOR 4.7KR0402 S B R337 C2 220P +12V VCC5 D10 C507 X_C0.1U16Y0402 R342 10KR0402 R339 4.7KR0402 G 1KR0402 change to 220p for EMI (1218) 1N4148S 4.7KR0402 R345 S R338 A R344 27K_0402 20 A 10KR0402 Micro Star Restricted Secret FAN1X3_white D C E 1KR0402 AUXFANIN R341 DZ1 Q32 B 20 AUX_FANPWM 100/4/1 SYSFAN1 Q31 P-SI2303DS_SOT23 R343 R340 Title VCC5 NPN-3904LT1-S-SOT23 EC24 10U16V1206 Rev IDE Conn/FAN/LPT/SATA Document Number 1N5817 MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Friday, February 22, 2008 Sheet of 21 34 0A E D C POWER CIRCUIT FOR USB PORT 0,1,2,3 B POWER CIRCUIT FOR USB PORT 4,5 SVCC1 SVCC2 +5VDUAL 5.1K/6 R700 EC2 C114 X_5.1K/6 330u_7343 /6.3V 60 mils C354 330u_7343 /6.3V + R278 + EC19 120 mils FS3 X_2.6A_miniSMDM260 FS4 2.6A_miniSMDM260 +5VDUAL A X_0.1u/16V/4 4 0.1u/16V/4 14 USB_OCP#_0123 14 USB_OCP#_45 FRONT USB CONNECTOR R279 10K/4 R701 10K/4 NEAR USB CONNECTOR there are two R1, R2 ,so change one to R700 in next version(1225) FRONT PANEL USB CONNECTOR FOR USB PORT 4,5 REAR PANEL USB CONNECTOR FOR USB PORT 0,1 SVCC1 SVCC2 SVCC2 RN4 ESD Protection LAN_USB1A SBD2SBD2+ ESD Protection SBD3SBD3+ SVCC1 23 24 25 26 27 28 29 30 UP DOWN SBD5+ SBD5- 4 SBD4+ SBD4- 14 14 14 14 USBP4 USBN4 USBP5 USBN5 USBP4 USBN4 USBP5 USBN5 X_0.1u/16V/4 SBD4+ SBD4SBD5+ SBD5- C113 JUSB1 X_CMC-L12-9007017 SBD4SBD4+ ESD3 X_ESD-IP4220 10 SBD5SBD5+ X_H2X5[9]M_COLOR-RH CONN-RJ45_USBX2_LEDX2_TX-3 RN2 SBD1- SBD1+ SBD0+ SBD0- 14 14 14 14 USBP3 USBN3 USBP2 USBN2 USBP3 USBN3 USBP2 USBN2 SBD3+ SBD3SBD2+ SBD2- CMC-L12-9007017 ESD2 ESD-IP4220 REAR PANEL USB CONNECTOR FOR USB PORT 2,3 FOR EMI SVCC1 C355 X_0.1u/25V/4 SVCC1 ESD Protection LAN_USB2A SBD2+ SBD0SBD0+ SBD1- SBD2- SBD1+ SBD3- SBD3+ ESD1 ESD-IP4220 UP DOWN 23 24 25 26 27 28 29 30 CONN-RJ45_USBX2_LEDX2_TX-3 RN3 14 14 14 14 USBP1 USBN1 USBP0 USBN0 USBP1 USBN1 USBP0 USBN0 SBD1+ SBD1SBD0+ SBD0- CMC-L12-9007017 1 MSI MICRO-STAR INt'L CO., LTD Title USB CONNECTORS Size Document Number Date: Monday, February 25, 2008 Rev 0A MS-9826 E D C B Sheet A 22 of 34 5 C357 VCC5 U22 NC7WZ08 10 HSYNC# HSYNC# VCC5 C358 X_0.1u/25V/4 5V_HSYNC X_0.1u/25V/4 D D VSYNC# VSYNC# VCC3 5V_VSYNC U23 NC7WZ08 10 VCC5 VCC3 D1 add for customer 1214 VGA_ESD R280 4.7K/4 VCC3 VCC3 Q11 10 5VDDCCL DAC_SCL _N-2N7002_SOT23 R50 4.7K/4 R25 4.7K/4 Q10 10 5VDDCDA DAC_SDAT BH1X8H-2PITCH_WHITE-RH N-2N7002_SOT23 C RR R L2 120nH/300mA 10 GR C37 22P/4 L1 C24 BR B C36 22P/4 L3 C25 R21 150R/1/4 C38 22P/4 VGA_B C26 R287 150R/1/4 22P/4 120nH/300mA 10 VGA_G R20 150R/1/4 1 R283 150R/1/4 22P/4 120nH/300mA G VGA_R R19 150R/1/4 1 R284 150R/1/4 10 C close VGA connector VGA CONNECTOR VGA_B VGA_G VGA_R A S-RB551V-30_SOD323 JVGA1 VGA_14 VGA_13 VGA_15 VGA_12 C R24 4.7K/4 22P/4 Closed NB change to 33p for EMI (1218) B VCC5 1.1A_microSMD110 FS2 B C27 0.1u/16V/4 CHANGE TO 22PF IN 1.0 (0219) C359 X_1u/16V/8 R16 R15 R17 R18 33/4 33/4 47R0402 47R0402 VGA_15 VGA_12 VGA_13 VGA_14 CONN1A 21 5VDDCCL 5VDDCDA 5V_HSYNC 5V_VSYNC C30 22P/4 C31 22P/4 VGA_G C33 10P/4 C32 10P/4 VGA_B VGA_9 10 11 VCC3 ESD Protection 12 VGA_12 13 VGA_13 14 VGA_14 15 23 VGA_ESD CHANGE C32,C33 TO 10PF IN 1.0 (0219) VGA_R VGA_15 CONN-VGA_COM-3.18mm ESD Protection A A VGA_15 VGA_R VGA_14 VGA_G VGA_12 VGA_13 ESD5 ESD-IP4220 ESD4 ESD-IP4220 VGA_B Micro Star Restricted Secret Title Rev TV_OUT & VGA CONNECTOR Document Number MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A MS-9826 Last Revision Date: Thursday, February 21, 2008 Sheet of 23 34 SATA_ACT# 15 PD_LED 15 ESD Protect Intel Front Panel D2 BAT54A-S-SOT23 C276 X_181P D D HDD- PWR_LED SUS_LED EMI C278 X_0.1u/25V/4 VCC3 C487 C489 X_0.1u/25V/4 X_0.1u/25V/4 3VDUAL JFP1 R163 20 12,14 220/6 HDD+ 0R/2 WDTO# R234 HDD+ PLED PWR_LED HDD- SLED SUS_LED RESET- PWSW+ PWSW+ R324 RESET+ PWSW- PWSW- C492 0.1u/16V/4 RESET33/4 RESET+ R325 FP_RST# C495 0.1u/16V/4 R323 4.7K/4 EMI 100/4/1 PSIN# 20 NC RESET+ JFP1 RESET+ 25 3VDUAL +5VDUAL R301 4.7KR0402 C C FP_RST# R180 330R0402 add 3v_sb for FP_RST# (1213) PWR_LED 20 FAN_SET FAN_SET R185 1KR0402 Q23 NPN-3904LT1-S-SOT23 +5VDUAL R196 330R0402 20 B SUSLED SUSLED R214 1KR0402 SUS_LED Q24 NPN-3904LT1-S-SOT23 B DC Connector VCC3 L04-22A7150-C36 DC Voltage IN L18 CH-2.2U14A_S-LF DC_IN D12V /?A C504 C0.1U50Y0603 C333 C0.1U50Y0603 C349 DC_10000P50V_0603 C8 C0.1U50Y0603 C503 C0.1U50Y0603 JPW1 12V GND VCC5 12V GND C342 0.1u/16V/4 0.1u/16V/4 A BH1X4B_white-2.5pitch-RH C332 C0.1U16V0402 DC_PWR-2X2M change to internel connector (1214) ADD C942 FOR EMI C348 C10U16Y1206 C244 HDPWR1 +12V C0.1U16X0402 A 0.1u/16V/4 VCC3 HDD Power D12V C346 EMI solution D12V C345 C344 Micro Star Restricted Secret C347 C10U10Y0805 Title C0.1U10X0402 Rev ATX connector / Front Panel Document Number MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Friday, February 22, 2008 Sheet 24 34 of 0A 3.3A DC_IN VCC5_SB R244 4.7R0603 D3 RB717F_SOT323 C2.2U10X50805 Place these CAPs close to FETs VIN C303 C312 C1U10X50402 DC_IN C506 5.2A C322 C1U25X0805 C505 C10U25X51206-RH C326 C0.1U50Y0603 C2200P50X0402 C501 C313 C0.1U50Y0603 C2200P50X0402 C500 C498 C10U25X51206-RH C10U25X51206-RH VREF2 add one pcs (1221) VCC3_PD 3VDUAL C300 L16 C0.1U25-X7R 9.6A EN5 EN3 PGOOD2 EN2 VBST2 DRVH2 LL2 DRVL2 33 GNDA + C296 NN-SP8K10S_SOP8-RH Q26 C329 C0.1U25-X7R R253 +5VDUAL /3.5A 4.7R0603 LL1 L17 10A CH-4.7u10A40mS-RH-1 C330 X_C0.1U10X0402 NN-SP8K10S_SOP8-RH C0.1U16Y0402 C339 17 18 19 20 21 22 23 24 C0.1U16Y0402 C220u6.3pSO-1 C301 X_C0.1U10X0402 SKIPSEL TONSEL 32 31 30 29 28 27 26 25 PGND2 CS2 VREG3 V5FILT VREG5 VIN CS1 PGND1 CH-4.7u10A40mS-RH-1 EC11 SKIPSEL TONSEL PGOOD1 EN1 VBST1 DRVH1 LL1 DRVL1 + R217 4.7R0603 LL2 10 11 12 13 14 15 16 C340 EC14 C220u6.3pSO-1 1 R220 X_10K0402 Q25 /1.2A U14 VO2 COMP2 VFB2 GND VREF2 VFB1 COMP1 VO1 VCC5 VIN TPS51120RHBR +3VALW PQ3 VCC5_SB C304 C10U10Y0805 N-AO4468_SOIC8 C1U10X50402 C10U10Y0805 C310 C1U10X50402 R232 4.7R0603 PS_ON_12V /6.6A VCC5 VREF2 /100mA C318 C10U10Y0805 max voltage 5.5 PS_ON_12V SP3 X_Short PAD 0603 R248 14.3KR1%0402 R218 14.3KR1%0402 SP1 X_Short PAD 0603 PQ4 N-AO4468_SOIC8 C338 VCC5_SB /8.4 A R165 1KR0402 R255 D VCC3 Q22 C319 1000P50X0402 R254 X_0R0402 G S X_0R0402 C277 D SP2 SLP_S5# IN 14,26 X_Short PAD 0603 R146 4.7KR0402 TONSEL SKIPSEL N-2N7002_SOT23 C1U16Y Q21 G S C256 C1U16Y R256 N-2N7002_SOT23 0R0402 CHANGE Q42,Q44 TO 7002 (1219) 3VDUAL R294 USB_PHY X_4.7K/4 5.5A C437 DC_IN U24 2.2UF Vin Q28 P-AO4413_SOIC8 Vout C436 GND EN 1U_16V PG 3VDUAL APL5158 C325 C0.47U25Y5 +12V R296 0R0402 +12V 150mA R331 10K0402 add for FP-RST IN 1.0 (0218) 33KR0603 PS_ON_12V VCC5 Q27 PS_ON_3V R75 10K0402 IN R86 0R0402 OUT VRM_EN S D C0.1U16Y0402 IN 26 VDDA_25_PWROK U9 C167 N-2N7002_SOT23 C1U16Y add C977 (1226) 3VDUAL G S C165 D N-2N7002_SOT23 Q13 R79 X_4.7K_0402 PWR_OK refer to ATX timing N-2N7002_SOT23 G IN POWER OK Q16 Q19 add R-C to aviod inrush current (1220) S D R105 10K0402 26 VCC_1V2_PG R99 240KR0402 VDDA_25 1A GND 2A 1Y VCC 2Y LVC2G14IDCKRQ1_SC70-6-RH NB_PWRGD OUT NB_PWRGD N-2N7002_SOT23 ADD VRM_EN (1212) VDDA_25_PWROK R77 G S R102 10K0402 N-2N7002_SOT23 C1U16Y Q14 G VCC3 27 D G S IN X_C1U16Y SLP_S3# G C335 D VRM_EN Q15 14,20,26 SLP_S3# 56KR0402 D R84 10K0402 N-2N7002_SOT23 C497 3VDUAL C327 C0.1U16Y0402 R265 S D2 S1 G1 S2 G2 2N7002DW 20 SIO_PSON# 10K0402 3VDUAL X_C1U16Y S-SM5817A[SN]_DO214AC PR15 470KR0603 24 PQ5 C0.1U50Y0603 PC18 RESET+ C502 D1 PS_ON_3V D11 RESET+ R241 240KR0402 R251 R328 0R0402 MICRO-STAR INt'L CO., LTD 10 Title R104 SB_PWRGD 14 Size Document Number Date: Monday, February 25, 2008 Rev 0A MS-9826 0R0402 Sheet 25 of 34 D D DC_IN 12V/ 2.2A add PC26,PC11 PQ1 N-AO4468_SOIC8 PC14 PC11 PC12 C0.1U50Y0603 C2200P50X0402 C10U25X51206-RH C10U25X51206-RH DDR2_DRVH PC13 (1221) VCC_DDR PL2 _CH-1.5U18A-RH 1.8V DDR2_LL TP1 /11.7A VCC_DDR2_PG PC5 C0.1U25Y PQ2 RI1 X_2.2R_1% IN DDR2_DRVL PC4 C1U16Y To CPU Copper trace width > 250mils , Fill island behind DIMM > 400mils PC15 19 DRVL1 21 20 LL1 DRVH1 CS1 17 16 V5FILT 15 VFB2 VO2 EN2 PGOOD2 CS2 14 PGND2 13 VCC5_SB PR14 3.3R 0.7mA PR13 PR5 16.9KR0402_1% TONSEL 20mA V5IN 16.9KR0402_1% X_1000P50X0402 VCC_1V2_PG 25 VCC_1V2_PG CI1 N-AO4410_SOIC8 C DC_IN PC17 PC10 C4.7U10Y0805 C1U16Y Q6 VCC_1V2_FB C PGND1 18 DRVL2 0R0402 25 12 PR9 GPAD TPS51124RGER_QFN24-RH LL2 GND DRVH2 VFB1 11 DDR2_FB 10 VO1 PR7 VBST2 VBST1 PGOOD1 PR8 100KR0402_1% 71.5KR0402_1% 23 PU1 22 C0.1U10X0402 PR6 100KR0402 24 SLP_S5# EN1 14,25 4.7R0603 PR4 12V/ 1.25A PC3 PC7 PC1 PC16 C0.1U50Y0603 C2200P50X0402 C10U25X51206-RH C10U25X51206-RH N-AO4468_SOIC8 VCC_1V2_DRVH VCC_1V2_EN VCC_1V2 PL1 CH-0.82U24A-RH VCC_1V2_LL PC8 1.2V / 10A PC9 C0.1U25Y R1 X_2.2R_1% Q3 R11-0143T12-R01 N-AO4410_SOIC8 C1 R11-0243T12-Y01 X_1000P50X0402 PC2 C330U2.5POS-1 VCC_1V2_DRVL + Vadj= 0.758v 4.7R0603 PR12 C0.01U25X0402 PC6 C0.1U10X0402 VCC5_SB PR10 PR11 24KR0402_1% 14KR0402_1% PR1 10K0402 VCC3 VDDA_25 300mA VCC5 the value of PR9,PR10 should be calculated again (1214) PR10=14K, PR9=24KR (1217) B D B Q1 PR3 10K0402 IN S G R76 1KR D G N-2N7002_SOT23 S VRM_GD +1.8V_S0 VCC_1V2_EN Q2 IN 27 4.7K_0402 C121 C1U10Y U8 D 0R0805 R2 VCC3 N-2N7002_SOT23 Q4 G S N-2N7002_SOT23 25 VDDA_25_PWROK VDDA_25_PWROK POK EN 1KR R80 VCC3 X_1KR R78 APL5913KAC-TRL_SOP8-RH D4 DDR VTT Power PC20 C0.1U10X0402 VOUT#3 FB R85 1KR1%0402 C128 2.2u0603 N-APM2054N_SOT89 change 330uf to 22u, 1u to 10uf D5 A 1PS226_SOT23 R85=1.0K , R81=470 , C351=2.2uF (1217) VTT_DDR R291 0R0805 +1.8V_S0 R231 1K/4 1% 220UF/4V EC10 PC19 EC3 22U6.3X0805 450mA Micro Star Restricted Secret Title C0.1U10X0402 Document Number Rev MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw add PC19, PC20 (0220) EC1 22U6.3X0805 R223 1K/4 1% W83310DG_SOP8-RH 0.9V/2.9A VIN GND VREF1 VOUT 4.7K_0402 +1 NC VREF2 ENABLE VCNTL BOOT_SEL C115 3.3V must not exceed the 1.8V rails by >2.1V U13 R98 VCC_DDR 3VDUAL A Q18 VCC_DDR C159 0.1u/16V/4 VDDA_25 R81 470R1%0402 1PS226_SOT23 VCC5 VCC3 VCC_DDR VIN#9 VOUT GND PR2 10K0402 VIN C10U6.3X50805 VCC5 Q5 NPN-3904LT1-S-SOT23 VCC3 SLP_S3# VCNTL R3 14,20,25 SLP_S3# 0A Last Revision Date: Monday, February 25, 2008 Sheet of 26 34 Voltage Regular Module CALCULATE WITH 65W, 12V WILL BE 6.8A +12VP_FET + D12V S-SM5817A[SN]_DO214AC R349 U12 ISL6312CR 10 C295 R233 249R1% R239 3KR1% C306 C12P50N RT2 X_4.7KRT R245 0R_0402 R247 X_1.6KR 13 14 15 R227 0R_0402 C317 R229 X_C680P16 X_750R1% 16 R212 UGATE1 PHASE1 LGATE1 32 33 30 ISEN1+ ISEN1- 35 34 2.2R LGATE1 C290 FB IDROOP BOOT2 27 UGATE2 PHASE2 LGATE2 26 25 28 VDIFF C 100R R334 C305 2.2R 19 20 PVCC3 42 COREFB- C307 18 X_0.1u/10V/6 VSEN C320 X_10u-0805 17 R242 R335 100R VCC5 VCC5 R209 R193 C314 X_0.1u/10V/6 -15mV Offset X_100KR X_5.1KR R202 changed 0627 X_1K-0402 R194 BOOT3 40 UGATE3 PHASE3 LGATE3 39 38 41 ISEN3+ ISEN3- 44 43 0-0805 R206 X_4.7KR1% R277 UGATE2 R271 ISEN2R167 C309 C0.1U16 R237 R238 1KR1% 2.2R0805 D12V X_4.7KR1% 10KR0402 PHASE2 U17 ISEN2 C324 C0.1U16 R213 X_10.2KR1% C283 C511 C350 LGATE3 X_C2200P16 R164 0R_0402 C275 C0.1U16 ISEN3- OVPSEL/SDA 11 45 REF FS SS/RST/A0 ISEN4+ ISEN4PWM4 24 EN_PH4 23 ISEN3 R348 C274 C0.1U16 R346 U20 SP8 X_Short PAD 0603 C X_C4.7U35Y1206 1u/16V/8 add copper by power team (1214) 10KR0402 BSC059N03S R174 X_4.7KR1% PHASE3 U16 COIL1 R228 CH-0.22U25A_S VCCP R266 2.2/8 SP6 X_Short PAD 0603 SP4 X_Short PAD 0603 C336 C1000P50X BSC032N03S VCC5 0R_0402 CONNECT TO 5V,DIABLE PWM_4 ISEN3- R179 R203 120KR 240KR REMOVE R213 FOR POWER TEST (0220) VCCP C328 C1000P50X C294 C0.01U10 B CH-0.22U25A_S SP9 X_Short PAD 0603 +12VP_FET UGATE3 CD270u16SO-RH-2 49 0R_0402 DRSEL/SCL R257 2.2/8 BSC032N03S 0.1u/25V/6 C281 21 22 COIL3 EC18 2.2R OFS 1u/16V/8 BSC059N03S X_C2200P16 0R_0402 R236 R162 1KR1% 12 C353 CD270u16SO-RH-2 U19 0-0805 X_0.1u/10V/6 VCC5 RGND C315 GND 0R_0402 C291 C0.1U16 LGATE2 C308 ISEN2+ ISEN2- C0.1U16 +12VP_FET EC17 ISEN1 0.1u/25V/6 C285 1u/16V/8 R177 R243 0R_0402 COREFB+ C293 R221 VCCP X_C2200P16 0R_0402 R195 ISEN1- SP7 SP5 X_Short PAD 0603X_Short PAD 0603 UGATE1 0.1u/25V/6 ISEN1 31 ISEN1- BOOT1 C341 C1000P50X BSC032N03S R201 1KR1% COMP 2.2/8 29 ISEN2 changed 0627 VCCP BOTTOM PAD CONNECT TO GND Through VIAs ISEN3 VCC5 CH-0.22U25A_S ISEN2- ADD SO10,SP11 FOR POWER TEAM DEBUG (0222) PVCC1_2 COIL2 R273 VID5SP10 VID4 VID3 VID2SP11 VID1 VID0 PGOOD EN VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL BSC059N03S U18 C298 1u/16V/8 VID[0 5] 37 36 46 47 X_Short PAD 0603 48 X_Short PAD 0603 C316 C1500P25 10KR0402 4.7K-0402 VCC VRM_EN R184 R347 PHASE1 + VRM_GD VRM_EN R216 2.2R0805 + C287 0.1u/10V/6 C299 4.7u/10V/8 D 0.8375~1.6V / 65A R222 X_2.2R C284 C0.1U16 C334 X_C4.7U35Y1206 0-0805 R178 1K-0402 X_C4.7U35Y1206 1u/16V/8 VCC5 D C352 C351 U21 D12 D12V EC16 CD270u16SO-RH-2 VCC5 26 10.8A COIL4 CH-2.2U14A_S-LF Add D12，reserve R222 , S3 leackage current from chip to VCC5 because of power from VID1,4 (0222) 25 B EL Capacitors 1 + EC22 330U2 + EC12 330U2 + EC13 330U2 + EC15 330U2 + EC25 330U2 2 + EC23 330U2 1 VCCP A A Micro Star Restricted Secret Title Document Number Rev MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw 0A Last Revision Date: Monday, February 25, 2008 Sheet of 27 34 D D C C BLANK B B A A Micro Star Restricted Secret Title Rev REVERSE Document Number 0A MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Sunday, December 09, 2007 Sheet 28 34 of PCB1 D D CPU2 U14_X1 MSI DDR P30-0982610-TB7 PCB D03-0980410-G36 D03-0980410-G37 D03-0980410-D05 SB_HEATSINK Mounting Holes Optics Orientation Holes 9 5 C FM3 X MH4 C 8 Simulation MH3 X_JS1 SIM2 NB_HEATSINK E95-0000003 MSI DDR VBAT1-S1 BAT-BCR2032P-RH U11_X1 X_JS2 SIM1 X_PIN1*2 X_PIN1*2 FM2 X X 9 5 MH2 FM7 FM1 X X MH1 X_FM X_FM X_FM X_FM FM5 X FM4 X FM6 X_FM CHANGE GNDF TO GND X_FM X_FM remove FM2 FM13 FM4 FM3 FM11 FM6 (1221) B B A A Micro Star Restricted Secret Title Document Number Rev MANUAL PARTS MS-9826 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Monday, February 25, 2008 Sheet of 29 34 0A ... 0. 1u _ 10 V _04 02 VCC_DDR C 206 0. 1u _ 10 V _04 02 C192 0. 1u _ 10 V _04 02 VCC_DDR C243 0. 1u _ 10 V _04 02 C2 40 0.1u _ 10 V _04 02 VCC_DDR C2 01 0. 1u _ 10 V _04 02 C252 0. 1u _ 10 V _04 02 VCC_DDR C236 0. 1u _ 10 V _04 02 C184 0. 1u _ 10 V _04 02... 0. 1u _ 10 V _04 02 C 203 0. 1u _ 10 V _04 02 VCC_DDR C178 0. 1u _ 10 V _04 02 C226 0. 1u _ 10 V _04 02 VCC_DDR C224 0. 1u _ 10 V _04 02 C199 0. 1u _ 10 V _04 02 VCC_DDR C182 0. 1u _ 10 V _04 02 C 208 0. 1u _ 10 V _04 02 VCC_DDR C 216 0. 1u _ 10 V _04 02... MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 add for DIMM (12 18) C 214 0. 1u _ 10 V _04 02 VCC_DDR C186 0. 1u _ 10 V _04 02 C235 0. 1u _ 10 V _04 02 VCC_DDR C239 0. 1u _ 10 V _04 02 C238 0. 1u _ 10 V _04 02 VCC_DDR C1 90 0.1u _ 10 V _04 02 C1 81 0. 1u _ 10 V _04 02