5 Title D Page Cover Sheet Block Diagram CPU-CLK/Control/MISC/PEG ,CPU-Memory 3,4 CPU-Power,CPU-GND 5,6 DDRIII DIMMA1&DDRIII DIMMB1 7,8 LYNX-PCI/E/DMI/USB/CLK LYNX-SATA/HOST/FAN/GPIO/VGA 10 LYNX-SMB/LPC/AUDIO/RTC/RST 11 LYNX-POWER PIN,GND/ LYNX STRAPS 12,13 ,14 PCIE1(X1) & PCIE2(X16) Slots 15 DVI , HDMI 16,17 SIO-NUVOTON NCT6779D 18 ALC892/887 19 LAN RTL8111G/8106E 20 SATA /USB3.0 Connector 21 USB3.0 Renes UPD720202 2PORT 22 USB2.0 Connector 23 VGA 24 ACPI Controller UPI 25 CPU Power - ISL95812,CPU Power - MOS 26 27 DDR Power -UP1513 1-Phase 28 PCH Power - OP+MOS 29 PCH Power - ME Power 30 FAN 31 ATX F_Panel/EMI/TPM/LPT 32 A XDP CPU & COM PORT 33 Manual Parts 34 MS-7846 mATX Ver: 2.1 Intel Sharkbay plamform H81 COLAY B85 H87 D CPU: INTEL-Haswell LGA1150 System Chipset: H81,B85,H87 C B Memory: DDRIII (1333/1666MHz) * (Dual Channel) PWM: VRD12 - ISL95812 OnBoard Chipset: C HD Audio Codec:RTL887 LAN-realtek8111G SIO:NUVOTON 6779D SPI ROM: 64 MB & 128MB Expansion Slots: PCI Express (X16) Slot * PCI Express (X1) Slot * Other: B VGA*1 SATA2*2 SATA3*2 FRONT USB2.0 *4 FRONT USB3.0 *2 REAL USB2.0 *2 REAL USB3.0 *2 PS2*1 FRONT COM PORT*1 REAL PRINT PORT*1 A MICRO-STAR INT'L CO.,LTD MS-7846 MSI Size Custom Document Description Rev 2.1 Cover Sheet Date: Monday, August 12, 2013 Sheet 1 of 38 MS-7846 Block Diagram VR12.5 ISL95812 CHANNEL A D DDR3 DIMM1 D INTEL DVI(portB) CHANNEL B Haswell LGA1150 FDIX2 DDR3 DIMM2 DMIX4 VGA realtek 8111G GIGA LAN C C FRONT USB PORT PORT10 PORT8 PORT11 PORT9 USB 2.0 REAL USB PORT PORT4 PORT5 HD AUDIO I/F Lynx Point USB 2.0 708 ball SATA III I/F FRONT USB PORT USB30-0 USB30-1 SATA0 SATA1 SATA4 SATA5 USB 3.0 B SPI ROM HD AUDIO RTL892 B SPI I/F LPC I/F TPM 1.2 NTC6779D A A KBD MOUSE print port com port MICRO-STAR INT'L CO.,LTD MS-7846 MSI Size Custom Document Description Rev 2.1 Block Diagram Date: Monday, August 12, 2013 Sheet of 38 CPU1C OF CPU1E OF R87 9 26 H_VIDSCLK 26 H_VIDSOUT 26 VID_ALERT# 33 H_PWRGD 11 CPU_PWRGD 11 PCH_MEM_PWRGD 11,33 CPURST# D CK_DMI_P CK_DMI_N R99 44.2R1% SP4 X_R/2 CK_DMI_P CK_DMI_N V5 V4 H_VIDSCLK H_VIDSOUT H_VIDALERT# C38 C37 B37 H_PWRGD H_PWRGD AB35 AK21 M39 CPURST# 10 PM_SYNC 10,18 H_PECI P36 N37 M36 K38 F37 H_CATERR# H_PROCHOT# H_THERMTRIP# TP4 26 H_PROCHOT# 10 H_THERMTRIP# D38 VREF_CA_A VREF_CA_B 2R1% 2R1% CPU_DDR_VREF R141 100R1% R142 75R1% R138 100R1% R107 49.9R1% R127 R135 C123 0.022u16 C45 X_10u6.3X6 R129 24.9R1% 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 C H_CFG0 H_CFG1 H_CFG2 H_CFG3 H_CFG4 H_CFG5 H_CFG6 H_CFG7 H_CFG8 H_CFG9 H_CFG10 H_CFG11 H_CFG12 H_CFG13 H_CFG14 H_CFG15 H_CFG16 H_CFG17 H_CFG18 H_CFG19 DDR_COMP0 DDR_COMP1 DDR_COMP2 CFG_COMP0 AB38 R1 P1 R2 H40 H_CFG0 H_CFG1 H_CFG2 H_CFG3 H_CFG4 H_CFG5 H_CFG6 H_CFG7 H_CFG8 H_CFG9 H_CFG10 H_CFG11 H_CFG12 H_CFG13 H_CFG14 H_CFG15 H_CFG16 H_CFG17 H_CFG18 H_CFG19 AA37 Y38 AA36 W38 V39 U39 U40 V38 T40 Y35 AA34 V37 Y34 U38 W34 V35 Y37 Y36 W36 V36 BCLK_0 BCLK#_0 PWR_DEBUG VIDSCLK VIDSOUT VIDALERT# TESTLO_P6 TESTLO_N5 PWRGOOD SM_DRAMPWROK RESET# DPLL_REF_CLK# DPLL_REF_CLK PM_SYNC PECI CATERR# PROCHOT# THERMTRIP# VCC_SENSE VSS_SENSE N40 PWR_DEBUG R94 R150 R149 P6 N5 150R1% PCH_1P05 PWR_DEBUG X_10K 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 33 49.9R1% 49.9R1% W6 W5 CK_DPNS_DN CK_DPNS_DP E40 F40 9 CPU_VCC_SENSE CPU_VSS_SENSE 26 26 SKTOCC# SM_VREF SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 CFG_RCOMP0 TDO TDI TCK TMS CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 TRST# PRDY# PREQ# DBR# BPM#_0 BPM#_1 BPM#_2 BPM#_3 BPM#_4 BPM#_5 BPM#_6 BPM#_7 F39 F38 D39 E39 CPU_TDO CPU_TDI CPU_TCK CPU_TMS E37 L39 L37 G40 CPU_TRST# XDP_CPU_PRDY# XDP_CPU_PREQ# CPU_DBR# SP5 CPU_TDO CPU_TDI CPU_TCK CPU_TMS CPU_TRST# 33 XDP_CPU_PRDY# 33 XDP_CPU_PREQ# 33 FP_RST# 11,32,33 X_R/2 XDP_CPU_BPM_N0 XDP_CPU_BPM_N1 XDP_CPU_BPM_N2 XDP_CPU_BPM_N3 XDP_CPU_BPM_N4 XDP_CPU_BPM_N5 XDP_CPU_BPM_N6 XDP_CPU_BPM_N7 G39 J39 G38 H37 H38 J38 K39 K37 33 33 33 33 XDP_CPU_BPM_N0 XDP_CPU_BPM_N1 9 9 9 9 33 33 TP3 TP7 TP6 TP5 TP2 TP8 E15 F15 D14 E14 E13 F13 D12 E12 E11 F11 F10 G10 E9 F9 F8 G8 D3 D4 E4 E5 F5 F6 G4 G5 H5 H6 J4 J5 K5 K6 L4 L5 EXP_A_RXP_0 EXP_A_RXN_0 EXP_A_RXP_1 EXP_A_RXN_1 EXP_A_RXP_2 EXP_A_RXN_2 EXP_A_RXP_3 EXP_A_RXN_3 EXP_A_RXP_4 EXP_A_RXN_4 EXP_A_RXP_5 EXP_A_RXN_5 EXP_A_RXP_6 EXP_A_RXN_6 EXP_A_RXP_7 EXP_A_RXN_7 EXP_A_RXP_8 EXP_A_RXN_8 EXP_A_RXP_9 EXP_A_RXN_9 EXP_A_RXP_10 EXP_A_RXN_10 EXP_A_RXP_11 EXP_A_RXN_11 EXP_A_RXP_12 EXP_A_RXN_12 EXP_A_RXP_13 EXP_A_RXN_13 EXP_A_RXP_14 EXP_A_RXN_14 EXP_A_RXP_15 EXP_A_RXN_15 DMI_RX0 DMI_RX0# DMI_RX1 DMI_RX1# DMI_RX2 DMI_RX2# DMI_RX3 DMI_RX3# DMI_RX0 DMI_RX0# DMI_RX1 DMI_RX1# DMI_RX2 DMI_RX2# DMI_RX3 DMI_RX3# U3 T3 U1 V1 W2 V2 Y3 W3 D1 C2 B3 A4 PEG_RX_0 PEG_RX#_0 PEG_RX_1 PEG_RX#_1 PEG_RX_2 PEG_RX#_2 PEG_RX_3 PEG_RX#_3 PEG_RX_4 PEG_RX#_4 PEG_RX_5 PEG_RX#_5 PEG_RX_6 PEG_RX#_6 PEG_RX_7 PEG_RX#_7 PEG_RX_8 PEG_RX#_8 PEG_RX_9 PEG_RX#_9 PEG_RX_10 PEG_RX#_10 PEG_RX_11 PEG_RX#_11 PEG_RX_12 PEG_RX#_12 PEG_RX_13 PEG_RX#_13 PEG_RX_14 PEG_RX#_14 PEG_RX_15 PEG_RX#_15 PEG_TX_0 PEG_TX#_0 PEG_TX_1 PEG_TX#_1 PEG_TX_2 PEG_TX#_2 PEG_TX_3 PEG_TX#_3 PEG_TX_4 PEG_TX#_4 PEG_TX_5 PEG_TX#_5 PEG_TX_6 PEG_TX#_6 PEG_TX_7 PEG_TX#_7 PEG_TX_8 PEG_TX#_8 PEG_TX_9 PEG_TX#_9 PEG_TX_10 PEG_TX#_10 PEG_TX_11 PEG_TX#_11 PEG_TX_12 PEG_TX#_12 PEG_TX_13 PEG_TX#_13 PEG_TX_14 PEG_TX#_14 PEG_TX_15 PEG_TX#_15 DMI_RX_0 DMI_RX#_0 DMI_RX_1 DMI_RX#_1 DMI_RX_2 DMI_RX#_2 DMI_RX_3 DMI_RX#_3 DMI_TX_0 DMI_TX#_0 DMI_TX_1 DMI_TX#_1 DMI_TX_2 DMI_TX#_2 DMI_TX_3 DMI_TX#_3 A12 B12 B11 C11 C10 D10 B9 C9 C8 D8 B7 C7 A6 B6 B5 C5 E1 E2 F2 F3 G1 G2 H2 H3 J1 J2 K2 K3 M2 M3 L1 L2 DMI_TX0 DMI_TX0# DMI_TX1 DMI_TX1# DMI_TX2 DMI_TX2# DMI_TX3 DMI_TX3# AA4 AA5 AB3 AB4 AC5 AC4 AC1 AC2 EXP_A_TXP_0 EXP_A_TXN_0 EXP_A_TXP_1 EXP_A_TXN_1 EXP_A_TXP_2 EXP_A_TXN_2 EXP_A_TXP_3 EXP_A_TXN_3 EXP_A_TXP_4 EXP_A_TXN_4 EXP_A_TXP_5 EXP_A_TXN_5 EXP_A_TXP_6 EXP_A_TXN_6 EXP_A_TXP_7 EXP_A_TXN_7 EXP_A_TXP_8 EXP_A_TXN_8 EXP_A_TXP_9 EXP_A_TXN_9 EXP_A_TXP_10 EXP_A_TXN_10 EXP_A_TXP_11 EXP_A_TXN_11 EXP_A_TXP_12 EXP_A_TXN_12 EXP_A_TXP_13 EXP_A_TXN_13 EXP_A_TXP_14 EXP_A_TXN_14 EXP_A_TXP_15 EXP_A_TXN_15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 DMI_TX0 DMI_TX0# DMI_TX1 DMI_TX1# DMI_TX2 DMI_TX2# DMI_TX3 DMI_TX3# 9 9 9 9 D C RDVD_TP_01 RDVD_TP_02 RDVD_TP_03 RDVD_TP_04 HASWELL VCCIOA R139 24.9R1% PEG_COMP P3 PEG_RCOMP L 250mils , Fill island behind DIMM > 400mils C70 X_0.1u10 0.2075A*4=0.8A VCC5 A VCC_DDR VTT_DDR C U9 R121 SLP_S4# 4.7K Q20 B E 11,18,22,23,25 2N3904 C147 0.1u10 NC3 NC2 NC1 VCNTL A VCC_DDR VIN GND REFIN VOUT GND DDRVTT_VREF R159 10K1% x1 per dimm MICRO-STAR INT'L CO.,LTD R164 10K1% 1.25V/2.9A C156 0.1u10 C152 0.1u10 C154 22u6.3X8 C153 22u6.3X8 MS-7846 MSI UP0109PSW8_PSOP8-HF P.S Only for meet Intel power down sequence Size Custom close pin Document Description Date: Monday, August 12, 2013 Rev 2.1 DDR Power -UP6103 1-Phase Sheet 28 of 38 PCH Power:1.05V 5.747A +12V 3VA ATX_5VSB C380 0.1uX25 VCC_DDR R200 22.1K1% D V1P05_CTRL_INPUT Q70 R205 C X_0R + - VCC3 PCH_VCC3 Q34 D 1P05_GATE G S N-TD422BL_TO252-3-HF R273 R198 11K1% E 2N7002 C208 0.1u10 R199 20K1% R196 X_20K1% C207 X_0.1u10 U15 Q71 VCC3 R192 47K VCC_DDR R451 X_47K X_0R/6 B 26 SLP_S3_CTRL 0.133A D 3.389x(11/(22.1+11))=1.126V R204 47K U11A AS358MTR-G1_SOIC8-HF C VCC1_5_CTRL_INPUT B VIN VOUT1 VOUT2 EN GND E N-SST3904_SOT23 1.4V enable UP7534AM5 C204 X_1u6.3 (OS-CON CAP) PCH_FB R197 2N7002 Q52 1K PCH_1P05 D + G S C C215 X_1u16X6 high by VCC3 CRB low by S3 SLP_S3_CTRL EC25 820u2.5SO C PCH_1P05V PCH_VCC3 PCH Power:1.5V 0.183A VCC3 +12V 3VA VCC3 ATX_5VSB R188 22.1K1% ATX_5VSB R189 47K U11B VCC1_5_CTRL_INPUT V1P5_CTRL_INPUT R193 47K VCC1_5_FB D 26 PCH1P05_CTRL Q37 G C S Q36 2N7002 G2 R191 17.8K1% D2 C198 0.1u10 3.389x(17.8/(22.1+17.8))=1.511V R194 20K + - B AS358MTR-G1_SOIC8-HF Q35 VCC1_5_GATE D G S N-P3057LCG_SOT89-RH B R186 20K1% R190 X_20K1% C199 X_0.1u10 D1 R207 4.7K Q38 2N3904 B S2 VCC1_5_CTRL_INPUT G1 E PCH_1P05 S1 C217 NN-2N7002DW (OS-CON CAP) 1u16 R187 Ib=(PCH_1P05-Vbe)/R207=0.021mA Ic=(ATX_5VSB-Vce)/R194=0.24mA Ic(max)