5 D D 加电阻 在H61GV80a基础上修改 Version: 1.0 C C B B A A GM Confidential Title Cover Sheet Size B Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1 1.0 of 30 D D ? CPU1C SKT_H2 ? DMI_IT_MR_0_DP DMI_IT_MR_0_DN DMI_IT_MR_1_DP DMI_IT_MR_1_DN DMI_IT_MR_2_DP DMI_IT_MR_2_DN DMI_IT_MR_3_DP DMI_IT_MR_3_DN W5 W4 V3 V4 Y3 Y4 AA4 AA5 P3 P4 R2 R1 T4 T3 U2 U1 V_CPU_VCCIO Near PIN 500MIL DMI_RX[0] DMI_RX#[0] DMI_RX[1] DMI_RX#[1] DMI_RX[2] DMI_RX#[2] DMI_RX_3 DMI_RX#[3] PE_RX[0] PE_RX#[0] PE_RX[1] PE_RX#[1] PE_RX[2] PE_RX#[2] PE_RX[3] PE_RX#[3] DMI 11 11 11 11 11 11 11 11 PEG_RX[0] PEG_RX#[0] PEG_RX[1] PEG_RX#[1] PEG_RX[2] PEG_RX#[2] PEG_RX[3] PEG_RX#[3] PEG_RX[4] PEG_RX#[4] PEG_RX[5] PEG_RX#[5] PEG_RX[6] PEG_RX#[6] PEG_RX[7] PEG_RX#[7] PEG_RX[8] PEG_RX#[8] PEG_RX[9] PEG_RX#[9] PEG_RX[10] PEG_RX#[10] PEG_RX[11] PEG_RX#[11] PEG_RX[12] PEG_RX#[12] PEG_RX[13] PEG_RX#[13] PEG_RX[14] PEG_RX#[14] PEG_RX[15] PEG_RX#[15] GEN C EXP_A_RX_0_DP EXP_A_RX_0_DN EXP_A_RX_1_DP EXP_A_RX_1_DN EXP_A_RX_2_DP EXP_A_RX_2_DN EXP_A_RX_3_DP EXP_A_RX_3_DN EXP_A_RX_4_DP EXP_A_RX_4_DN EXP_A_RX_5_DP EXP_A_RX_5_DN EXP_A_RX_6_DP EXP_A_RX_6_DN EXP_A_RX_7_DP EXP_A_RX_7_DN EXP_A_RX_8_DP EXP_A_RX_8_DN EXP_A_RX_9_DP EXP_A_RX_9_DN EXP_A_RX_10_DP EXP_A_RX_10_DN EXP_A_RX_11_DP EXP_A_RX_11_DN EXP_A_RX_12_DP EXP_A_RX_12_DN EXP_A_RX_13_DP EXP_A_RX_13_DN EXP_A_RX_14_DP EXP_A_RX_14_DN EXP_A_RX_15_DP EXP_A_RX_15_DN CPU1D PEG_TX[0] PEG_TX#[0] PEG_TX[1] PEG_TX#[1] PEG_TX[2] PEG_TX#[2] PEG_TX[3] PEG_TX#[3] PEG_TX[4] PEG_TX#[4] PEG_TX[5] PEG_TX#[5] PEG_TX[6] PEG_TX#[6] PEG_TX[7] PEG_TX#[7] PEG_TX[8] PEG_TX#[8] PEG_TX[9] PEG_TX#[9] PEG_TX[10] PEG_TX#[10] PEG_TX[11] PEG_TX#[11] PEG_TX[12] PEG_TX#[12] PEG_TX[13] PEG_TX#[13] PEG_TX[14] PEG_TX#[14] PEG_TX[15] PEG_TX#[15] DMI_TX[0] DMI_TX#[0] DMI_TX[1] DMI_TX#[1] DMI_TX[2] DMI_TX#[2] DMI_TX[3] DMI_TX#[3] PE_TX[0] PE_TX#[0] PE_TX[1] PE_TX#[1] PE_TX[2] PE_TX#[2] PE_TX[3] PE_TX#[3] C13 C14 E14 E13 G14 G13 F12 F11 J14 J13 D8 D7 D3 C3 E6 E5 F8 F7 G10 G9 G5 G6 K7 K8 J5 J6 M8 M7 L6 L5 N5 N6 V7 V6 W7 W8 Y6 Y7 AA7 AA8 P8 P7 T7 T8 R6 R5 U5 U6 DMI_MT_IR_0_DP DMI_MT_IR_0_DN DMI_MT_IR_1_DP DMI_MT_IR_1_DN DMI_MT_IR_2_DP DMI_MT_IR_2_DN DMI_MT_IR_3_DP DMI_MT_IR_3_DN SKT_H2 REV = BALLMAP_REV = 1.6 EXP_A_TX_0_DP 10 EXP_A_TX_0_DN 10 EXP_A_TX_1_DP 10 EXP_A_TX_1_DN 10 EXP_A_TX_2_DP 10 EXP_A_TX_2_DN 10 EXP_A_TX_3_DP 10 EXP_A_TX_3_DN 10 EXP_A_TX_4_DP 10 EXP_A_TX_4_DN 10 EXP_A_TX_5_DP 10 EXP_A_TX_5_DN 10 EXP_A_TX_6_DP 10 EXP_A_TX_6_DN 10 EXP_A_TX_7_DP 10 EXP_A_TX_7_DN 10 EXP_A_TX_8_DP 10 EXP_A_TX_8_DN 10 EXP_A_TX_9_DP 10 EXP_A_TX_9_DN 10 EXP_A_TX_10_DP 10 EXP_A_TX_10_DN 10 EXP_A_TX_11_DP 10 EXP_A_TX_11_DN 10 EXP_A_TX_12_DP 10 EXP_A_TX_12_DN 10 EXP_A_TX_13_DP 10 EXP_A_TX_13_DN 10 EXP_A_TX_14_DP 10 EXP_A_TX_14_DN 10 EXP_A_TX_15_DP 10 EXP_A_TX_15_DN 10 13 FDI_FSYNC_0 13 FDI_LSYNC_0 13 FDI_FSYNC_1 13 FDI_LSYNC_1 V_CPU_VCCIO 13 R1 FDI_INT 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 PEG REV = BALLMAP_REV = 1.6 B11 B12 D12 D11 C10 C9 E10 E9 B8 B7 C6 C5 A5 A6 E2 E1 F4 F3 G2 G1 H3 H4 J1 J2 K3 K4 L1 L2 M3 M4 N1 N2 CPU AC5 AC4 AE5 AE4 AG3 SNB_IPL_RCOMPAE2 AE1 24.9 OHM FDI_FSYNC_0 FDI_LSYNC_0 FDI_TX[0] FDI_INT AD7 AD6 AE7 AE8 AF3 AF2 AG2 AG1 FDI_TX[4] FDI_TX#[4] FDI_TX[5] FDI_TX#[5] FDI_TX[6] FDI_TX#[6] FDI_TX[7] FDI_TX#[7] FDI_LSYNC_1 FDI_FSYNC_1 FDI_COMPIO FDI_ICOMPO OF 11 AC8 AC7 AC2 AC3 AD2 AD1 AD4 AD3 FDI_TX[0] FDI_TX#[0] FDI_TX[1] FDI_TX#[1] FDI_TX[2] FDI_TX#[2] FDI_TX[3] FDI_TX#[3] FDI_TX_0_DP FDI_TX_0_DN FDI_TX_1_DP FDI_TX_1_DN FDI_TX_2_DP FDI_TX_2_DN FDI_TX_3_DP FDI_TX_3_DN 13 13 13 13 13 13 13 13 FDI_TX_4_DP FDI_TX_4_DN FDI_TX_5_DP FDI_TX_5_DN FDI_TX_6_DP FDI_TX_6_DN FDI_TX_7_DP FDI_TX_7_DN 13 13 13 13 13 13 13 13 FDI LINK W=10 Near PIN 250MIL SKT_H2 ? C CPU 11 11 11 11 11 11 11 11 Note PCIE X4 LANES ARE NOT SUPPORTED ON DESKTOP CPU SKUS 24.9 OHM GRCOMPB5 R2 C4 PEG_ICOMPO CPU SHORT B4 & C4 B4 PEG_RCOMPO PEG_ICOMPI TOGETHER, ROUTE AS A SINGLE MIL OF 11 SKT_H2 TRACE TO Rcomp, ROUTE B5 TO RCOMP AS A SEPERATE 10 MIL TRACE CPU ? B B A A GM Confidential Title H2-PCIE&FDI Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 M_DATA_B[0 63] M_DQS_B_DP[0 7] M_DQS_B_DN[0 7] ? SKT_H2 M_DATA_A[0 63] M_DQS_A_DP[0 7] M_DQS_A_Dn[0 7] D C ? AK3 AP3 AW4 AV8 AV37 AP38 AK38 AF38 M_DQS_A_DN0 M_DQS_A_DN1 M_DQS_A_DN2 M_DQS_A_DN3 M_DQS_A_DN4 M_DQS_A_DN5 M_DQS_A_DN6 M_DQS_A_DN7 AK2 AP2 AV4 AW8 AV36 AP39 AK39 AF39 M_MAA_A[0 15] CPU1A REV = BALLMAP_REV = 1.6 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_WE# SA_CAS# SA_RAS# SA_BS_0 SA_BS[1] SA_BS[2] SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] SA_CKE[0] SA_CKE[1] SA_CKE[3] SA_CKE[2] SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] SA_CK[0] SA_CK#[0] SA_CK[1] SA_CK#[1] SA_CK[2] SA_CK#[2] SA_CK[3] SA_CK#[3] SM_DRAMRST# AV27 AY24 AW24 AW23 AV23 AT24 AT23 AU22 AV22 AT22 AV28 AU21 AT21 AW32 AU20 AT20 M_MAA_A0 M_MAA_A1 M_MAA_A2 M_MAA_A3 M_MAA_A4 M_MAA_A5 M_MAA_A6 M_MAA_A7 M_MAA_A8 M_MAA_A9 M_MAA_A10 M_MAA_A11 M_MAA_A12 M_MAA_A13 M_MAA_A14 M_MAA_A15 AW29 AV30 AU28 DQ REMAPPING IMPLEMENTED TO IMPROVE BREAKOUT AND MINIMIZE CH-2-CH COUPLING M_WE_A_N M_CAS_A_N M_RAS_A_N 8 M_SBS_A[0 2] AY29 M_SBS_A0 AW28 M_SBS_A1 AV20 M_SBS_A2 M_SCS_A_N[0 3] AU29 M_SCS_A_N0 AV32 M_SCS_A_N1 AW30 M_SCS_A_N2 AU33 M_SCS_A_N3 M_SCKE_A[0 3] AV19 M_SCKE_A0 AT19 M_SCKE_A1 AU18 M_SCKE_A2 AV18 M_SCKE_A3 M_ODT_A[0 3] AV31 M_ODT_A0 AU32 M_ODT_A1 AU30 M_ODT_A2 AW33 M_ODT_A3 AY25 AW25 AU24 AU25 AW27 AY27 AV26 AW26 DQ REMAPPING IMPLEMENTED TO IMPROVE BREAKOUT AND MINIMIZE CH-2-CH COUPLING CK_M_DDR0_A_DP CK_M_DDR0_A_DN CK_M_DDR1_A_DP CK_M_DDR1_A_DN CK_M_DDR2_A_DP CK_M_DDR2_A_DN CK_M_DDR3_A_DP CK_M_DDR3_A_DN AW18 DDR3_DRAMRST_N_R6PR R3 B M_DQS_A_DP0 M_DQS_A_DP1 M_DQS_A_DP2 M_DQS_A_DP3 M_DQS_A_DP4 M_DQS_A_DP5 M_DQS_A_DP6 M_DQS_A_DP7 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] CPU1B M_MAA_B[0 15] REV = BALLMAP_REV = 1.6 SKT_H2 M_DATA_A0 AJ3 M_DATA_A1 AJ4 M_DATA_A2 AL3 M_DATA_A3 AL4 M_DATA_A4 AJ2 M_DATA_A5 AJ1 M_DATA_A6 AL2 M_DATA_A7 AL1 M_DATA_A8 AN1 M_DATA_A9 AN4 M_DATA_A10 AR3 M_DATA_A11 AR4 M_DATA_A12 AN2 M_DATA_A13 AN3 M_DATA_A14 AR2 M_DATA_A15 AR1 M_DATA_A16 AV2 M_DATA_A17 AW3 M_DATA_A18 AV5 M_DATA_A19 AW5 M_DATA_A20 AU2 M_DATA_A21 AU3 M_DATA_A22 AU5 M_DATA_A23 AY5 M_DATA_A24 AY7 M_DATA_A25 AU7 M_DATA_A26 AV9 M_DATA_A27 AU9 M_DATA_A28 AV7 M_DATA_A29 AW7 M_DATA_A30 AW9 M_DATA_A31 AY9 M_DATA_A32 AU35 M_DATA_A33AW37 M_DATA_A34 AU39 M_DATA_A35 AU36 M_DATA_A36AW35 M_DATA_A37 AY36 M_DATA_A38 AU38 M_DATA_A39 AU37 M_DATA_A40 AR40 M_DATA_A41 AR37 M_DATA_A42 AN38 M_DATA_A43 AN37 M_DATA_A44 AR39 M_DATA_A45 AR38 M_DATA_A46 AN39 M_DATA_A47 AN40 M_DATA_A48 AL40 M_DATA_A49 AL37 M_DATA_A50 AJ38 M_DATA_A51 AJ37 M_DATA_A52 AL39 M_DATA_A53 AL38 M_DATA_A54 AJ39 M_DATA_A55 AJ40 M_DATA_A56 AG40 M_DATA_A57 AG37 M_DATA_A58 AE38 M_DATA_A59 AE37 M_DATA_A60 AG39 M_DATA_A61 AG38 M_DATA_A62 AE39 M_DATA_A63 AE40 OHM C3 RC FILTER CPU DDR3_DRAMRST_N 8,9 NS 0.1UF/16V 0402 CPU SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_DQS[8] SA_DQS#[8] SA_ECC_CB[0] SA_ECC_CB[1] SA_ECC_CB[2] SA_ECC_CB[3] SA_ECC_CB[4] SA_ECC_CB[5] SA_ECC_CB[6] SA_ECC_CB[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] AV13 AV12 AU12 AU14 AW13 AY13 AU13 AU11 AY12 AW12 Design Note DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY M_DATA_B0 M_DATA_B1 M_DATA_B2 M_DATA_B3 M_DATA_B4 M_DATA_B5 M_DATA_B6 M_DATA_B7 M_DATA_B13 M_DATA_B9 M_DATA_B11 M_DATA_B15 M_DATA_B12 M_DATA_B8 M_DATA_B14 M_DATA_B10 M_DATA_B16 M_DATA_B17 M_DATA_B18 M_DATA_B19 M_DATA_B20 M_DATA_B21 M_DATA_B22 M_DATA_B23 M_DATA_B24 M_DATA_B25 M_DATA_B26 M_DATA_B27 M_DATA_B28 M_DATA_B29 M_DATA_B30 M_DATA_B31 M_DATA_B32 M_DATA_B33 M_DATA_B34 M_DATA_B35 M_DATA_B36 M_DATA_B37 M_DATA_B38 M_DATA_B39 M_DATA_B40 M_DATA_B41 M_DATA_B42 M_DATA_B43 M_DATA_B44 M_DATA_B45 M_DATA_B46 M_DATA_B47 M_DATA_B48 M_DATA_B52 M_DATA_B55 M_DATA_B51 M_DATA_B54 M_DATA_B49 M_DATA_B53 M_DATA_B50 M_DATA_B56 M_DATA_B57 M_DATA_B58 M_DATA_B59 M_DATA_B60 M_DATA_B61 M_DATA_B62 M_DATA_B63 AG7 AG8 AJ9 AJ8 AG5 AG6 AJ6 AJ7 AL7 AM7 AM10 AL10 AL6 AM6 AL9 AM9 AP7 AR7 AP10 AR10 AP6 AR6 AP9 AR9 AM12 AM13 AR13 AP13 AL12 AL13 AR12 AP12 AR28 AR29 AL28 AL29 AP28 AP29 AM28 AM29 AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34 AM32 AM31 AL35 AL32 AM34 AL31 AM35 AL34 AH35 AH34 AE34 AE35 AJ35 AJ34 AF33 AF35 M_DQS_B_DP0 M_DQS_B_DP1 M_DQS_B_DP2 M_DQS_B_DP3 M_DQS_B_DP4 M_DQS_B_DP5 M_DQS_B_DP6 M_DQS_B_DP7 AH7 AM8 AR8 AN13 AN29 AP33 AL33 AG35 M_DQS_B_DN0 M_DQS_B_DN1 M_DQS_B_DN2 M_DQS_B_DN3 M_DQS_B_DN4 M_DQS_B_DN5 M_DQS_B_DN6 M_DQS_B_DN7 AH6 AL8 AP8 AN12 AN28 AR33 AM33 AG34 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_WE# SB_CAS# SB_RAS# SB_BS[0] SB_BS[1] SB_BS[2] SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] SB_CKE[0] SB_CKE[1] SB_CKE[2] SB_CKE[3] SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] M_MAA_B0 M_MAA_B1 M_MAA_B2 M_MAA_B3 M_MAA_B4 M_MAA_B5 M_MAA_B6 M_MAA_B7 M_MAA_B8 M_MAA_B9 M_MAA_B10 M_MAA_B11 M_MAA_B12 M_MAA_B13 M_MAA_B14 M_MAA_B15 AR25 AK25 AP24 D M_WE_B_N M_CAS_B_N M_RAS_B_N AP23 M_SBS_B0 AM24 M_SBS_B1 AW17 M_SBS_B2 9 M_SBS_B[0 2] M_SCS_B_N[0 3] AN25 M_SCS_B_N0 AN26 M_SCS_B_N1 AL25 M_SCS_B_N2 AT26 M_SCS_B_N3 M_SCKE_B[0 3] AU16 M_SCKE_B0 AY15 M_SCKE_B1 AW15 M_SCKE_B2 AV15 M_SCKE_B3 AL26 M_ODT_B0 AP26 M_ODT_B1 AM26 M_ODT_B2 AK26 M_ODT_B3 SB_CK[0] C SB_CK[0] SB_CK#[0] SB_CK[1] SB_CK#[1] SB_CK[2] SB_CK#[2] SB_CK[3] SB_CK#[3] SB_DIMM_DQVREF SA_DIMM_DQVREF AL21 AL22 AL20 AK20 AL23 AM22 AP21 AN21 CK_M_DDR0_B_DP CK_M_DDR0_B_DN CK_M_DDR1_B_DP CK_M_DDR1_B_DN CK_M_DDR2_B_DP CK_M_DDR2_B_DN CK_M_DDR3_B_DP CK_M_DDR3_B_DN AH1 AH4 C2 9 9 C1 DIMM_DQ_CPU_VREF_A DIMM_DQ_CPU_VREF_B 0402 0.1UF/16V 0402 0.1UF/16V CPU CPU SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_DQS[8] SB_DQS#[8] SB_ECC_CB[0] SB_ECC_CB[1] SB_ECC_CB[2] SB_ECC_CB[3] SB_ECC_CB[4] SB_ECC_CB[5] SB_ECC_CB[6] SB_ECC_CB[7] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#7] DDR_A AK24 AM20 AM19 AK18 AP19 AP18 AM18 AL18 AN18 AY17 AN23 AU17 AT18 AR26 AY16 AV16 AN16 AN15 AL16 AM16 AP16 AR16 AL15 AM15 AR15 AP15 Design Note DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY DDR_B B OF 11 SKT_H2 ? OF 11 ? CPU SKT_H2 CPU A A GM Confidential Title H2-DRAM Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 VCC SKT_H2 REV = BALLMAP_REV = 1.6 13 CK_PE_100M_MCP_DP 13 CK_PE_100M_MCP_DN 12 H_PM_SYNC_0 12,23 H_PECI 0 OHM R18 27 H_PROCHOT_N 12 H_THERMTRIP_N V_SM 51 OHM 200 OHM H_DRAMPWRGD E38 J35 E37 H_CATERR_N H_PROCHOT_R_N H34 G35 H_SKTOCC_N H_SNB_N R23 100 OHM AJ33 K32 SNB_DDR_VREFAJ22 SNB_DDR_VREF C4 BCLK[0] BCLK#[0] VCCIO_SELECT VCCSA_VID_0 VCCSA_SENSE VIDSCLK VIDSOUT VIDALERT# VCC_SENSE VSS_SENSE VCCIO_SENSE VSSIO_SENSE UNCOREPWRGOOD SM_DRAMPWROK RESET# VCCAXG_SENSE VSSAXG_SENSE PM_SYNC PECI CATERR# PROCHOT# THERMTRIP# TDO TDI TCK TMS TRST# PRDY# PREQ# DBR# BCLK_ITP BCLK_ITP# ? SKTOCC# FC_K32 OF 11 SM_VREF P33 P34 T2 A36 B36 AB4 AB3 L32 M32 L39 L40 M40 L38 J39 K38 K40 E39 C40 D40 R5 10K OHM D VCCIO_SEL VCCSA_VID 24 VCCSA_SENSE 24 VCC_SENSE VSS_SENSE 27 27 R6 4.7K OHM VCCP_SENSE VSSP_SENSE VCCAXG_SENSE 27 VSSAXG_SENSE 27 H_TDO H_TDI H_TCK H_TMS H_TRST_N H_PRDY_N H_PREQ_N XDP_DBRESET_N R24 4 R4 1K OHM V_SM H_VIDSOUT H_VIDSCK H_PWRGD R607 H_VIDALERT_N H_PECI H_CATERR_N H_PROCHOT_R_N H_THERMTRIP_N H_TDO H_TDI H_TMS 51 OHM R7 R16 110 OHM 90.9 OHM 51 OHM NS 75 OHM 1K OHM NS 1K OHM NS 51 OHM 51 OHM NS 51 OHM 51 OHM 51 OHM H_TCK R21 Near CPU 1.5" H_TRST_N R22 22222222222 00000000000 44444444444 00000000000 R8 R9 R10 R11 R12 R13 R14 R15 R17 R19 R20 22 00 44 00 C37 H_VIDSCK H_VIDSOUT B37 44.2 OHM VIDALERT_N A37 100 OHM NS J40 12,21 H_PWRGD AJ19 12 H_DRAMPWRGD F36 21 PLTRST_CPU_N H_VIDALERT_N V_CPU_VCCIO W2 W1 D ? CPU1E FP_RST_N 12,22 SKT_H2 H_VIDSCK_VR R26 H_VIDSCK H_VIDSOUT_VR R27 H_VIDSOUT 27 H_VIDALERT_N_VR H_VIDALERT_N_VR R28 27 H_VIDSCK_VR 27 H_VIDSOUT_VR OHM OHM TPEV_SNB_PCUDEBUG_0 TPEV_SNB_PCUDEBUG_1 TPEV_SNB_PCUDEBUG_2 TPEV_SNB_PCUDEBUG_3 TPEV_SNB_PCUDEBUG_4 TPEV_SNB_PCUDEBUG_5 TPEV_SNB_PCUDEBUG_6 TPEV_SNB_PCUDEBUG_7 TPEV_SNB_PCUDEBUG_8 TPEV_SNB_PCUDEBUG_9 TPEV_SNB_PCUDEBUG_10 TPEV_SNB_PCUDEBUG_11 TPEV_SNB_PCUDEBUG_12 TPEV_SNB_PCUDEBUG_13 TPEV_SNB_PCUDEBUG_14 TPEV_SNB_PCUDEBUG_15 TPEV_SNB_PCUSTB_0 TPEV_SNB_PCUSTB_1 R25 0402 0.1UF/16V 100 OHM OHM H_VIDALERT_N C 3D3V_SB AT14 R29 AY3 V_1P8_SFR 4 1K/NC R30 12 H_SKTOCC_R_N H36 J36 J37 K36 L36 N35 L37 M36 J38 L35 M38 N36 N38 N39 N37 N40 G37 G36 H_SKTOCC_N H7 H8 H_SKTOCC_N 27 NS R31 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD1 RSVD12 RSVD13 RSVD2 RSVD14 RSVD15 RSVD16 RSVD3 RSVD4 RSVD17 10K/NC VCC_VALIDATION_SENSE VSSU_VALIDATION_SENSE Near PCH 100MIL R32 2.2K OHM VCCAXG_VALIDATION_SENSE VSSGT_VALIDATION_SENSE R33 222222222222222222 000000000000000000 444444444444444444 000000000000000000 B R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 C N33 M34 AV1 AW2 L9 J9 K9 L31 J31 K31 AD34 AD35 4.7K OHM 11 NVR_CLE C445 DMI/FDI TERMINATION VOLTAGE DC COUPLED: TX/RX0402 TO VCC ISF SAMPLED HIGH DC COUPLED: TX/RX TO VSS IF SAMPLED LOW 0.1UF/16V AC COUPLED: TX SET TO VCC/2, RX SET TO VSS REGARDLESS OF THIS STRAP TPEV_SNB_PCUDEBUG_0 TPEV_SNB_PCUDEBUG_1 TPEV_SNB_PCUDEBUG_2 TPEV_SNB_PCUDEBUG_3 TPEV_SNB_PCUDEBUG_4 TPEV_SNB_PCUDEBUG_5 TPEV_SNB_PCUDEBUG_6 TPEV_SNB_PCUDEBUG_7 TPEV_SNB_PCUDEBUG_8 TPEV_SNB_PCUDEBUG_9 TPEV_SNB_PCUDEBUG_10 TPEV_SNB_PCUDEBUG_11 TPEV_SNB_PCUDEBUG_12 TPEV_SNB_PCUDEBUG_13 TPEV_SNB_PCUDEBUG_14 TPEV_SNB_PCUDEBUG_15 TPEV_SNB_PCUSTB_0 TPEV_SNB_PCUSTB_1 B39 J33 L34 L33 K34 H_SNB_N H40 H38 G38 G40 G39 F38 E40 F40 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM 1K OHM NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS MISC SNB STRAP TABLE CFG H RESERVED RESERVED NORM RESERVED RESERVED * * RESERVED RESERVED RESERVED 10 RESERVED 11 RESERVED 12 RESERVED 13 RESERVED 14 RESERVED 15 RESERVED L RESERVED RESERVED REVERSE RESERVED RESERVED * * RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED DESCRIPTION RESERVED RESERVED PEGLANE REVERSAL[0],X16 RESERVED RESERVED PEOFGSEL[0] PEOFGSEL[1] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED B PLACE AS NEAR AS POSSIBLE TO SNB PEG CONFIG TABLE SEL1 SEL0 1 PCIE CONFIG 1X16 (Default) 2X8 A A GM Confidential Title H2-MISC Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 ? VCCP SKT_H2 CPU1F VCCP ? SKT_H2 CPU1G REV = REV = V_AXG A12 A13 A14 A15 A16 A18 A24 A25 A27 A28 B15 B16 B18 B24 B25 B27 B28 B30 B31 B33 B34 C15 C16 C18 C19 C21 C22 C24 C25 C27 C28 C30 C31 C33 C34 C36 D13 D14 D15 D16 D18 D19 D21 D22 D24 D25 D27 D28 D30 D31 D33 D34 D35 D36 E15 E16 E18 E19 E21 E22 E24 E25 E27 E28 E30 E31 E33 E34 E35 F15 F16 F18 F19 F21 F22 F24 F25 F27 F28 F30 F31 D C BALLMAP_REV = 1.6 VCC1 VCC82 VCC2 VCC83 VCC3 VCC84 VCC4 VCC85 VCC5 VCC86 VCC6 VCC87 VCC7 VCC88 VCC8 VCC89 VCC9 VCC90 VCC10 VCC91 VCC11 VCC92 VCC12 VCC93 VCC13 SKT_H2 VCC94 VCC14 VCC95 VCC15 VCC96 VCC16 VCC97 VCC17 VCC98 VCC18 VCC99 VCC19 VCC100 VCC20 VCC101 VCC21 VCC102 VCC22 VCC103 VCC23 OF 11 VCC104 VCC24 VCC105 ? VCC25 VCC106 VCC26 VCC107 VCC27 VCC108 VCC28 VCC109 VCC29 VCC110 VCC30 VCC111 VCC31 VCC112 VCC32 VCC113 VCC33 VCC114 VCC34 VCC115 VCC35 VCC116 VCC36 VCC117 VCC37 VCC118 VCC38 VCC119 VCC39 VCC120 VCC40 VCC121 VCC41 VCC122 VCC42 VCC123 VCC43 VCC124 VCC44 VCC125 VCC45 VCC126 VCC46 VCC127 VCC47 VCC128 VCC48 VCC129 VCC49 VCC130 VCC50 VCC131 VCC51 VCC132 VCC52 VCC133 VCC53 VCC134 VCC54 VCC135 VCC55 VCC136 VCC56 VCC137 VCC57 VCC138 VCC58 VCC139 VCC59 VCC140 VCC60 VCC141 VCC61 VCC142 VCC62 VCC143 VCC63 VCC144 VCC64 VCC145 VCC65 VCC146 VCC66 VCC147 VCC67 VCC148 VCC68 VCC149 VCC69 VCC150 VCC70 VCC151 VCC71 VCC152 VCC72 VCC153 VCC73 VCC154 VCC74 VCC155 VCC75 VCC156 VCC76 VCC157 VCC77 VCC158 VCC78 VCC159 VCC79 VCC160 VCC80 VCC161 VCC81 F32 F33 F34 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G32 G33 H13 H14 H15 H16 H18 H19 H21 H22 H24 H25 H27 H28 H30 H31 H32 J12 J15 J16 J18 J19 J21 J22 J24 J25 J27 J28 J30 K15 K16 K18 K19 K21 K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18 M19 M21 M22 M24 M25 M27 M28 M30 BALLMAP_REV = 1.6 AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB40 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40 T33 T34 T35 T36 T37 T38 T39 T40 U33 U34 U35 U36 U37 U38 U39 U40 W33 W34 W35 W36 W37 W38 Y33 Y34 Y35 Y36 Y37 Y38 VCCAXG1 VCCAXG2 VCCAXG3 VCCAXG4 VCCAXG5 VCCAXG6 VCCAXG7 VCCAXG8 VCCAXG9 VCCAXG10 VCCAXG11 VCCAXG12 VCCAXG13 VCCAXG14 VCCAXG15 VCCAXG16 VCCAXG17 VCCAXG18 VCCAXG19 OF 11 VCCAXG20 VCCAXG21 VCCAXG22 VCCAXG23 VCCAXG24 VCCAXG25 SKT_H2 VCCAXG26 VCCAXG27 VCCAXG28 VCCAXG29 VCCAXG30 VCCAXG31 VCCAXG32 VCCAXG33 VCCAXG34 VCCAXG35 VCCAXG36 VCCAXG37 VCCAXG38 VCCAXG39 VCCAXG40 VCCAXG41 VCCAXG42 VCCAXG43 VCCAXG44 ? CPU1H V_CPU_VCCIO A11 A7 AA3 AB8 AF8 AG33 AJ16 AJ17 AJ26 AJ28 AJ32 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK30 B9 D10 D6 E3 E4 G3 G4 J3 J4 J7 J8 L3 L4 L7 N3 N4 N7 R3 R4 R7 U3 U4 U7 V8 W3 ? GFX POWER V_SA H10 H11 H12 J10 K10 K11 L11 L12 M10 M11 M12 AK11 AK12 V_1P8_SFR SKT_H2 REV = BALLMAP_REV = 1.6 M13 V_SM VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO188 OF 11 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 SKT_H2 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 ? VDDQ23 AJ13 AJ14 AJ23 AJ24 AR20 AR21 AR22 AR23 AR24 AU19 AU23 AU27 AU31 AV21 AV24 AV25 AV29 AV33 AW31 AY23 AY26 AY28 D AJ20 C VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCPLL1 VCCPLL2 IO/SA/PLL POWER CPU POWER B B PLACE ALL 0805 CAPS INSIDE BACKSIDE VCCP V_1P8_SFR VCCP V_SA V_AXG C435 C7 C8 C9 C10 C11 CPU CAVITY CAPS C12 C432 0805 0805 0805 0805 0805 0805 0805 22UF/6.3V 0805 C17 22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V 0805 C18 0805 C19 C20 0805 0805 C21 0805 C429 22UF/6.3V 0805 22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V 22UF/6.3V VCCP C22 0805 C23 0805 C24 0805 C25 0805 C26 0805 C27 0805 C28 0805 C29 V_AXG 0805 22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V22UF/6.3V CPU CAVITY CAPS BACKSIDE VCCP V_SM C431 0805 22UF/6.3V C32 C33 C34 C35 C36 A 0805 0805 0805 22UF/6.3V22UF/6.3V 0805 A NS 0805 22UF/6.3V22UF/6.3V22UF/6.3V PLACE ALL 0805 CAPS INSIDE CPU SOCKET CAVITY GM Confidential Title H2-POWER Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 D C B ? CPU1I SKT_H2 A17 REV = A23 VSS1 BALLMAP_REV = 1.6 A26 VSS2 A29 VSS3 A35 VSS4 AA33 VSS5 AA34 VSS6 AA35 VSS7 AA36 VSS8 AA37 VSS9 AA38 VSS10 AA6 VSS11 AB5 VSS12 AC1 VSS13 AC6 VSS14 AD33 VSS15 AD36 VSS16 AD38 VSS17 AD39 VSS18 AD40 VSS19 AD5 VSS20 AD8 VSS21 AE3 VSS22 AE33 VSS23 VSS24 AE36 OF 11 AF1 VSS25 AF34 VSS26 VSS27 AF36 SKT_H2 AF37 VSS28 AF40 VSS29 AF5 VSS30 AF6 VSS31 AF7 VSS32 AG36 VSS33 AH2 VSS34 AH3 VSS35 AH33 VSS36 AH36 VSS37 AH37 VSS38 AH38 VSS39 AH39 VSS40 AH40 VSS41 AH5 VSS42 AH8 VSS43 AJ12 VSS44 AJ15 VSS45 AJ18 VSS46 AJ21 VSS47 AJ25 VSS48 AJ27 VSS49 AJ36 VSS50 AJ5 VSS51 AK1 VSS52 AK10 VSS53 AK13 VSS_AK10 AK14 VSS54 AK16 VSS55 AK22 VSS56 AK28 VSS57 AK31 VSS58 AK32 VSS59 AK33 VSS60 AK34 VSS61 AK35 VSS62 AK36 VSS63 AK37 VSS64 AK4 VSS65 AK40 VSS66 AK5 VSS67 AK6 VSS68 AK7 VSS69 AK8 VSS70 AK9 VSS71 AL11 VSS72 AL14 VSS73 AL17 VSS74 AL19 VSS75 AL24 VSS76 AL27 VSS77 AL30 VSS78 AL36 VSS79 AL5 VSS80 AM1 VSS81 AM11 VSS82 AM14 VSS83 AM17 VSS84 AM2 VSS85 AM21 VSS86 AM23 VSS87 AM25 VSS88 A4 VSS89 AV39 VSS_NCTF1 VSS_NCTF2 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 ? VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 AM27 AM3 AM30 AM36 AM37 AM38 AM39 AM4 AM40 AM5 AN10 AN11 AN14 AN17 AN19 AN22 AN24 AN27 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN5 AN6 AN7 AN8 AN9 AP1 AP11 AP14 AP17 AP22 AP25 AP27 AP30 AP36 AP37 AP4 AP40 AP5 AR11 AR14 AR17 AR18 AR19 AR27 AR30 AR36 AR5 AT1 AT10 AT12 AT13 AT15 AT16 AT17 AT2 AT25 AT27 AT28 AT29 AT3 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT4 AT40 AT5 AT6 AT7 AT8 AT9 AU1 AU15 AU26 AU34 AU4 AU6 AU8 AV10 ? CPU1K ? SKT_H2 AV11 AV14 AV17 AV3 AV35 AV38 AV6 AW10 AW11 AW14 AW16 AW36 AW6 AY11 AY14 AY18 AY35 AY4 AY6 AY8 B10 B13 B14 B17 B23 B26 B29 B32 B35 B38 B6 C11 C12 C17 C20 C23 C26 C29 C32 C35 C7 C8 D17 D2 D20 D23 D26 D29 D32 D37 D39 D4 D5 D9 E11 E12 E17 E20 E23 E26 E29 E32 E36 E7 E8 F1 F10 F13 F14 F17 F2 F20 F23 F26 F29 F35 F37 F39 F5 F6 F9 G11 G12 G17 G20 G23 G26 G29 G34 G7 AY37 B3 CPU1J REV = AB7 AD37 AG4 AJ29 AJ30 AJ31 AV34 AW34 P35 P37 P39 R34 R36 R38 R40 A38 AU40 10 OF 11 AW38 C2 SKT_H2 D1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 BALLMAP_REV = 1.6 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD21 RSVD22 RSVD23 RSVD24 NCTF1 NCTF2 NCTF3 NCTF4 NCTF5 RSVD25 RSVD26 RSVD27 ? RSVD28 RSVD29 AT11 AP20 AN20 AU10 AY10 AF4 AB6 AE6 AJ11 D38 C39 C38 J34 N34 SPARES VSS1 VSS91 REV = VSS2 VSS92 VSS3 BALLMAP_REV = 1.6VSS93 VSS4 VSS94 VSS5 VSS95 VSS6 VSS96 VSS7 VSS97 VSS8 VSS98 VSS9 VSS99 VSS10 VSS100 VSS11 VSS101 VSS12 VSS102 VSS13 VSS103 VSS14 VSS104 VSS15 VSS105 VSS16 VSS106 VSS17 VSS107 VSS18 VSS108 VSS19 VSS109 VSS20 VSS110 VSS21 VSS111 VSS22 OF 11 VSS112 VSS23 VSS113 VSS24 VSS114 VSS25 VSS115 VSS26 VSS116 ? VSS27 SKT_H2 VSS117 VSS28 VSS118 VSS29 VSS119 VSS30 VSS120 VSS31 VSS121 VSS32 VSS122 VSS33 VSS123 VSS34 VSS124 VSS35 VSS125 VSS36 VSS126 VSS37 VSS127 VSS38 VSS128 VSS39 VSS129 VSS40 VSS130 VSS41 VSS131 VSS42 VSS132 VSS43 VSS133 VSS44 VSS134 VSS45 VSS135 VSS46 VSS136 VSS47 VSS137 VSS48 VSS138 VSS49 VSS139 VSS50 VSS140 VSS51 VSS141 VSS52 VSS142 VSS53 VSS143 VSS54 VSS144 VSS55 VSS145 VSS56 VSS146 VSS57 VSS147 VSS58 VSS148 VSS59 VSS149 VSS60 VSS150 VSS61 VSS151 VSS62 VSS152 VSS63 VSS153 VSS64 VSS154 VSS65 VSS155 VSS66 VSS156 VSS67 VSS157 VSS68 VSS158 VSS69 VSS159 VSS70 VSS160 VSS71 VSS161 VSS72 VSS162 VSS73 VSS163 VSS74 VSS164 VSS75 VSS165 VSS76 VSS166 VSS77 VSS167 VSS78 VSS168 VSS79 VSS169 VSS80 VSS170 VSS81 VSS171 VSS82 VSS172 VSS83 VSS173 VSS84 VSS174 VSS85 VSS175 VSS86 VSS176 VSS87 VSS177 VSS88 VSS178 VSS89 VSS179 VSS90 VSS180 VSS_NCTF1 VSS_NCTF2 G8 H1 H17 H2 H20 H23 H26 H29 H33 H35 H37 H39 H5 H6 H9 J11 J17 J20 J23 J26 J29 J32 K1 K12 K13 K14 K17 K2 K20 K23 K26 K29 K33 K35 K37 K39 K5 K6 L10 L17 L20 L23 L26 L29 L8 M1 M17 M2 M20 M23 M26 M29 M33 M35 M37 M39 M5 M6 M9 N8 P1 P2 P36 P38 P40 P5 P6 R33 R35 R37 R39 R8 T1 T5 T6 U8 V1 V2 V33 V34 V35 V36 V37 V38 V39 V40 V5 W6 Y5 Y8 D C B A A GM Confidential Title H2-GND\ Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 DIMM1 V_SM 197 194 191 189 186 183 182 179 176 173 170 78 75 72 69 66 65 62 60 57 54 51 PLACE BETWEEN CHA &CHB DO NOT PUNCH VIA C51 0402 C52 0402 0.1UF/16V 0.1UF/16V NS NS B 236 VCC3 DIMM_CA_VREF_A DIMM_DQ_VREF_A 9,10,12,16 SMB_CLK_MAIN 9,10,12,16 SMB_DATA_MAIN M_SBS_A[0 2] 4 4 67 118 238 237 117 M_SBS_A2 M_SBS_A1 M_SBS_A0 52 190 71 M_SCKE_A1 M_SCKE_A0 169 50 M_SCS_A_N1 M_SCS_A_N0 76 193 64 63 185 184 CK_M_DDR1_A_DN CK_M_DDR1_A_DP CK_M_DDR0_A_DN CK_M_DDR0_A_DP M_MAA_A0 M_MAA_A1 M_MAA_A2 M_MAA_A3 M_MAA_A4 M_MAA_A5 M_MAA_A6 M_MAA_A7 M_MAA_A8 M_MAA_A9 M_MAA_A10 M_MAA_A11 M_MAA_A12 M_MAA_A13 M_MAA_A14 M_MAA_A15 A 188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171 168 74 192 73 4,9 DDR3_DRAMRST_N M_CAS_A_N M_RAS_A_N M_WE_A_N VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDSPD VREFCA VREFDQ SCL SDA SA1 SA0 BA2 BA1 BA0 CKE1 CKE0 S1* S0* CK1/NU* CK1/NU CK0* CK0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 RESET* CAS# RAS# WE# CB CB CB CB CB CB CB CB M_ODT_A1 M_ODT_A0 M_MAA_A[0 15] 68 53 167 M_MAA_A[0 15] M_SCS_A_N[0 3] M_SCKE_A[0 3] M_ODT_A[0 3] M_DATA_A[0 63] M_DQS_A_DP[0 7] M_DQS_A_DN[0 7] 39 40 45 46 158 159 164 165 D V_SM C37 0402 DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DM0/DQS9 NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ M_DQS_A_DP0 M_DQS_A_DN0 16 15 M_DQS_A_DP1 M_DQS_A_DN1 25 24 M_DQS_A_DP2 M_DQS_A_DN2 34 33 M_DQS_A_DP3 M_DQS_A_DN3 85 84 M_DQS_A_DP4 M_DQS_A_DN4 94 93 M_DQS_A_DP5 M_DQS_A_DN5 103 102 M_DQS_A_DP6 M_DQS_A_DN6 0.1UF/16V C38 0402 0.1UF/16V C39 0402 112 111 R53 1K OHM V_SM 0.1UF/16V M_DQS_A_DP7 M_DQS_A_DN7 R54 1K OHM DIMM_DQ_VREF_A R55 C40 C41 NS 43 42 DIMM_DQ_CPU_VREF_A NS 0402 R56 0402 1K OHM0.1UF/16V0.1UF/16V 125 126 C 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234 M_DATA_A0 M_DATA_A1 M_DATA_A2 M_DATA_A3 M_DATA_A4 M_DATA_A5 M_DATA_A6 M_DATA_A7 M_DATA_A8 M_DATA_A9 M_DATA_A10 M_DATA_A11 M_DATA_A12 M_DATA_A13 M_DATA_A14 M_DATA_A15 M_DATA_A16 M_DATA_A17 M_DATA_A18 M_DATA_A19 M_DATA_A20 M_DATA_A21 M_DATA_A22 M_DATA_A23 M_DATA_A24 M_DATA_A25 M_DATA_A26 M_DATA_A27 M_DATA_A28 M_DATA_A29 M_DATA_A30 M_DATA_A31 M_DATA_A32 M_DATA_A33 M_DATA_A34 M_DATA_A35 M_DATA_A36 M_DATA_A37 M_DATA_A38 M_DATA_A39 M_DATA_A40 M_DATA_A41 M_DATA_A42 M_DATA_A43 M_DATA_A44 M_DATA_A45 M_DATA_A46 M_DATA_A47 M_DATA_A48 M_DATA_A49 M_DATA_A50 M_DATA_A51 M_DATA_A52 M_DATA_A53 M_DATA_A54 M_DATA_A55 M_DATA_A56 M_DATA_A57 M_DATA_A58 M_DATA_A59 M_DATA_A60 M_DATA_A61 M_DATA_A62 M_DATA_A63 B A GM Confidential Title DDR3-A DDR3 R52 1K OHM DIMM_CA_VREF_A C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SA2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC/PAR_IN NC/ERR_OUT NC/TEST4 79 77 195 D 239 235 232 229 226 223 220 217 214 211 208 205 202 199 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 119 116 113 110 107 104 101 98 95 92 89 86 83 80 47 44 41 38 35 32 29 26 23 20 17 14 11 VTT VTT RSVD ODT1 ODT0 240 120 FREE1 FREE2 FREE3 FREE4 198 187 49 48 V_SM_VTT Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 DIMM3 V_SM 197 194 191 189 186 183 182 179 176 173 170 78 75 72 69 66 65 62 60 57 54 51 B 236 VCC3 DIMM_CA_VREF_B DIMM_DQ_VREF_B 8,10,12,16 SMB_CLK_MAIN 8,10,12,16 SMB_DATA_MAIN VCC3 M_SBS_B[0 2] 4 4 67 118 238 237 117 M_SBS_B2 M_SBS_B1 M_SBS_B0 52 190 71 M_SCKE_B1 M_SCKE_B0 169 50 M_SCS_B_N1 M_SCS_B_N0 76 193 64 63 185 184 CK_M_DDR1_B_DN CK_M_DDR1_B_DP CK_M_DDR0_B_DN CK_M_DDR0_B_DP M_MAA_B0 M_MAA_B1 M_MAA_B2 M_MAA_B3 M_MAA_B4 M_MAA_B5 M_MAA_B6 M_MAA_B7 M_MAA_B8 M_MAA_B9 M_MAA_B10 M_MAA_B11 M_MAA_B12 M_MAA_B13 M_MAA_B14 M_MAA_B15 A 188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171 168 74 192 73 4,8 DDR3_DRAMRST_N M_CAS_B_N M_RAS_B_N M_WE_B_N VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDSPD VREFCA VREFDQ SCL SDA SA1 SA0 BA2 BA1 BA0 CKE1 CKE0 S1* S0* CK1/NU* CK1/NU CK0* CK0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 RESET* CAS# RAS# WE# CB CB CB CB CB CB CB CB M_ODT_B1 M_ODT_B0 M_MAA_B[0 15] M_SCS_B_N[0 3] M_SCKE_B[0 3] M_ODT_B[0 3] 68 53 167 M_DATA_B[0 63] M_DQS_B_DP[0 7] M_DQS_B_DN[0 7] 39 40 45 46 158 159 164 165 D V_SM C58 0402 DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DQS DQS# DM0/DQS9 NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ M_DQS_B_DP0 M_DQS_B_DN0 16 15 M_DQS_B_DP1 M_DQS_B_DN1 25 24 M_DQS_B_DP2 M_DQS_B_DN2 34 33 M_DQS_B_DP3 M_DQS_B_DN3 85 84 M_DQS_B_DP4 M_DQS_B_DN4 94 93 M_DQS_B_DP5 M_DQS_B_DN5 103 102 M_DQS_B_DP6 M_DQS_B_DN6 0.1UF/16V C59 0402 0.1UF/16V C64 0402 112 111 R58 1K OHM V_SM 0.1UF/16V M_DQS_B_DP7 M_DQS_B_DN7 R59 1K OHM DIMM_DQ_VREF_B R60 C70 C71 NS 43 42 DIMM_DQ_CPU_VREF_B NS 0402 R61 0402 1K OHM0.1UF/16V0.1UF/16V 125 126 C 134 135 143 144 152 153 203 204 212 213 V_SM_VTT 221 222 C77 230 231 0805 C80 C48 0402 0402 4.7UF/10V0.1UF/16V 0.1UF/16V 161 162 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234 M_DATA_B0 M_DATA_B1 M_DATA_B2 M_DATA_B3 M_DATA_B4 M_DATA_B5 M_DATA_B6 M_DATA_B7 M_DATA_B8 M_DATA_B9 M_DATA_B10 M_DATA_B11 M_DATA_B12 M_DATA_B13 M_DATA_B14 M_DATA_B15 M_DATA_B16 M_DATA_B17 M_DATA_B18 M_DATA_B19 M_DATA_B20 M_DATA_B21 M_DATA_B22 M_DATA_B23 M_DATA_B24 M_DATA_B25 M_DATA_B26 M_DATA_B27 M_DATA_B28 M_DATA_B29 M_DATA_B30 M_DATA_B31 M_DATA_B32 M_DATA_B33 M_DATA_B34 M_DATA_B35 M_DATA_B36 M_DATA_B37 M_DATA_B38 M_DATA_B39 M_DATA_B40 M_DATA_B41 M_DATA_B42 M_DATA_B43 M_DATA_B44 M_DATA_B45 M_DATA_B46 M_DATA_B47 M_DATA_B48 M_DATA_B49 M_DATA_B50 M_DATA_B51 M_DATA_B52 M_DATA_B53 M_DATA_B54 M_DATA_B55 M_DATA_B56 M_DATA_B57 M_DATA_B58 M_DATA_B59 M_DATA_B60 M_DATA_B61 M_DATA_B62 M_DATA_B63 V_SM C85 0805 C86 C87 0805 C88 0805 0805 B 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V STICHING CAPS FOR CMD, ADDR, CTL V_SM C90 0402 C91 0402 C92 0402 C93 0402 0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/6.3V V_SM C94 0402 C95 0402 C96 0402 C97 0402 0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/6.3V A GM Confidential Title DDR3-B DDR3 R57 1K OHM DIMM_CA_VREF_B C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SA2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC/PAR_IN NC/ERR_OUT NC/TEST4 79 77 195 D 239 235 232 229 226 223 220 217 214 211 208 205 202 199 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 119 116 113 110 107 104 101 98 95 92 89 86 83 80 47 44 41 38 35 32 29 26 23 20 17 14 11 VTT VTT RSVD ODT1 ODT0 240 120 FREE1 FREE2 FREE3 FREE4 198 187 49 48 V_SM_VTT Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 1.0 of 30 3D3V_SB VCC3 +12V +12V VCC3 PCIEX1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 D 8,9,12,16 SMB_CLK_MAIN 8,9,12,16 SMB_DATA_MAIN 12,16,19 WAKE_N 12V_1(P) 12V_2(P) 12V_3(P) GND_1(P) SMCLK(B) SMDAT(B) GND_2(P) 3_3V_1(P) JTAG1(B) 3_3VAUX(I) WAKE*(B) PRSNT1#(B) 12V_4(P) 12V_5(P) GND_3(P) JTAG2(B) JTAG3(B) JTAG4(B) JTAG5(B) 3_3V_2(P) 3_3V_3(P) PERST# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D PLTRST_PCIE_SLOTS_N 16,19,21 KEY B12 B13 B14 B15 B16 B17 B18 All AC Coupling caps should be placed within 250 mils of the connector EXP_A_TX_2_DP EXP_A_TX_2_DN EXP_A_TX_3_DP EXP_A_TX_3_DN C108 C109 C110 C111 04020402 04020402 C106 C107 0.1UF/16V 0.1UF/16V 04020402 EXP_A_TX_1_DP EXP_A_TX_1_DN C104 C105 04020402 EXP_A_TX_0_DP EXP_A_TX_0_DN B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V RSVD_1(B) GND_4(P) HSOP0(I) HSON0(I) GND_5(P) PRSNT2#_1(I) GND_6(P) GND_7(P) REFCLK+(I) REFCLK-(I) GND_8(P) HSIP0(O) HSIN0(O) GND_9(P) HSOP1(I) HSON1(I) GND_10(P) GND_11(P) HSOP2(I) HSON2(I) GND_12(P) GND_13(P) HSOP3(I) HSON3(I) GND_14(P) RSVD_2(B) PRSNT2#_2(I) GND_15(P) RSVD_3(B) GND_16(P) HSIP1(O) HSIN1(O) GND_17(P) GND_18(P) HSIP2(O) HSIN2(O) GND_19(P) GND_20(P) HSIP3(O) HSIN3(O) GND_21(P) RSVD_4(B) A12 A13 A14 A15 A16 A17 A18 CK_PE_16PORT_PCH_DP 13 CK_PE_16PORT_PCH_DN 13 EXP_A_RX_0_DP EXP_A_RX_0_DN A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 EXP_A_RX_1_DP EXP_A_RX_1_DN EXP_A_RX_2_DP EXP_A_RX_2_DN +12V EXP_A_RX_3_DP EXP_A_RX_3_DN EC1 + EC2 + 8*12 8*12 470UF/16V 470UF/16V C EXP_A_TX_10_DP EXP_A_TX_10_DN EXP_A_TX_11_DP EXP_A_TX_11_DN EXP_A_TX_12_DP EXP_A_TX_12_DN B EXP_A_TX_13_DP EXP_A_TX_13_DN EXP_A_TX_14_DP EXP_A_TX_14_DN EXP_A_TX_15_DP EXP_A_TX_15_DN C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 04020402 04020402 04020402 04020402 04020402 C125 C126 04020402 EXP_A_TX_9_DP EXP_A_TX_9_DN C123 C124 04020402 EXP_A_TX_8_DP EXP_A_TX_8_DN C121 C122 04020402 EXP_A_TX_7_DP EXP_A_TX_7_DN C116 C117 04020402 EXP_A_TX_6_DP EXP_A_TX_6_DN C114 C115 04020402 EXP_A_TX_5_DP EXP_A_TX_5_DN C112 C113 04020402 EXP_A_TX_4_DP EXP_A_TX_4_DN 04020402 C B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V All AC Coupling caps should be placed within 250 mils of the connector HSOP4(I) HSON4(I) GND_22(P) GND_23(P) HSOP5(I) HSON5(I) GND_24(P) GND_25(P) HSOP6(I) HSON6(I) GND_26(P) GND_27(P) HSOP7(I) HSON7(I) GND_28(P) PRSNT2#_3(B) GND_29(P) RSVD_5(B) GND_30(P) HSIP4(O) HSIN4(O) GND_31(P) GND_32(P) HSIP5(O) HSIN5(O) GND_33(P) GND_34(P) HSIP6(O) HSIN6(O) GND_35(P) GND_36(P) HSIP7(O) HSIN7(O) GND_37(P) HSOP8(I) HSON8(I) GND_38(P) GND_39(P) HSOP9(I) HSON9(I) GND_40(P) GND_41(P) HSOP10(I) HSON10(I) GND_42(P) GND_43(P) HSOP11(I) HSON11(I) GND_44(P) GND_45(P) HSOP12(I) HSON12(I) GND_46(P) GND_47(P) HSOP13(I) HSON13(I) GND_48(P) GND_49(P) HSOP14(I) HSON14(I) GND_50(P) GND_51(P) HSOP15(I) HSON15(I) GND_52(P) PRSNT2#_4(I) RSVD_6(I) RSVD_7(B) GND_53(P) HSIP8(O) HSIN8(O) GND_54(P) GND_55(P) HSIP9(O) HSIN9(O) GND_56(P) GND_57(P) HSIP10(O) HSIN10(O) GND_58(P) GND_59(P) HSIP11(O) HSIN11(O) GND_60(P) GND_61(P) HSIP12(O) HSIN12(O) GND_62(P) GND_63(P) HSIP13(O) HSIN13(O) GND_64(P) GND_65(P) HSIP14(O) HSIN14(O) GND_66(P) GND_67(P) HSIP15(O) HSIN15(O) GND_68(P) A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 EXP_A_RX_4_DP EXP_A_RX_4_DN VCC3 +12V 3D3V_SB EXP_A_RX_5_DP EXP_A_RX_5_DN 0402 EXP_A_RX_6_DP EXP_A_RX_6_DN C118 0.1UF/25V 0402 C119 0.1UF/25V 0402 C120 0.1UF/25V EXP_A_RX_7_DP EXP_A_RX_7_DN A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 EXP_A_RX_8_DP EXP_A_RX_8_DN EXP_A_RX_9_DP EXP_A_RX_9_DN EXP_A_RX_10_DP EXP_A_RX_10_DN EXP_A_RX_11_DP EXP_A_RX_11_DN B EXP_A_RX_12_DP EXP_A_RX_12_DN EXP_A_RX_13_DP EXP_A_RX_13_DN EXP_A_RX_14_DP EXP_A_RX_14_DN EXP_A_RX_15_DP EXP_A_RX_15_DN PCIE164 A A GM Confidential Title PICE16X Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 10 1.0 of 30 CPT_CRB ? PCH1A D D ? 12 12 P_GNT_N0 P_GNT_N1 C BK10 BJ5 BM15 BP5 BN9 AV9 BT15 BR4 REQ0# REQ1#_GPIO50 REQ2#_GPIO52 REQ3#_GPIO54 PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#_GPIO2 PIRQF#_GPIO3 PIRQG#_GPIO4 PIRQH#_GPIO5 R63 R64 16 16 16 16 16 16 16 16 BN4 BP7 BG2 BP13 C_BE0# C_BE1# C_BE2# C_BE3# ? R71 OC0#_GPIO59 OC1#_GPIO40 OC2#_GPIO41 OC3#_GPIO42 OC4#_GPIO43 OC5#_GPIO9 OC6#_GPIO10 OC7#_GPIO14 18 18 18 18 18 18 18 18 19 19 19 19 USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P M48 R47 Y41 M50 M49 U43 J57 NVR_CLE CPT_CRB RESERVED_29 REV 1.0 DF_TVS RESERVED_6 RESERVED_4 RESERVED_3 RESERVED_2 RESERVED_1 BM43 USB_OC0_R_N BD41 USB_OC1_R_N BG41 USB_OC2_R_N BK43 USB_OC3_R_N BP43 USB_OC4_R_N BJ41 USB_OC5_R_N BT45 USB_OC6_R_N BM45 USB_OC7_R_N USBRBIAS# USBRBIAS CPT_CRB OF 10 CLKIN_DOT_96N CLKIN_DOT_96P ? DMI2RBIAS BD38 BF38 CK_96M_DREF_DN R66 CK_96M_DREF_DPR67 A32 RBIAS_CPY R68 K50 K49 AB46 G56 R50 RESERVED_5 10K OHM 10K OHM C Y44 L53 RESERVED_24 RESERVED_23 OF 10 NVRAM CPT_CRB 750 OHM ? USB_OC2_R_N USB_OC1_R_N USB_OC3_R_N USB_OC5_R_N USB_OC6_R_N USB_OC7_R_N USB_OC0_R_N USB_OC4_R_N 1K OHM NS AB50 Y50 AB49 AB44 U49 R44 U50 U46 U44 H50 K46 L56 J55 F53 H52 E52 RESERVED_22 RESERVED_21 RESERVED_14 RESERVED_13 RESERVED_12 RESERVED_11 RESERVED_10 RESERVED_9 RESERVED_8 RESERVED_7 RESERVED_20 RESERVED_19 RESERVED_18 RESERVED_17 RESERVED_16 RESERVED_15 RESERVED_28 RESERVED_27 RESERVED_26 RESERVED_25 For USB OC# Detect connect to USB power divider W4 Near PIN 500MIL BP25 USBRBIAS_PCHR65 22.6 BM25 3D3V_SB RN12 410K 0402 RN22 410K 0402 0402 0402 0402 0402 3D3V_SB 0402 0402 For USB OC# Detect connect to USB power divider R80 ? PCH1E P_GNT_N3 PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P 4 A16 SWAP OVERRIDE IF SAMPLED LOW P_GNT_N2 1K OHM NS R70 CLKIN_DMI_N CLKIN_DMI_P BF36 BD36 BC33 BA33 BM33 BM35 BT33 BU32 BR32 BT31 BN29 BM30 BK33 BJ33 BF31 BD31 BN27 BR29 BR26 BT27 BK25 BJ25 BJ31 BK31 BD27 BF27 BK27 BJ27 22 00 44 00 OF 10 J20 L20 F25 F23 P20 R20 C22 A22 H17 J17 E21 B21 P17 M17 F18 E17 N15 M15 B17 C16 J15 L15 A16 B15 J12 H12 F15 F13 H10 J10 B13 D13 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12P USBP12N USBP13P USBP13N 19 19 19 19 PCI CPT_CRB PCH_PCIE_RN1 PCH_PCIE_RP1 PCH_PCIE_TN1 PCH_PCIE_TP1 PCH_PCIE_RN2 PCH_PCIE_RP2 PCH_PCIE_TN2 PCH_PCIE_TP2 PCH_PCIE_RN3 PCH_PCIE_RP3 PCH_PCIE_TN3 PCH_PCIE_TP3 PCH_PCIE_RN4 PCH_PCIE_RP4 PCH_PCIE_TN4 PCH_PCIE_TP4 PCH_PCIE_RN5 PCH_PCIE_RP5 PCH_PCIE_TN5 PCH_PCIE_TP5 PCH_PCIE_RN6 PCH_PCIE_RP6 PCH_PCIE_TN6 PCH_PCIE_TP6 10K OHM P33 10K OHM R33 REV 1.0 DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_IRCOMP DMI_ZCOMP PCI-E P_INTA_N P_INTB_N P_INTC_N P_INTD_N P_INTE_N P_INTF_N P_INTG_N P_INTH_N BG5 BT5 BK8 AV11 GNT0# GNT1#_GPIO51 GNT2#_GPIO53 GNT3#_GPIO55 D33 DMI_MT_IR_0_DN B33 DMI_MT_IR_0_DP J36 DMI_IT_MR_0_DN H36 DMI_IT_MR_0_DP A36 DMI_MT_IR_1_DN B35 DMI_MT_IR_1_DP P38 DMI_IT_MR_1_DN R38 DMI_IT_MR_1_DP B37 DMI_MT_IR_2_DN C36 DMI_MT_IR_2_DP H38 DMI_IT_MR_2_DN J38 DMI_IT_MR_2_DP E37 DMI_MT_IR_3_DN F38 DMI_MT_IR_3_DP M41 DMI_IT_MR_3_DN P41 DMI_IT_MR_3_DP DMICOMP B31 R62 49.9 V_1P05_PCH W4S8 Near PIN 500MIL E31 22 00 44 00 P_REQ_N0 P_REQ_N1 P_REQ_N2 P_REQ_N3 BA15 AV8 BU12 BE2 CPT_CRB PCH1B P_GNT_N0 P_GNT_N1 P_GNT_N2 P_GNT_N3 BF15 BF17 BT7 BT13 BG12 BN11 BJ12 BU9 BR12 BJ3 BR9 BJ10 BM8 BF3 BN2 BE4 BE6 BG15 BC6 BT11 BA14 BL2 BC4 BL4 BC2 BM13 BA9 BF9 BA8 BF8 AV17 BK12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 USB 13 CK_PCH_33M_FB REV 1.0 PAR DEVSEL# CLKIN_PCILOOPBACK PCIRST# IRDY# PME# SERR# STOP# PLOCK# TRDY# PERR# FRAME# DMI BH8 BH9 P_DEVSEL_N CK_PCH_33M_FB BD15 AV14 BF11 P_IRDY_N AV15 P_PME_N BR6 P_SERR_N BC12 P_STOP_N BA17 P_PLOCK_N BC8 P_TRDY_N BM3 P_PERR_N BC11 P_FRAME_N 8.2K/NC P_PME_N VCC3 B 7 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 RN6 48.2K P_INTE_N P_INTA_N P_INTC_N P_INTG_N B RN7 P_REQ_N0 48.2K P_INTF_N P_REQ_N3 P_TRDY_N RN3 48.2K P_REQ_N1 P_SERR_N P_REQ_N2 P_DEVSEL_N RN4 48.2K P_FRAME_N P_IRDY_N P_STOP_N P_PLOCK_N RN5 48.2K P_INTB_N P_PERR_N P_INTH_N P_INTD_N VCC3 7 0402 0402 0402 0402 0402 0402 0402 0402 A A GM Confidential Title PCH-PCIE&USB Size C Document Number Date: Monday, June 04, 2012 Rev Sugar Bay Sheet 11 1.0 of 30 ? 22 OHMCK_P_33M_PCI2AT12 CLKOUT_PCI_3_R AT17 22 OHM AT14 D R194 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCI2 CLKOUT_PCIE7N CLKOUT_PCIE7P 22 OHM AT9 BA5 AW5 BA2 CLKOUT_PCI3 CLKOUT_PCI4 CLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_DP_N CLKOUT_DP_P CLKOUTFLEX0_GPIO64 CLKOUTFLEX1_GPIO65 CLKOUTFLEX2_GPIO66 CLKOUTFLEX3_GPIO67 CLKOUT_PCIE0N CLKOUT_PCIE0P CLKOUT_PCIE1N CLKOUT_PCIE1P V_1P05_PCH R296 23 CK_PCH_48M_SIO CLKOUT_PCI1 90.9 OHM XCLK_RCOMP AL2 R573 10K OHM AN8 XCLK_RCOMP REFCLK14IN CLKOUT_PCIE2N CLKOUT_PCIE2P OF 10 CLKOUT_PCIE3N CLKOUT_PCIE3P CPT_CRB ? CLKOUT_PCIE4N CLKOUT_PCIE4P CLKOUT_PCIE5N CLKOUT_PCIE5P CLKOUT_PCIE6N CLKOUT_PCIE6P AJ5 XTAL_25M_PCH_OUT XTAL_25M_PCH_IN AJ3 CLKOUT_PEG_A_N CLKOUT_PEG_A_P XTAL25_OUT CLKOUT_PEG_B_N CLKOUT_PEG_B_P XTAL25_IN W53 CK_CSI_PCH_IN_DN V52 CK_CSI_PCH_IN_DP R184 R186 REV 1.0 10K OHM 10K OHM 10K OHM 10K OHM 17 DDSP_B_HPD0 DDSP_C_HPD1 R52 N52 R8 R9 U14 U12 N6 R6 AE2 AF1 P31 R31 CK_PE_100M_MCP_DN CK_PE_100M_MCP_DP 17 17 17 17 17 17 17 17 N56 M55 AE6 AC6 AA5 W5 AB12 AB14 AB9 AB8 Y9 Y8 CK_PCIE1X_S1_DN CK_PCIE1X_S1_DP CK_PCIE1X_S2_DN 16 CK_PCIE1X_S2_DP 16 CK_LAN_DN CK_LAN_DP 19 19 CK_PCI_DN CK_PCI_DP CK_PCIE1X_S3_DN 16 CK_PCIE1X_S3_DP 16 AF3 AG2 AB3 AA2 AG8 AG9 T1 N2 M1 DDSP_B_TX_0_DP DDSP_B_TX_0_DN DDSP_B_TX_1_DP DDSP_B_TX_1_DN DDSP_B_TX_2_DP DDSP_B_TX_2_DN DDSP_B_TX_3_DP DDSP_B_TX_3_DN DDSP_C_TX_0_DP DDSP_C_TX_0_DN DDSP_C_TX_1_DP DDSP_C_TX_1_DN DDSP_C_TX_2_DP DDSP_C_TX_2_DN DDSP_C_TX_3_DP DDSP_C_TX_3_DN R14 R12 M11 M12 H8 K8 L5 M3 L2 J3 G2 G4 F3 F5 E4 E2 D5 B5 C6 D7 B7 C9 E11 B11 U2 T3 CK_PE_16PORT_PCH_DN 10 CK_PE_16PORT_PCH_DP 10 AE12 AE11 W3 U5 U8 U9 DDPB_HPD DDPC_HPD DDPD_HPD CRT_HSYNC CRT_VSYNC CRT_RED CRT_GREEN CRT_BLUE DDPB_AUXP DDPB_AUXN DDPC_AUXP DDPC_AUXN DDPD_AUXP DDPD_AUXN DDPB_0P DDPB_0N DDPB_1P DDPB_1N DDPB_2P DDPB_2N DDPB_3P DDPB_3N DDPC_0P DDPC_0N DDPC_1P DDPC_1N DDPC_2P DDPC_2N DDPC_3P DDPC_3N DDPD_0P DDPD_0N DDPD_1P DDPD_1N DDPD_2P DDPD_2N DDPD_3P DDPD_3N CRT_IRTN