5 MS-7C30 Ver:10 D CPU: AMD AM4 System Chipset: Promontory A320 (Value DIY or System Builder) FUSION BLOCK DIAGRAM D AM4 Main Memory: DDR IV * MAX:32 GB VRM RT8894 4+2 PCIE x16 GEN3 REAR USB *2 C On Board Chipset: LPC Super I/O NCT5567D-M LAN RTL8111H Azalia CODEC - Realtek ALC887 Expansion Slots: From CPU PCI Express X16 Slot * M2_M * M2_E * CHA DDRIV 2667 DP0~1 HDMI CON & DVI Raven Ridge PCIEx16 USB2.0 & USB3.1 GEN1 REAR USB *2 CHB DDRIV 2667 Pinnacle Ridge UNBUFFERED DDRIV DIMM1 00 UNBUFFERED DDRIV DIMM2 01 65W USB2.0 GPP1 C AUDIO ALC887 GPP3 M2 SOCKET 1331 GPP0 SPI ROM 128M SPI Bus NCT5567D LPC CLOCK SW GPP2 KBD MOUSE Vinafix.com HUB *4 GEN3 JUSB1 JUSB2 USB2.0 Promontory PS2+USB B FRONT USB GPP5_PCIE GEN2 M2 WIFI GPP4_PCIE GEN2 RTL8111H PROM1 Chipset M2_WIFI USB3.1 GEN1 A320 B SATA [2:1] A A MICRO-START INT'L CO.,LTD Title Block Diagram Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 1 of 56 AMD AM4 A 01 Block Diagram 38 CPU Power 1P8V-MP2147 02 Cover Sheet 39 CPU Power VDDP-MP8712 03 FM4 DDR4 I/F 40 CPU Power Connector/PWRGD 04 AM4 PCIE/SATAE 41 CPU Power RT8894 3+2 Phase 05 AM4 Display/Audio 42/43 CPU Power Phase 1-4 06 AM4 SVI/ACPI/GPIO 44 CPU Power NB Phase 1-2 07 AM4 LPC/SPI/USB/CLK/STRAP 45 CPU Power NB Switch/NCT3933 08 AM4 Power/RTC Power/ 09 AM4 GND 46 RT9553B CURRENT SENSE 10,11 DDR4-DIMM CH-A/B 47 ATX/Front Panel 12,13 DDR4-POWER/GND 48 ALL LED Control 14 Promontory-PCIE/SATA/SATAE 49 JRGB1/JRGB2 15 Promontory-USB/OC 50 BOM Option 16 Promontory-CLK/ACPI/GPIO 51 RTC Circuit/Moat Cap 17 Promontory-Power / 18 Promontory-GND 52 M2_2 20 SIO NCT6797D Vinafix.com 21 SIO HWM/COM 55 Power Delivery 22 DVI Connector 56 GPIO MAP 19 PCIE X16(X1*2) SLOT 53 History A 54 Power Sequence 23 FAN Control TYPE L/ K 24 / 25 / 26 LAN-RTL8111H/Audio ALC887 27 USB Rear PS2+USB2.0 28 USB Rear LAN+USB3.1 GEN1 29 Rear USB3.1 Type C / mux 30 USB Front Side 31 SATA Connector 32 HDMI Connector 34 ACPI uPI-5VDIMM&3VSB 35 PM-SY8288RAC-1.05V/GS7133-2.5V MICRO-START INT'L CO.,LTD 36 DDR PWR VPP25/VTT-MP2147 Title COVER SHEET Size Document Number Custom MS-7C30 37 DDR Power-RT8231AGQW Date: Tuesday, November 13, 2018 Rev 10 Sheet of 56 10 C B CPU1A MA_ADD[13 0] D 10 10 10 MA_ACT_L MA_BG0 MA_BG1 10 10 MA_BANK0 MA_BANK1 10 10 10 10 10 10 10 10 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 10 10 10 10 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 10 10 MA_RESET_L MA_EVENT_L 10 10 MA0_CKE0 MA0_CKE1 10 10 MA0_ODT0 MA0_ODT1 10 10 MA0_CS_L0 MA0_CS_L1 10 10 10 10 MA_ADD_17 MA_RAS_L MA_CAS_L MA_WE_L 10 10 MA_ALERT_L MA_PAROUT MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 AA32 T32 T35 T31 R30 R33 R32 P34 P30 P31 AA36 P33 N35 AE32 MA_ACT_L MA_BG0 MA_BG1 M35 N31 N32 MA_BANK0 MA_BANK1 AA35 AA33 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 K19 J23 G26 H30 AJ31 AM31 AL29 AL26 G34 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 H19 G19 F23 G23 F27 F26 F30 E30 AJ33 AJ34 AN32 AN33 AP29 AN29 AP26 AN26 H34 H33 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 T34 U34 U33 V33 V35 V36 V32 W32 MA_RESET_L MA_EVENT_L L33 W35 MA0_CKE0 MA0_CKE1 M32 M30 M33 L34 MA0_ODT0 MA0_ODT1 AD35 AF31 AD33 AF34 MA0_CS_L0 MA0_CS_L1 AC33 AE35 AC34 AE34 MA_ADD_17 MA_RAS_L MA_CAS_L MA_WE_L AF33 AB34 AD32 AB35 MA_ALERT_L MA_PAROUT N34 Y33 MA_DATA[63 0] MAMORY-A MA_ADD[0] MA_ADD[1] MA_ADD[2] MA_ADD[3] MA_ADD[4] MA_ADD[5] MA_ADD[6] MA_ADD[7] MA_ADD[8] MA_ADD[9] MA_ADD[10] MA_ADD[11] MA_ADD[12] MA_ADD[13] MA_DATA[0] MA_DATA[1] MA_DATA[2] MA_DATA[3] MA_DATA[4] MA_DATA[5] MA_DATA[6] MA_DATA[7] MA_DATA[8] MA_DATA[9] MA_DATA[10] MA_DATA[11] MA_DATA[12] MA_DATA[13] MA_DATA[14] MA_DATA[15] MA_ACT_L MA_BG[0] MA_BG[1] MA_BANK[0] MA_BANK[1] MA_DATA[16] MA_DATA[17] MA_DATA[18] MA_DATA[19] MA_DATA[20] MA_DATA[21] MA_DATA[22] MA_DATA[23] MA_DM[0] MA_DM[1] MA_DM[2] MA_DM[3] MA_DM[4] MA_DM[5] MA_DM[6] MA_DM[7] MA_DM[8] MA_DATA[24] MA_DATA[25] MA_DATA[26] MA_DATA[27] MA_DATA[28] MA_DATA[29] MA_DATA[30] MA_DATA[31] MA_DQS_H[0] MA_DQS_L[0] MA_DQS_H[1] MA_DQS_L[1] MA_DQS_H[2] MA_DQS_L[2] MA_DQS_H[3] MA_DQS_L[3] MA_DQS_H[4] MA_DQS_L[4] MA_DQS_H[5] MA_DQS_L[5] MA_DQS_H[6] MA_DQS_L[6] MA_DQS_H[7] MA_DQS_L[7] MA_DQS_H[8] MA_DQS_L[8] MA_DATA[32] MA_DATA[33] MA_DATA[34] MA_DATA[35] MA_DATA[36] MA_DATA[37] MA_DATA[38] MA_DATA[39] MA_DATA[40] MA_DATA[41] MA_DATA[42] MA_DATA[43] MA_DATA[44] MA_DATA[45] MA_DATA[46] MA_DATA[47] MA_CLK_H[0] MA_CLK_L[0] MA_CLK_H[1] MA_CLK_L[1] MA_CLK_H[2] MA_CLK_L[2] MA_CLK_H[3] MA_CLK_L[3] MA_DATA[48] MA_DATA[49] MA_DATA[50] MA_DATA[51] MA_DATA[52] MA_DATA[53] MA_DATA[54] MA_DATA[55] MA_RESET_L MA_EVENT_L MA0_CKE[0] MA0_CKE[1] MA1_CKE[0] MA1_CKE[1] MA_DATA[56] MA_DATA[57] MA_DATA[58] MA_DATA[59] MA_DATA[60] MA_DATA[61] MA_DATA[62] MA_DATA[63] MA0_ODT[0] MA0_ODT[1] MA1_ODT[0] MA1_ODT[1] MA0_CS_L[0] MA0_CS_L[1] MA1_CS_L[0] MA1_CS_L[1] MA_CHECK[0] MA_CHECK[1] MA_CHECK[2] MA_CHECK[3] MA_CHECK[4] MA_CHECK[5] MA_CHECK[6] MA_CHECK[7] MA_ADD_17 MA_RAS_L_ADD[16] MA_CAS_L_ADD[15] MA_WE_L_ADD[14] MA_ALERT_L MA_PAROUT AM4 E18 J18 J20 H21 H18 F18 G20 F20 MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 H22 G22 E24 J24 F21 J21 H24 F24 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 J26 J27 G28 H28 H25 G25 E28 H27 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 F29 J30 H31 F32 J29 G29 E31 G31 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 AH34 AJ30 AK30 AL34 AH31 AH32 AK33 AK32 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 AM34 AM33 AP31 AR33 AL32 AL31 AP34 AP32 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 AR31 AK29 AM28 AL28 AM30 AN30 AP28 AR28 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 AK27 AK26 AP25 AR25 AN27 AM27 AL25 AM25 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 10 11 VCC_DDR Type0 Only MA_ZVDDIO_MEM_S3 MA_ZVSS 11 11 11 MB_ACT_L MB_BG0 MB_BG1 11 11 MB_BANK0 MB_BANK1 11 11 11 11 11 11 11 11 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 11 11 11 11 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 R256 R269 39.2R/1% X_40.2R/1% 11 11 MB_RESET_L MB_EVENT_L 11 11 MB0_CKE0 MB0_CKE1 11 11 MB0_ODT0 MB0_ODT1 11 11 MB0_CS_L0 MB0_CS_L1 11 11 11 11 MB_ADD_17 MB_RAS_L MB_CAS_L MB_WE_L 11 11 MB_ALERT_L MB_PAROUT CPU1B MB_ADD[13 0] Vinafix.com F33 G32 K31 K32 E33 E34 J32 J33 Y34 MA_ZVDDIO_MEM_S3 AJ37 MA_ZVSS MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 AC36 U36 U37 T38 T37 R39 R36 P39 R38 P36 AC39 P37 N38 AG38 MB_ACT_L MB_BG0 MB_BG1 M38 M36 M39 MB_BANK0 MB_BANK1 AD38 AC37 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 C21 D26 A32 D37 AL38 AR39 AT35 AW29 F39 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 B22 A22 C27 B27 C33 C32 B37 A37 AM37 AM36 AT38 AT39 AU34 AV34 AU28 AU29 G38 G37 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_RESET_L MB_EVENT_L MB0_CKE0 MB0_CKE1 U39 V39 V38 W38 W37 Y37 Y39 AA39 K35 AA38 L37 K37 L39 L36 MB0_ODT0 MB0_ODT1 AF39 AH36 AF37 AH38 MB0_CS_L0 MB0_CS_L1 AE37 AG39 AE38 AG36 MB_ADD_17 MB_RAS_L MB_CAS_L MB_WE_L AH37 AD36 AF36 AD39 MB_ALERT_L MB_PAROUT N37 AB38 MB_DATA[63 0] MEMORY-B MB_ADD[0] MB_ADD[1] MB_ADD[2] MB_ADD[3] MB_ADD[4] MB_ADD[5] MB_ADD[6] MB_ADD[7] MB_ADD[8] MB_ADD[9] MB_ADD[10] MB_ADD[11] MB_ADD[12] MB_ADD[13] MB_DATA[0] MB_DATA[1] MB_DATA[2] MB_DATA[3] MB_DATA[4] MB_DATA[5] MB_DATA[6] MB_DATA[7] MB_DATA[8] MB_DATA[9] MB_DATA[10] MB_DATA[11] MB_DATA[12] MB_DATA[13] MB_DATA[14] MB_DATA[15] MB_ACT_L MB_BG[0] MB_BG[1] MB_BANK[0] MB_BANK[1] MB_DATA[16] MB_DATA[17] MB_DATA[18] MB_DATA[19] MB_DATA[20] MB_DATA[21] MB_DATA[22] MB_DATA[23] MB_DM[0] MB_DM[1] MB_DM[2] MB_DM[3] MB_DM[4] MB_DM[5] MB_DM[6] MB_DM[7] MB_DM[8] MB_DATA[24] MB_DATA[25] MB_DATA[26] MB_DATA[27] MB_DATA[28] MB_DATA[29] MB_DATA[30] MB_DATA[31] MB_DQS_H[0] MB_DQS_L[0] MB_DQS_H1] MB_DQS_L[1] MB_DQS_H[2] MB_DQS_L[2] MB_DQS_H[3] MB_DQS_L[3] MB_DQS_H[4] MB_DQS_L[4] MB_DQS_H[5] MB_DQS_L[5] MB_DQS_H[6] MB_DQS_L[6] MB_DQS_H[7] MB_DQS_L[7] MB_DQS_H[8] MB_DQS_L[8] MB_DATA[32] MB_DATA[33] MB_DATA[34] MB_DATA[35] MB_DATA[36] MB_DATA[37] MB_DATA[38] MB_DATA[39] MB_DATA[40] MB_DATA[41] MB_DATA[42] MB_DATA[43] MB_DATA[44] MB_DATA[45] MB_DATA[46] MB_DATA[47] MB_CLK_H[0] MB_CLK_L[0] MB_CLK_H[1] MB_CLK_L[1] MB_CLK_H[2] MB_CLK_L[2] MB_CLK_H[3] MB_CLK_L[3] MB_DATA[48] MB_DATA[49] MB_DATA[50] MB_DATA[51] MB_DATA[52] MB_DATA[53] MB_DATA[54] MB_DATA[55] MB_RESET_L MB_EVENT_L MB0_CKE[0] MB0_CKE[1] MB1_CKE[0] MB1_CKE[1] MB0_CS_L[0] MB0_CS_L[1] MB1_CS_L[0] MB1_CS_L[1] MB_CHECK[0] MB_CHECK[1] MB_CHECK[2] MB_CHECK[3] MB_CHECK[4] MB_CHECK[5] MB_CHECK[6] MB_CHECK[7] MB_ADD_17 MB_RAS_L_ADD[16] MB_CAS_L_ADD[15] MB_WE_L_ADD[14] MB_ALERT_L MB_PAROUT Type2/3 Only MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 A26 C26 A29 C29 A25 B25 A28 B28 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 A31 B31 B34 C35 B30 C30 B33 A34 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 B36 E36 C39 D38 A35 C36 B38 C38 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 AK39 AL37 AN36 AN39 AK38 AK36 AM39 AN38 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 AR36 AR37 AU37 AV37 AP37 AP38 AT36 AU38 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 AW35 AU35 AW32 AU32 AV36 AW36 AW33 AV33 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 AW30 AV30 AW27 AW26 AV31 AU31 AV28 AV27 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 11 D C B MB_DATA[56] MB_DATA[57] MB_DATA[58] MB_DATA[59] MB_DATA[60] MB_DATA[61] MB_DATA[62] MB_DATA[63] MB0_ODT[0] MB0_ODT[1] MB1_ODT[0] MB1_ODT[1] PART OF D20 B21 B24 C24 A20 C20 A23 C23 F38 F36 H39 J39 E37 E39 H36 H37 VCC_DDR Type0 Only AM4 Y36 MB_ZVDDIO_MEM_S3 AJ39 MB_ZVSS MB_ZVDDIO_MEM_S3 MB_ZVSS R257 R271 39.2R/1% X_40.2R/1% Type2/3 Only PART OF ZIF-SOCKET1331-HF ZIF-SOCKET1331-HF A A Project Schematic Cfg V A MICRO-START INT'L CO.,LTD Title AM4 DDR4 I/F Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet of 56 CPU1C PCIE 14 14 D Not supported HUB on TYPE Not supported PCIE on TYPE 0,1 PCIE SATA TYPE 2 TYPE 2/3 or or APU_RXP0 APU_RXN0 14 14 APU_RXP1 APU_RXN1 14 14 APU_RXP2 APU_RXN2 14 14 APU_RXP3 APU_RXN3 52 52 APU_GPP_RXP0 APU_GPP_RXN0 52 52 APU_GPP_RXP1 APU_GPP_RXN1 52 52 APU_GPP_RXP2 APU_GPP_RXN2 52 52 APU_GPP_RXP3 APU_GPP_RXN3 19 19 19 19 19 19 C Not supported GFX 4~15 on TYPE,1 GFX_RXP3 GFX_RXN3 GFX_RXP4 GFX_RXN4 19 19 GFX_RXP5 GFX_RXN5 GFX_RXP6 GFX_RXN6 19 19 GFX_RXP7 GFX_RXN7 19 19 GFX_RXP8 GFX_RXN8 19 19 GFX_RXP9 GFX_RXN9 19 19 GFX_RXP10 GFX_RXN10 19 19 19 19 B GFX_RXP2 GFX_RXN2 19 19 19 19 Not supported GFX 8~15 on TYPE 0,3 GFX_RXP1 GFX_RXN1 19 19 19 19 Only supported on TYPE GFX_RXP0 GFX_RXN0 GFX_RXP11 GFX_RXN11 GFX_RXP12 GFX_RXN12 GFX_RXP13 GFX_RXN13 19 19 GFX_RXP14 GFX_RXN14 19 19 GFX_RXP15 GFX_RXN15 APU_RXP0 APU_RXN0 AE8 AD8 APU_RXP1 APU_RXN1 AB8 AA8 APU_RXP2 APU_RXN2 Y6 Y7 APU_RXP3 APU_RXN3 W4 W5 APU_GPP_RXP0 APU_GPP_RXN0 AR9 AT9 APU_GPP_RXP1 APU_GPP_RXN1 AM9 AM10 APU_GPP_RXP2 APU_GPP_RXN2 AR10 AP10 APU_GPP_RXP3 APU_GPP_RXN3 AP11 AN11 GFX_RXP0 GFX_RXN0 F6 F5 GFX_RXP1 GFX_RXN1 G5 G4 GFX_RXP2 GFX_RXN2 H7 H6 GFX_RXP3 GFX_RXN3 J6 J5 GFX_RXP4 GFX_RXN4 K8 K7 GFX_RXP5 GFX_RXN5 K5 K4 GFX_RXP6 GFX_RXN6 L7 L6 GFX_RXP7 GFX_RXN7 M6 M5 GFX_RXP8 GFX_RXN8 N8 N7 GFX_RXP9 GFX_RXN9 N5 N4 GFX_RXP10 GFX_RXN10 P7 P6 GFX_RXP11 GFX_RXN11 R6 R5 GFX_RXP12 GFX_RXN12 T8 T7 GFX_RXP13 GFX_RXN13 T4 T5 GFX_RXP14 GFX_RXN14 U7 U6 GFX_RXP15 GFX_RXN15 V6 V5 Within 1500 mils from APU_P_ZVDDP APU CPU_VDDP R258 R304 196R/1% Within 1500 mils from APU 1KR/1% APU_SATA_ZVDDP Within 1000 mils from APU Within 1000 mils from APU W8 AV7 APUTXP0 APUTXN0 C906 C905 C0.22u6.3X C0.22u6.3X APU_TXP0 APU_TXN0 APUTXP1 APUTXN1 C912 C911 C0.22u6.3X C0.22u6.3X APU_TXP1 APU_TXN1 P_HUB_RXP[2] P_HUB_RXN[2] AE4 P_HUB_TXP[0] AE5 P_HUB_TXN[0] AA5 P_HUB_TXP[1] AB5 P_HUB_TXN[1] AC6 P_HUB_TXP[2] AC7 P_HUB_TXN[2] APUTXP2 APUTXN2 C909 C910 C0.22u6.3X C0.22u6.3X APU_TXP2 APU_TXN2 P_HUB_RXP[3] P_HUB_RXN[3] AD5 P_HUB_TXP[3] AD6 P_HUB_TXN[3] APUTXP3 APUTXN3 C907 C908 C0.22u6.3X C0.22u6.3X APU_TXP3 APU_TXN3 P_HUB_RXP[0] P_HUB_RXN[0] P_HUB_RXP[1] P_HUB_RXN[1] P_GPP_RXP[0] P_GPP_RXN[0] SATA Express P_GPP_RXP[1] P_GPP_RXN[1] P_GPP_RXP[2]/SATA_RX0P P_GPP_RXN[2]/SATA_RX0N P_GPP_RXP[3]/SATA_RX1P P_GPP_RXN[3]/SATA_RX1N P_GFX_RXP[0] P_GFX_RXN[0] P_GFX_RXP[1] P_GFX_RXN[1] P_GFX_RXP[2] P_GFX_RXN[2] P_GFX_RXP[3] P_GFX_RXN[3] P_GFX_RXP[4] P_GFX_RXN[4] P_GFX_RXP[5] P_GFX_RXN[5] P_GFX_RXP[6] P_GFX_RXN[6] P_GFX_RXP[7] P_GFX_RXN[7] AT12 P_GPP_TXP[0] AR12 P_GPP_TXN[0] AP13 P_GPP_TXP[1] AR13 P_GPP_TXN[1] APU_GPP_TXP0 APU_GPP_TXN0 AL13 P_GPP_TXP[2]/SATA_TX0PAM13 P_GPP_TXN[2]/SATA_TX0N AN14 P_GPP_TXP[3]/SATA_TX1PAP14 P_GPP_TXN[3]/SATA_TX1N APU_GPP_TXP2 APU_GPP_TXN2 P_GFX_RXP[9] P_GFX_RXN[9] P_GFX_RXP[10] P_GFX_RXN[10] P_GFX_RXP[11] P_GFX_RXN[11] P_GFX_RXP[12] P_GFX_RXN[12] P_GFX_RXP[13] P_GFX_RXN[13] P_GFX_RXP[14] P_GFX_RXN[14] P_GFX_RXP[15] P_GFX_RXN[15] P_ZVDDP SATA_ZVDDP Type0 Only AM4 APU_GPP_TXP3 APU_GPP_TXN3 D1 P_GFX_TXP[0] E1 P_GFX_TXN[0] E3 P_GFX_TXP[1] F3 P_GFX_TXN[1] GFX_TXP0 GFX_TXN0 F2 P_GFX_TXP[2] G2 P_GFX_TXN[2] G1 P_GFX_TXP[3] H1 P_GFX_TXN[3] GFX_TXP2 GFX_TXN2 H3 P_GFX_TXP[4] J3 P_GFX_TXN[4] J2 P_GFX_TXP[5] K2 P_GFX_TXN[5] K1 P_GFX_TXP[6] L1 P_GFX_TXN[6] GFX_TXP4 GFX_TXN4 L3 P_GFX_TXP[7] M3 P_GFX_TXN[7] M2 P_GFX_TXP[8] N2 P_GFX_TXN[8] GFX_TXP7 GFX_TXN7 N1 P_GFX_TXP[9] P1 P_GFX_TXN[9] P3 P_GFX_TXP[10] R3 P_GFX_TXN[10] R2 P_GFX_TXP[11] T2 P_GFX_TXN[11] GFX_TXP9 GFX_TXN9 T1 P_GFX_TXP[12] U1 P_GFX_TXN[12] U3 P_GFX_TXP[13] V3 P_GFX_TXN[13] GFX_TXP12 GFX_TXN12 Vinafix.com P_GFX_RXP[8] P_GFX_RXN[8] APU_GPP_TXP1 APU_GPP_TXN1 V2 P_GFX_TXP[14] W2 P_GFX_TXN[14] W1 P_GFX_TXP[15] Y1 P_GFX_TXN[15] W7 Type0 Only P_ZVSS V8 P0A_ZVSS AT8 Type2 Only P0B_ZVSS AV6 Type0 Only SATA_ZVSS GFX_TXP1 GFX_TXN1 GFX_TXP3 GFX_TXN3 GFX_TXP5 GFX_TXN5 GFX_TXP6 GFX_TXN6 GFX_TXP8 GFX_TXN8 GFX_TXP10 GFX_TXN10 GFX_TXP11 GFX_TXN11 GFX_TXP13 GFX_TXN13 GFX_TXP14 GFX_TXN14 GFX_TXP15 GFX_TXN15 APU_P_ZVSS APU_P0A_ZVSS APU_P0B_ZVSS APU_SATA_ZVSS R222 R253 R325 R309 APU_GPP_TXP0 APU_GPP_TXN0 52 52 APU_GPP_TXP1 APU_GPP_TXN1 52 52 APU_GPP_TXP2 APU_GPP_TXN2 52 52 APU_GPP_TXP3 APU_GPP_TXN3 52 52 GFX_TXP0 GFX_TXN0 19 19 GFX_TXP1 GFX_TXN1 19 19 GFX_TXP2 GFX_TXN2 19 19 GFX_TXP3 GFX_TXN3 19 19 GFX_TXP4 GFX_TXN4 19 19 GFX_TXP5 GFX_TXN5 19 19 GFX_TXP6 GFX_TXN6 19 19 GFX_TXP7 GFX_TXN7 19 19 GFX_TXP8 GFX_TXN8 19 19 GFX_TXP9 GFX_TXN9 19 19 GFX_TXP10 GFX_TXN10 19 19 GFX_TXP11 GFX_TXN11 19 19 GFX_TXP12 GFX_TXN12 19 19 GFX_TXP13 GFX_TXN13 19 19 GFX_TXP14 GFX_TXN14 19 19 GFX_TXP15 GFX_TXN15 19 19 196R/1% X_200R X_200R 1KR/1% PART OF APU_TXP0 APU_TXN0 14 14 APU_TXP1 APU_TXN1 14 14 APU_TXP2 APU_TXN2 14 14 APU_TXP3 APU_TXN3 14 14 D M2 Not supported PCIE on TYPE 0,1 C Only supported on TYPE B Within Within Within Within 1500 1500 1000 1000 mils mils mils mils from from from from APU APU APU APU ZIF-SOCKET1331-HF A A MICRO-START INT'L CO.,LTD Title AM4 PCIE/SATAE Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 of 56 R313 R311 R316 R312 AZ_BITCLK_R AZ_RST_R AZ_SYNC_R AZ_SDOUT_R 1KR/4 1KR/4 1KR/4 1KR/4 EMI AZ_BITCLK_R AZ_SDIN0 AZ_SDIN1 AZ_SDIN2 DVI change to HDMI CPU1D APU_TEST18 APU_TEST19 E6 E7 APU_TEST31 APU_TEST40 APU_TEST41 TP3 TP16 TP9 AA30 W30 A16 TEST28_H TEST28_L A10 DP2_AUXP A11 DP2_AUXN E10 DP2_HPD F12 DP_ZVSS E12 DP_AUX_ZVSS G13 DP_BLON H13 DP_DIGON H12 DP_VARY_BL K14 DP_STEREOSYNC DP_ZVSS DP_AUX_ZVSS DP_BLON DP_DIGON DP_VARY_BL Vinafix.com TEST31 TEST40 TEST41 AM4 DP_STEREOSYNC K14 PIN: ✞ PART OF R170 R159 2K1% 150R R147 R148 1KR/4 X_1KR/4 DVI Here is the example of Raven2 AM4’s DP2 function on existing AM4 board : 1.D-sub : DP to VGA translator (e.g ANX62xx) ok 2.DP : only lanes can work (lane and lane1) 3.DVI-D : no display (no TMDS clock on lane3) 4.HDMI : no display (no TMDS clock on lane3) by mail 2017-11-28 Type0 Only TP8 TP7 TP6 For Debug2 Not support Type2 CPU_1P8 SPEC HDMI, PU HIGH, HDMI Dongle, HDMI ✕ 1KR/4 1KR/4 APU_TEST28_H APU_TEST28_L TP12 TP13 C RV2 AM4 35W is a de-featured version For DP to VGA of RV1 AM4 65W, RV2 AM4 35W can only support displays ✔ R156 R155 TP14 TP4 AM4 Type processors: DP2 is not supported 50724 1_13 ✓ X_1KR/4 APU_TEST11 X_1KR/4 APU_TEST14 X_1KR/4 APU_TEST17 X_1KR/4 APU_TEST16 TP10 B6 B7 A7 A8 C8 C9 B9 B10 ✒ R183 R182 R206 R205 For Debug2 DP2_TXP[0] DP2_TXN[0] DP2_TXP[1] DP2_TXN[1] DP2_TXP[2] DP2_TXN[2] DP2_TXP[3] DP2_TXN[3] DP1_AUXP 33 DP1_AUXN 33 DP1_DP_HPD 33 ✄ 15K 15K 15K TEST APU_TEST0 APU_TEST1 APU_TEST2 R344 R353 R324 F11 DP1_AUXP G11 DP1_AUXN D10 DP1_HPD ✑ C APU_TEST11 APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 APU_TEST18 APU_TEST19 APU_TEST46 APU_TEST47 TEST0 TEST1/TMS TEST2 TEST4 TEST5 TEST6 TEST10 TEST11 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST46[13] TEST47 ✏ TP1 TP2 Not supported on TYPE ✎ APU_TEST1 APU_TEST0 APU_TEST2 For DVI ✝ X_1KR/4 X_2.2K X_2.2K 33 33 33 33 33 33 33 33 ✍ R355 R346 R323 32 DP1_TX2P_APU DP1_TX2N_APU DP1_TX1P_APU DP1_TX1N_APU DP1_TX0P_APU DP1_TX0N_APU DP1_TX3P_APU DP1_TX3N_APU ✆ AM6 AM7 AT3 L23 M22 D13 AB4 A13 C12 B12 C11 D11 G16 H16 AL4 P28 3VSB DP0_AUXP 32 DP0_AUXN 32 DP0_HDMI_HPD ✌ APU_TEST0 APU_TEST1 APU_TEST2 APU_TEST4 APU_TEST5 G10 DP0_AUXP H10 DP0_AUXN H9 DP0_HPD D4 DP1_TXP[0] D5 DP1_TXN[0] D7 DP1_TXP[1] D8 DP1_TXN[1] F8 DP1_TXP[2] G8 DP1_TXN[2] E9 DP1_TXP[3] F9 DP1_TXN[3] ✄ TP5 TDI TDO TCK TMS TRST_L DBRDY DBREQ_L For HDMI 32 32 32 32 32 32 32 32 ☞ For Debug1 A14 C14 C15 B15 B13 E13 D14 DP0_TX2P_APU DP0_TX2N_APU DP0_TX1P_APU DP0_TX1N_APU DP0_TX0P_APU DP0_TX0N_APU DP0_CLKP_APU DP0_CLKN_APU ☎ TP11 APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# D D2 C2 C3 B3 B4 A4 C5 C6 ✄ 33R/4 33R/4 33R/4 DP0_TXP[0] DP0_TXN[0] DP0_TXP[1] DP0_TXN[1] DP0_TXP[2] DP0_TXN[2] DP0_TXP[3] DP0_TXN[3] ✂ APU_DBREQ# R303 R319 R318 AZ_BITCLK AZ_SDIN0 AZ_SDIN1 AZ_SDIN2 AZ_RST_L AZ_SYNC AZ_SDOUT ✁ 1KR/4 AZ_RST# AZ_SYNC AZ_SDOUT AW3 AV3 AU5 AV4 AU1 AU2 AU4 ☛ R176 25 25 25 AZ_BITCLK_R AZ_SDIN0 AZ_SDIN1 AZ_SDIN2 AZ_RST_R AZ_SYNC_R AZ_SDOUT_R ✡ APU_TCK APU_TMS APU_TDI APU_TRST# 33R/4 ✠ 1KR/4 1KR/4 1KR/4 1KR/4 R321 ✟ R188 R187 R186 R185 AZ_BITCLK AZ_SDIN0 AUDIO AMD_HDTPWR 25 25 DISPLAY-0 D DISPLAY-1 X_10KR/4 10K 10K X_C10p50N/4 DISPLAY-2 R345 R329 R308 C303 ZIF-SOCKET1331-HF AMD_HDTPWR R767 R2347 1K/4 1K/4 I I HDT_PWROK HDT_RST_L 3VSB B APU_TRST# C1960 C0.01u16X/4 I R772 PWROK 4.7K/4 I R771 PWROK_LS 10K/4 I IB=(AMD_HDTPWR-Vbe)/4.7k (1.8-0.95)/4.7k=0.181mA Q106 HDT_PWROK PWROK_LS IB=(Vb-Vbe)/10k (1.75-0.95)/10k=0.08mA NN-CMKT3904 I R777 R770 R769 R766 33R/4 10K/4 10K/4 10K/4 I I I I TRST# DBRDY3 DBRDY2 DBRDY1 TP42 TP43 TP44 TP45 3VSB R765 RESET_L 4.7K/4 I R764 RESET_L_LS 10K/4 I Q342 IC=(Vc-Vce)/10k (3.3-0.2)/10k=0.16mA HDT_RST_L RESET_L_LS IB=(Vb-Vbe)/10k (1.75-0.95)/10k=0.08mA Stuff for first model S G TYPE1_CPU_SEL B*Ib>Ic=10*0.08=0.8>0.16 PN514 Vgs =0.5V~1.0V D 6,28,39,40,45 B*Ib>Ic=10*0.181=1.81>0.16 CPU_1P8 R1487 47KR/4 TYPE1_CPU_SEL: 1:CPU_1P8_S5 (Type2,3) 0:CPU_1P8(Type0) B B*Ib>Ic=10*0.08=0.8>0.16 IC=(Vc-Vce)/10k (3.3-0.2)/10k=0.16mA 11-15 Q149 N-PM514BA S CPU_1P8_S5 G TYPE1_CPU_SEL D G S Q148 2N7002 A Q150 P-PA002FMG AMD_HDTPWR D A B*Ib>Ic=10*0.181=1.81>0.16 IB=(AMD_HDTPWR-Vbe)/4.7k (1.8-0.95)/4.7k=0.181mA IC=(Vc-Vce)/10k (1.8-0.2)/10k=0.16mA NN-CMKT3904 I ATX_5VSB IC=(Vc-Vce)/10k (1.8-0.2)/10k=0.16mA MICRO-START INT'L CO.,LTD Title CPU_1P8_S5 R1488 X_0R/6 CPU_1P8 R1534 X_0R/6 AM4 DISPLAY/AUDIO AMD_HDTPWR Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 of 56 VCC3 ATX_5VSB 3VSB ATX_5VSB VCC5 VCC3 3VSB D S D Q94 P-PA002FMG APU_S0A3_GPIO R301 2.2K/4 VCC3 3VSB PWR_SW SLP_S3# R483 X_0R0402 AMD Hardware Validated Boot (HVB) 0:Enable or NC:Disable APU_SLP_S3# 2.2K/4 2.2K/4 AGPIO5_DEVSLP0 R417 CPU1E Add for HDT and close to PIN E16 & B16 CPU_1P8 R144 R145 1KR/4 APU_SIC 1KR/4 APU_SID R189 R172 300R/4 PWROK 300R/4 RESET_L APU_SVC 41 APU_SVD 41 APU_SVT 51 22,27,34,36,37,51 PWRBTN# APU_AM4R1 BLINK WAKE_L PCIE_RST SVD C17 R196 0R0402 1.8V 22 22 C346 1u6.3X Q27 APU_PROCHOT# RSMRST# SYSREST# PCIE_REST# KBRST# RSMRST# SYSREST# PCIE_REST# KBRST# APU_SIC APU_SID PROCHOT#_LS 33R/4 PCIE_RST 0R0402 KBRST_L R398 R384 R399 0R0402 APU_SIC R157 APU_SID APU_ALERT# 0R0402 APU_AM4R1 APU_AM4R1 AT2 AP2 AR3 AP4 AP5 AM4 AL7 AN24 WAKE_L AL5 AL2 TP41 SVT PWROK PWR_GOOD RESET_L PROCHOT_L THERMTRIP_L SLP_S3_L SLP_S5_L S0A3_GPIO/AGPIO10/SGPIO0_CLK S5_MUX_CTRL/EGPIO42 PWR_BTN_L/AGPIO0 BLINK/AGPIO11 SPKR/AGPIO91 RSMRST_L SYS_RESET_L/AGPIO1 PCIE_RST_L/EGPIO26 ESPI_RESET_L/KBRST_L WAKE_L/AGPIO2 LPC_PME_L/AGPIO22 Vinafix.com B18 C18 D16 SIC AL8 CORETYPE0 CORETYPE1 AM24 AN9 AGPIO84 AN23 AP23 IB=(Vcc3-Vbe)/10k (3.3-0.95)/10k=0.235mA IC=(VCC2-Vce)/10k (3.3-0.2)/10k=0.31mA SVD SIC SID ALERT_L FANIN0/AGPIO84 FANOUT0/AGPIO85 NN-CMKT3904 AP8 RTCCLK RTCCLK APU_32K_X1 AW5 Turn off power when BIOS into deep mode APU_32K_X2 AW6 RTCCLK X32K_X1 RTC B SCL0 SDA0 R416 R413 100R1% 100R1% SCLK0 10,41,51 SDATA0 10,41,51 AK3 SCL1/I2C3_SCL/AGPIO19 AK2 SDA1/I2C3_SDA/AGPIO20 SCL1 SDA1 R281 R280 X_0R X_0R SCLK_PCIE SDATA_PCIE AT6 AGPIO3 AR6 AGPIO4 AP22 AGPIO5/DEVSLP0 AN8 AGPIO6 AP7 AGPIO8 AN2 AGPIO9/SGPIO0_DATAOUTAN3 AGPIO23/SGPIO0_LOADAR4 AGPIO40/SGPIO0_DATAINAW17 AGPIO86 AV22 GENINT1_L/AGPIO89 AU23 GENINT2_L/AGPIO90 AM22 SATA_ACT_L/AGPIO130 AT18 EGPIO70 AW11 EGPIO95 AV12 EGPIO96 AW12 EGPIO97 AU13 EGPIO98 AV13 EGPIO99 AT14 EGPIO100 AT23 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AV24 CLK_REQ1_L/AGPIO115 AT24 CLK_REQ2_L/AGPIO116AL23 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 AR22 CLK_REQG_L/OSCIN/EGPIO132 AM4R1 CORETYPE[0] CORETYPE[1] AU25 SCL0/I2C2_SCL/EGPIO113 AV25 SDA0/I2C2_SDA/EGPIO114 AL1 USB_OC0_L/AGPIO16 AM1 USB_OC1_L/TDI/AGPIO17AR1 USB_OC2_L/TCK/AGPIO18AP1 USB_OC3_L/TDO/AGPIO24 FAN H15 A19 SVC MISC 22K A17 SVT AN5 AT5 AW23 PWRBTN# BLINK SPKR 34,37,38,39,40 0R0402 16,19,20,24,52 APU_WAKE# 16 APU_LPC_PME# RSMRST# C349 10u6.3X6 PROCHOT# R197 SPKR PWRBTN# 22,40 7,35,40,47 19 22 CPU_1P8_S5 S5_MUX_CTRL PROCHOT#_LS APU_SVD APU_SLP_S3# SLP_S5# APU_S0A3_GPIO S5_MUX_CTRL S5_MUX_CTRL 47 R377 4.7K D17 APU_PWROK E16 R190 0R0402 PWROK ALL_PWR_PWRGD AM3 RESET_L B16 KBRST# D14 X_S-LRB520S-40T1G APU_SLP_S3# SLP_S5# 22,51 10K SVC APU_PROCHOT# APU_THERMTRIP# 3VSB R518 0R0402 APU_SVT 41 APU_PWROK ALL_PWR_PWRGD 45 10K X_10K 10K 10K 10K X_C100p50N R198 3.3V Follow CRB R386 R393 R363 R397 R396 C358 APU_SVC ACPI 40 41 SMBus 1KR/4 APU_ALERT# 1KR/4 APU_PROCHOT# 1KR/4 APU_THERMTRIP# R179 R141 R152 X32K_X2 APU_AM4R1 F14 VDDCR_CPU_SENSE E15 VDDCR_SOC_SENSE G14 VDDIO_MEM_S3_SENSE F15 VSS_SENSE_A AL22 VDDP_SENSE AM23 VSS SENSE_B AGPIO3 AGPIO3 M2_DET AGPIO5_DEVSLP0 G S CPUFAN1_MODE SYSFAN1_MODE USB_MODE AGPIO86 GENINT1_L 23 23 For K TYPE FAN 27,34 TP22 SATA_LED# SATA_LED# 14,47 C VCC3 CLK_REQ0 CLK_REQ1 CLK_REQ2_M.2 CLK_REQ3 CLK_REQG R375 R348 CLK_REQ1 16 CLK_REQ2_M.2 52 APU_OC0# R2348 28 200KR/4 3VSB 11/20 VDDCR_CPU_SENSE+ VDDCR_SOC_SENSE+ VDDCR_CPU_SENSE+ VDDCR_SOC_SENSE+ VDDIO_MEM_S3_SENSE+ VSS_SENSE_A R963 R964 CPU_VDDP_SENSE VSS_SENSE_B CPU TYPE CORETYPE 41 41 VDDIO_MEM_S3_SENSE+ 37 VDDCR_CPU_SENSE41 VDDCR_SOC_SENSE41 X_0R0402 X_0R0402 CPU_VDDP_SENSE B 39 TP21 R342 R412 R336 R335 R341 ZIF-SOCKET1331-HF AM4 CPU TYPE Circuit SATA_LED# 560R/4 X_10K CLK_REQ2_M.2 Modify USB_OC# circuit APU_OC0# AM4 Q64 N-2N7002 Layout:Place x'tal within 1.5 inch of APU 19,20 19,20 52 PART OF D DEEP_S5 D by check list Within 500mils PWROK RESET_L PWROK RESET_L 10K PN514 Vgs =0.45V~1.2V SVI C445 0.1u16X 2N7002 GPIO PWR_SW 22,34,35 R282 R279 8.2KR/4 GENINT1_L X_10KR/4 R364 R354 NC7SZ08M5X_SOT23-5 OC 5 41 SCL1 SDA1 100KR/4 SENSE S 2N7002 PWR_SW R146 R337 G S VCC3 B GND APU_SLP_S3# D G C Y Q63 TYPE1_CPU_SEL A SLP_S3# VCC3 Q91 N-PM514BA G Q62 TYPE1_CPU_SEL Q85 X_P-PA002FMG PWR_SB_SW CPU_1P8 D G S G TYPE1_CPU_SEL: 1:3.3V(Type2,3) 0:1.8V(Type0) 22,27,34,35,37,38,40 0.1u16X 2.2K/4 2.2K/4 3VSB VCC Q90 N-PM514BA CPU_1P8_S5 D U44 D S R495 X_47KR/4 S D G TYPE1_CPU_SEL: 1:NC (Type2,3) 0:3.3V(Type0) R496 47KR/4 PN514 Vgs =0.5V~1.0V R424 R415 C431 R455 47KR/4 SCL0 SDA0 10K 10K X_10K 10K 10K CLK_REQ0 CLK_REQ1 CLK_REQ2_M.2 CLK_REQ3 CLK_REQG ATX_5VSB APU_32K_X2 APU_32K_X1 Change by CRB rev E 32.768KHZ12.5p ATX_5VSB R402 1KR/4 R383 47KR/4 3VSB A C296 C15p50N6 20MR R405 X_1KR/4 C295 C15p50N6 TYPE1_SEL S C R401 10K PLACE THESE COMPONENTS CLOSE TO U600, AND USE GROUND GUARD FOR 32K_X1 AND 32K_X2 D G CORETYPE1 B SR RV/ZP 1 TYPE1_CPU_SEL CPU_1P8_S5 0 CPU_1P8_S5 Q69 2N7002 5,28,39,40,45 CORETYPE0 0:BR/SR 1:RV/ZP TYPE1_CPU_SEL 0:BR/NA 1:ST/RV/ZP TYPE1_CPU_SEL 0:BR/NA 1:ST/RV/ZP TYPE0_CPU_SEL R444 4.7K B TYPE0_CPU_SEL 7,39,40 A Q87 2N3904 IB=(CPU_1P8_S5-Vbe)/5.7k (1.8-0.95)/5.7k=0.149mA IB=(vcc3-Vbe)/21k (3.3-0.95)/21k=0.111mA Q78 2N3904 R474 47KR/4 R443 1KR/4 CORETYPE0 IC=(VCC5-Vce)/47k (5-0.2)/47k=0.102mA IC=(VCC5-Vce)/10k (5-0.2)/47k=0.102mA E R317 R400 47KR/4 C ATX_5VSB Y2 NA E BR MICRO-START INT'L CO.,LTD Title AM4 SVI/ACPI/GPIO Document Number Size Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 of 56 Strapping Options EMI LPCCLK1 C313 X_C10p50N/4 VCC3 VCC3 VCC3 CPU1F LPC/SPI/USB/CLOCK 22,47 AU20 AU19 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 AW20 AV21 AT21 AT20 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_LFRAME# LPC_LDRQ0# LPC_SERIRQ R314 2KR/4 R28 LPC_RST# 33R/4 LPC_LFRAME# AW18 LPC_LDRQ0# AT15 LPC_SERIRQ AW21 LPC_CLKRUN AV19 AV18 LPC_RST_L AU22 LPCCLK0/EGPIO74 LPCCLK1/EGPIO75 48M_OSC LFRAME_L/EGPIO109 ESPI_ALERT_L/LDRQ0_L/EGPIO108 SERIRQ/AGPIO87 LPC_CLKRUN_L/AGPIO88 LPC_PD_L/AGPIO21 LPC_RST_L C1983 C150p50N/4 follow CRB SPI_CLK R338 10R/4 C314 AW14 AT17 AW15 AU14 AU16 AV16 AV15 AU17 SPI_CLK/ESPI_CLK/EGPIO117 SPI_CS1_L/EGPIO118 SPI_CS2_L/ESPI_CS_L/EGPIO119 SPI_DI/ESPI_DAT1/EGPIO120 SPI_DO/ESPI_DAT0/EGPIO121 SPI_WP_L/ESPI_DAT2/EGPIO122 SPI_HOLD_L/ESPI_DAT3/EGPIO133 SPI_TPM_CS_L/AGPIO76 X_C10p50N/4 PCIE X16 19 19 PE1_GFX_CLKP PE1_GFX_CLKN AF6 AF7 AG5 AG6 Promontory C APU_CLKP APU_CLKN 52 52 CLK_M2_DP CLK_M2_DN AH4 AH5 AH7 AH8 AJ6 AJ7 APU_48M_X1 APU_48M_X2 AJ1 AH1 AV9 USB_HSD3P AV10 USB_HSD3N GFX_CLKP GFX_CLKN APU_USB1+ APU_USB1- 28 28 APU_USB2+ APU_USB2- 28 28 APU_USB3+ APU_USB3- 28 28 R360 10K LPCCLK0 LAN USB2.0 R320 10K D LPC_LFRAME# LPCCLK1 R343 2KR/4 R340 X_2K R307 X_2K Front USB3.0 Type A PULL HIGH LPCCLK1 LPC device Boot Fail Timer Enabled SIO_LFRAME Configured for Internal clock generator SPI ROM (Default) AD2 USB_SS_2RXP AE2 USB_SS_2RXN AG2 USB_SS_3TXP AG3 USB_SS_3TXN AE1 USB_SS_3RXP AF1 USB_SS_3RXN GPP_CLK1P GPP_CLK1N GPP_CLK3P GPP_CLK3N R349 X_10KR/4 28 28 LPCCLK0 AA2 USB_SS_1RXP AA3 USB_SS_1RXN AC3 USB_SS_2TXP AC4 USB_SS_2TXN GPP_CLK0P GPP_CLK0N GPP_CLK2P GPP_CLK2N TP20 APU_USB0+ APU_USB0- AF3 USB_SS_0TXP AF4 USB_SS_0TXN Y3 USB_SS_0RXP Y4 USB_SS_0RXN AB1 USB_SS_1TXP AC1 USB_SS_1TXN CLOCK M.2_1 16 16 AW8 USB_HSD1P AW9 USB_HSD1N AU10 USB_HSD2P AU11 USB_HSD2N SPI SPI_DATAIN SPI_DATAOUT SPI_WP#_R SPI_HOLD#_R EMI SPI_CLK SPI_CLK_R SPI_CS# AR7 APU_48M_OSC AU7 USB_HSD0P AU8 USB_HSD0N LAD0/EGPIO104 LAD1/EGPIO105 LAD2/EGPIO106 LAD3/EGPIO107 USB2.0 22,47 22 22,47 0R0402 LPCCLK0 0R0402 LPCCLK1 LPC 22,47 22,47 22,47 22,47 D R330 R352 TPM_LPCCLK0 SIO_LPCCLK1 USB3.0 33M 47 33M 22 APU_USB_SSTX2+ APU_USB_SSTX2- 28 28 APU_USB_SSRX2+ APU_USB_SSRX2- 28 28 APU_USB_SSTX3+ APU_USB_SSTX3- 28 28 APU_USB_SSRX3+ APU_USB_SSRX3- 28 28 LPC device Boot Fail Timer Disabled PULL LOW Front USB3.0 Type A (Default) Configured for External clock generator ????? LPC ROM (Default) C 3VSB PWR_1P8B_SW 3VSB Only Support Type0 AJ4 USB_SS_ZVSS AK8 USB_SS_ZVDDP X48M_X1 AT11 USB_ZVSS AJ3 USB0_ZVSS AN6 USB1_ZVSS AK6 USB2_ZVSS AK5 USB3_ZVSS USB_SS_ZVSS USB_SS_ZVDDP R275 R273 USB_ZVSS R305 1K/1% 1K/1% R367 10K CPU_VDDP_S5 Vinafix.com X48M_X2 USB0_ZVSS USB1_ZVSS USB2_ZVSS USB3_ZVSS R315 10K 11.8K1% R268 R274 R270 R272 X_200R1% X_200R1% X_200R1% X_200R1% SPI_CLK_R AGPIO3 6,35,40,47 R366 X_2K R297 10K SYSREST# R306 X_2K R298 X_2K Within 1000 mils from APU AM4 PART OF ZIF-SOCKET1331-HF Only Support Type2/3 VDDP_S5 (S5 Wake Implemented) or VDDP (S5 Wake Not Implemented) PULL HIGH B AGPIO3 SPI_CLK Enhanced Reset logic Use 48Mhz crystal clock and generate both internal and external clocks (Default) SPI ROM(1.8V) 12-19 Layout:Place x'tal within 1.5 inch of APU APU_48M_X1 1MR 0R0402 0R0402 0R0402 CS# DATAIN SPI_WP# CS DO(IO1) WP(IO2) GND VCC HOLD(IO3) CLK DI(IO0) SPI_HOLD# SPI_CLK DATAOUT 0R0402 SPI_HOLD#_R R525 0R0402 SPI_DATAOUT R378 10K PLACE THESE COMPONENTS CLOSE TO U600, AND USE GROUND GUARD FOR48M_X1 AND 48M_X2 D29 SPI_SW_SEL SPI_WP#_R C251 8.2p50N4 11 SPI_PWR_SW SPI_DATAOUT SPI_CLK TYPE0_CPU_SEL: 0:CPU_1P8_S5 (Type1,3) 1:CPU_1P8(Type2) 12 SPI_HOLD#_R D30 X_ESD-0402-L CPU_1P8_S5 G D G R373 X_2K D03-PA00209-N03 Q338 PA002FMG 6,39,40 TYPE0_CPU_SEL TYPE0_CPU_SEL D G S 40 ALL_PWR_MUX PULL LOW RTC Coin Battery is not on board A PWR_1P8B_SW Q337 Q336 N-2N7002 MICRO-START INT'L CO.,LTD N-PM514BA_SOT23-3-HF Title D03-514BA09-N03 (Default) RTCCLK S H2X6[10]M-2PITCH_BLACK-RH-3 P.S Close to JSPI1 R2329 47K/4 C243 8.2p50N4 SPI_DATAIN SPI_CS# RTC Coin Battery is on board PWR_1P8B_SW JSPI1 A PULL HIGH CPU_1P8 PWR_1P8B_SW 48MHZ12p_S-HF RTCCLK M31-2512883-W03 SPI CS# < 20pF D0G-0402510-SI0 X_ESD-SFI0402-050E100NP GND GND APU_48M_R PWR_SB_SW ATX_5VSB W25Q128FWSIQ-RH R262 49.9R/1% Y1 short reset mode 20170417update R527 B (Default) Use 100Mhz PCIE clock as reference clock and generate internal clocks only SPI_HOLD# SPI_WP# SPI_CS# D R261 R517 R492 R504 10u6.3X6 0.1u16X X_10KR/4 X_10KR/4 10KR/4 S SPI_CS# SPI_DATAIN SPI_WP#_R C449 C452 SPI1 R526 R505 R524 PWR_1P8B_SW PWR_1P8B_SW APU_48M_X2 Normal reset mode (Default) Traditional Reset logic PULL LOW SYSREST# R539 0R0402 AM4 LPC/SPI/USB/CLK/STRAP Size Document Number Custom MS-7C30 SPI_SW_SEL Date: Rev 10 Sheet Tuesday, November 13, 2018 of 56 VDDIO_AUDIO Circuit 5VDUAL 3VSB CPU_V_AUDIO_CNTL C B A VCORE VCCP_NB CPU1H M7 N3 N6 P2 R7 T3 T6 T9 U2 U10 V9 V11 W3 W6 W10 W12 Y2 Y9 Y11 Y13 AA7 AA10 AA12 AB3 AB6 AB9 AB11 AB13 AC2 AC10 AC12 AD7 AD9 AD11 AD13 AE3 AE6 AE10 AE12 AF2 AF9 AF11 AF13 AG7 AG10 AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AH3 AH6 AH9 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AJ2 AJ10 AJ12 AJ14 AJ22 AJ24 AK7 AK9 AK11 AK13 AL3 AL6 AL10 AL12 AL14 AM2 AM8 AN7 AN10 AN13 AP3 AP9 AP12 AR2 AT4 AU3 AU6 AU9 AU12 AU15 AV5 AV8 AV11 AV14 POWER VDDCR_CPU_0 VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8 VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15 VDDCR_CPU_16 VDDCR_CPU_17 VDDCR_CPU_18 VDDCR_CPU_19 VDDCR_CPU_20 VDDCR_CPU_21 VDDCR_CPU_22 VDDCR_CPU_23 VDDCR_CPU_24 VDDCR_CPU_25 VDDCR_CPU_26 VDDCR_CPU_27 VDDCR_CPU_28 VDDCR_CPU_29 VDDCR_CPU_30 VDDCR_CPU_31 VDDCR_CPU_32 VDDCR_CPU_33 VDDCR_CPU_34 VDDCR_CPU_35 VDDCR_CPU_36 VDDCR_CPU_37 VDDCR_CPU_38 VDDCR_CPU_39 VDDCR_CPU_40 VDDCR_CPU_41 VDDCR_CPU_42 VDDCR_CPU_43 VDDCR_CPU_44 VDDCR_CPU_45 VDDCR_CPU_46 VDDCR_CPU_47 VDDCR_CPU_48 VDDCR_CPU_49 VDDCR_CPU_50 VDDCR_CPU_51 VDDCR_CPU_52 VDDCR_CPU_53 VDDCR_CPU_54 VDDCR_CPU_55 VDDCR_CPU_56 VDDCR_CPU_57 VDDCR_CPU_58 VDDCR_CPU_59 VDDCR_CPU_60 VDDCR_CPU_61 VDDCR_CPU_62 VDDCR_CPU_63 VDDCR_CPU_64 VDDCR_CPU_65 VDDCR_CPU_66 VDDCR_CPU_67 VDDCR_CPU_68 VDDCR_CPU_69 VDDCR_CPU_70 VDDCR_CPU_71 VDDCR_CPU_72 VDDCR_CPU_73 VDDCR_CPU_74 VDDCR_CPU_75 VDDCR_CPU_76 VDDCR_CPU_77 VDDCR_CPU_78 VDDCR_CPU_79 VDDCR_CPU_80 VDDCR_CPU_81 VDDCR_CPU_82 VDDCR_CPU_83 VDDCR_CPU_84 VDDCR_CPU_85 VDDCR_CPU_86 VDDCR_CPU_87 VDDCR_CPU_88 VDDCR_CPU_89 VDDCR_CPU_90 VDDCR_CPU_91 VDDCR_CPU_92 VDDCR_CPU_93 VDDCR_CPU_94 VDDCR_CPU_95 VDDCR_CPU_96 VDDCR_CPU_97 VDDCR_CPU_98 VDDCR_SOC_0 VDDCR_SOC_1 VDDCR_SOC_2 VDDCR_SOC_3 VDDCR_SOC_4 VDDCR_SOC_5 VDDCR_SOC_6 VDDCR_SOC_7 VDDCR_SOC_8 VDDCR_SOC_9 VDDCR_SOC_10 VDDCR_SOC_11 VDDCR_SOC_12 VDDCR_SOC_13 VDDCR_SOC_14 VDDCR_SOC_15 VDDCR_SOC_16 VDDCR_SOC_17 VDDCR_SOC_18 VDDCR_SOC_19 VDDCR_SOC_20 VDDCR_SOC_21 VDDCR_SOC_22 VDDCR_SOC_23 VDDCR_SOC_24 VDDCR_SOC_25 VDDCR_SOC_26 VDDCR_SOC_27 VDDCR_SOC_28 VDDCR_SOC_29 VDDCR_SOC_30 VDDCR_SOC_31 VDDCR_SOC_32 VDDCR_SOC_33 VDDCR_SOC_34 VDDCR_SOC_35 VDDCR_SOC_36 VDDCR_SOC_37 VDDCR_SOC_38 VDDCR_SOC_39 VDDCR_SOC_40 VDDCR_SOC_41 VDDCR_SOC_42 VDDCR_SOC_43 VDDCR_SOC_44 VDDCR_SOC_45 VDDCR_SOC_46 VDDCR_SOC_47 VDDCR_SOC_48 VDDCR_SOC_49 VDDCR_SOC_50 VDDCR_SOC_51 VDDCR_SOC_52 VDDCR_SOC_53 VDDCR_SOC_54 VDDCR_SOC_55 VDDCR_SOC_56 VDDCR_SOC_57 VDDCR_SOC_58 VDDCR_SOC_59 VDDCR_SOC_60 VDDCR_SOC_61 VDDCR_SOC_62 VDDCR_SOC_63 VDDCR_SOC_64 VDDCR_SOC_65 VDDCR_SOC_66 VDDCR_SOC_67 VDDCR_SOC_68 VDDCR_SOC_69 VDDCR_SOC_70 VDDCR_SOC_71 VDDCR_SOC_72 B5 B8 B11 B14 B17 B20 C4 C7 C10 C13 C16 C19 D3 E2 F7 F10 F13 F16 G3 G6 G9 G12 G15 G18 H2 J7 J10 J12 J14 J16 K3 K6 K9 K11 K13 K15 L2 L10 L12 L14 L16 L18 L20 L22 L24 L26 M9 M11 M13 M15 M17 M19 M21 M23 M25 N10 N12 N14 N16 N18 N20 N22 N24 N26 P9 P11 P13 R10 R12 T11 T13 U12 V13 AJ18 VDDCR_SOC_S5_0 AK18 VDDCR_SOC_S5_1 C397 0.1u16X C459 10u6.3X6 POK VOUT NC FB R536 10K/1% D CPU_V_AUDIO_FB GS7166SSO 1.5V 0.25A X_0R/6 0R/6 CPU_V_1P5V C464 C560p50X4 VIN R530 R531 EN D 3VSB GND-1 VDDIO_AUDIO 1u6.3X CPU_1P8 CPU_V_1P5V VDD U49 CPU_V_AUDIO_EN C456 R537 10K/1% GND-2 10R/4 R529 C453 C22u6.3X6 R535 11.3KR1%/4 VFB=0.8 AVL: I31-3730S02-N62 TOP SIDE CPU_1P8 VCORE VCC_DDR CPU1G K36 K39 L32 L35 L38 M29 M31 M34 M37 N28 N30 N33 N36 N39 P27 P29 P32 P35 P38 R28 R31 R34 R37 T27 T29 T33 T36 T39 U28 U30 U32 U35 U38 V27 V29 V31 V34 V37 W28 W33 W34 W36 W39 Y27 Y29 Y31 Y32 Y35 Y38 AA28 AA34 AA37 AB27 AB29 AB31 AB32 AB33 AB36 AB39 AC28 AC30 AC32 AC35 AC38 AD27 AD29 AD31 AD34 AD37 AE28 AE30 AE33 AE36 AE39 AF27 AF29 AF32 AF35 AF38 AG33 AG34 AG35 AG37 AH39 VCCP_NB_S5 0.9A AM4 CPU_VDDP POWER VDDIO_MEM_S3_0 VDDIO_MEM_S3_1 VDDIO_MEM_S3_2 VDDIO_MEM_S3_3 VDDIO_MEM_S3_4 VDDIO_MEM_S3_5 VDDIO_MEM_S3_6 VDDIO_MEM_S3_7 VDDIO_MEM_S3_8 VDDIO_MEM_S3_9 VDDIO_MEM_S3_10 VDDIO_MEM_S3_11 VDDIO_MEM_S3_12 VDDIO_MEM_S3_13 VDDIO_MEM_S3_14 VDDIO_MEM_S3_15 VDDIO_MEM_S3_16 VDDIO_MEM_S3_17 VDDIO_MEM_S3_18 VDDIO_MEM_S3_19 VDDIO_MEM_S3_20 VDDIO_MEM_S3_21 VDDIO_MEM_S3_22 VDDIO_MEM_S3_23 VDDIO_MEM_S3_24 VDDIO_MEM_S3_25 VDDIO_MEM_S3_26 VDDIO_MEM_S3_27 VDDIO_MEM_S3_28 VDDIO_MEM_S3_29 VDDIO_MEM_S3_30 VDDIO_MEM_S3_31 VDDIO_MEM_S3_32 VDDIO_MEM_S3_33 VDDIO_MEM_S3_34 VDDIO_MEM_S3_35 VDDIO_MEM_S3_36 VDDIO_MEM_S3_37 VDDIO_MEM_S3_38 VDDIO_MEM_S3_39 VDDIO_MEM_S3_40 VDDIO_MEM_S3_41 VDDIO_MEM_S3_42 VDDIO_MEM_S3_43 VDDIO_MEM_S3_44 VDDIO_MEM_S3_45 VDDIO_MEM_S3_46 VDDIO_MEM_S3_47 VDDIO_MEM_S3_48 VDDIO_MEM_S3_49 VDDIO_MEM_S3_50 VDDIO_MEM_S3_51 VDDIO_MEM_S3_52 VDDIO_MEM_S3_53 VDDIO_MEM_S3_54 VDDIO_MEM_S3_55 VDDIO_MEM_S3_56 VDDIO_MEM_S3_57 VDDIO_MEM_S3_58 VDDIO_MEM_S3_59 VDDIO_MEM_S3_60 VDDIO_MEM_S3_61 VDDIO_MEM_S3_62 VDDIO_MEM_S3_63 VDDIO_MEM_S3_64 VDDIO_MEM_S3_65 VDDIO_MEM_S3_66 VDDIO_MEM_S3_67 VDDIO_MEM_S3_68 VDDIO_MEM_S3_69 VDDIO_MEM_S3_70 VDDIO_MEM_S3_71 VDDIO_MEM_S3_72 VDDIO_MEM_S3_73 VDDIO_MEM_S3_74 VDDIO_MEM_S3_75 VDDIO_MEM_S3_76 VDDIO_MEM_S3_77 VDDIO_MEM_S3_78 VDDIO_MEM_S3_79 VDDIO_MEM_S3_80 VDDIO_MEM_S3_81 VDDIO_MEM_S3_82 VDDIO_MEM_S3_83 VDDP_0 VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5 VDDP_6 VDDP_7 VDDP_8 VDDIO_AUDIO C215 AM18 AM19 AM20 AN18 AN19 AN20 AP18 AP19 AP20 C213 C217 C218 C22u6.3X6 C22u6.3X6 C22u6.3X6 C874 C895 C920 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C873 C1000p50X4 C896 C869 C180P50N C180P50N C900 C317 C320 C0.22u6.3X 10u6.3X6 C220 VDDIO_AUDIO 0.25A C299 VCC3 C0.22u6.3X4 C0.22u6.3X4 C901 10u6.3X6 C892 C0.22u6.3X4 BOTTOM SIDE C331 C893 C330 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C329 0.1u16X C CPU_VDDP_S5 1.00A Vinafix.com AJ15 VDD_18_S5_0 AK15 VDD_18_S5_1 CPU_1P8_S5 AJ19 VDD_33_S5_0 AK19 VDD_33_S5_1 3VSB 0.25A AL15 C722 C719 1u6.3X C0.22u6.3X4 AM12 AT25 AR15 AP15 AN12 AN15 AT30 AW24 AR24 A5 AD3 AB2 AH2 AL16 AL17 AL18 AL19 AL20 AL21 AM16 AM17 AM21 AN16 AN17 AN21 AP16 AP17 AP21 AR16 AR18 AR19 AR20 AR21 AT19 D28 E19 E22 E25 G17 J36 J38 K34 K38 R35 AB37 AH35 AK34 0.5A VDDBT_RTC_G 4.5uA C865 C876 C867 C868 C884 C844 C843 C883 C881 C882 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 X_C22u6.3X6 C22u6.3X6 C848 C880 C847 C22u6.3X6 C22u6.3X6 C22u6.3X6 C845 C862 C846 C863 C849 C878 C877 C22u6.3X6 X_C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C837 C856 C872 C894 C889 C891 C885 C922 C923 C921 C924 C926 C927 C925 C972 C929 C928 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C861 C879 C0.22u6.3X4 C0.22u6.3X4 C897 C904 C850 C839 C857 C841 C811 C796 C818 C805 C793 CPU_VDDP C903 C22u6.3X6 VCC_DDR C826 C823 C821 C827 C828 C830 C824 C825 C835 C815 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 TOP CAVITY VCCP_NB X_C22u6.3X6 C22u6.3X6 C22u6.3X6 X_C22u6.3X6 X_C22u6.3X6 X_C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C814 C832 C809 C806 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C808 C792 C804 C794 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C788 C803 C807 C798 C800 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C795 C789 C802 C813 C820 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C791 C797 C801 C180P50N C180P50N C180P50N VCORE C860 C852 C22u6.3X6 C22u6.3X6 C859 C22u6.3X6 C810 C816 C858 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C855 C870 C851 C790 C838 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C831 C871 C240 C875 C812 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C2.2u6.3X4 C829 C0.22u6.3X4 C817 C819 C822 C0.22u6.3X4 C0.22u6.3X4 C0.22u6.3X4 C834 C0.22u6.3X4 C887 C799 C0.22u6.3X4 C0.22u6.3X4 C888 C886 C180P50N C180P50N C125 C172 C230 C231 C137 C112 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C212 C228 C229 C232 C122 C233 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 X_C22u6.3X6 C118 C22u6.3X6 C163 C2.2u6.3X4 VCCP_NB B C199 C81 C200 C201 X_C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C80 C203 C85 C84 C22u6.3X6 X_C22u6.3X6 C22u6.3X6 X_C22u6.3X6 C86 C679 C202 C82 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 VCC_DDR C294 C22u6.3X6 C205 C197 C222 C236 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C219 C208 C210 C235 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 C284 C241 C2.2u6.3X4 C2.2u6.3X4 A MICRO-START INT'L CO.,LTD Title AM4 Power/RTC Power Size Document Number Custom MS-7C30 ZIF-SOCKET1331-HF C321 CPU_1P8_S5 C22u6.3X6 Date: C22u6.3X6 C315 2.00A 0.25A PART OF ZIF-SOCKET1331-HF 10u6.3X6 CPU_1P8 AJ16 VDDP_S5_0 AJ17 VDDP_S5_1 RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27 RSVD_28 RSVD_29 RSVD_30 RSVD_31 RSVD_32 RSVD_33 RSVD_34 RSVD_35 RSVD_36 RSVD_37 RSVD_38 RSVD_39 RSVD_40 RSVD_41 RSVD_42 RSVD_43 RSVD_44 RSVD_45 RSVD_46 C0.22u6.3X4 C333 VCCP_NB_S5 VCORE VDDBT_RTC_G C335 VCC3 X_C22u6.3X6 3VSB AM15 AJ20 VDD_18_0 AK20 VDD_18_1 AJ21 VDD_33_0 AK21 VDD_33_1 AM4 PART OF 8.5A CPU_VDDP_S5 Rev 10 Tuesday, November 13, 2018 Sheet of 56 F35 F37 G7 G21 G24 G27 G30 G33 G35 G36 G39 H4 H5 H8 H11 H14 H17 H20 H23 H26 H29 H32 H35 H38 J1 J4 J8 J9 J11 J13 J17 J19 J22 J25 J28 J31 J34 J35 J37 K10 K12 K18 K20 K21 K22 K23 K26 K27 K28 K29 K30 K33 L4 L5 L8 L9 L11 L13 L15 L17 L19 L21 L25 L27 L28 L30 L31 M1 M4 M8 M10 M12 M14 M16 M18 M20 M24 M26 M27 M28 N9 N11 N13 N15 N17 N19 N21 N23 N25 N27 N29 P4 P5 P8 P10 P12 R1 R4 R8 R9 R11 R13 R27 R29 T10 T12 T28 T30 U4 U5 U8 U9 U11 U13 U27 U29 U31 V1 V4 V7 V10 V12 V28 V30 W9 W11 W13 W27 W29 W31 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 CPU1I C B J15 L29 AJ11 A3 A6 A9 A12 A15 A18 A21 A24 A27 A30 A33 A36 B19 B23 B26 B29 B32 B35 C1 C22 C25 C28 C31 C34 C37 D6 D9 D12 D15 D18 D19 D21 D22 D23 D24 D25 D27 D29 D30 D31 D32 D33 D34 D35 D36 D39 E4 E5 E8 E11 E14 E17 E20 E21 E23 E26 E27 E29 E32 E35 E38 F1 F4 F17 F19 F22 F25 F28 F31 F34 AN1 AN4 AN22 AN25 AN28 AN31 AN34 AN35 AN37 AP6 AP24 AP27 AP30 AP33 AP35 AP36 AP39 AR5 AR8 AR11 AR14 AR17 AR23 AR26 AR27 AR29 AR30 AR32 AR34 AR35 AR38 AT1 AT7 AT10 AT13 AT16 AT22 AT26 AT27 AT28 AT29 AT31 AT32 AT33 AT34 AT37 AU18 AU21 AU24 AU26 AU27 AU30 AU33 AU36 AU39 AV2 AV17 AV20 AV23 AV26 AV29 AV32 AV35 AV38 AW4 AW7 AW10 AW13 AW16 AW19 AW22 AW25 AW28 AW31 AW34 AW37 AF28 AF30 AG1 AG4 AG8 AG9 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AG28 AG29 AG30 AG31 AG32 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH29 AH30 AH33 AJ5 AJ8 AJ9 AJ13 AJ23 AJ25 AJ26 AJ27 AJ28 AJ29 AJ32 AJ35 AJ36 AJ38 MEC6 MEC5 MEC4 MEC3 MEC2 MEC1 D VSS_398 VSS_397 VSS_396 VSS_395 VSS_394 VSS_393 VSS_392 VSS_391 VSS_390 VSS_389 VSS_388 VSS_387 VSS_386 VSS_385 VSS_384 VSS_383 VSS_382 VSS_381 VSS_380 VSS_379 VSS_378 VSS_377 VSS_376 VSS_375 VSS_374 VSS_373 VSS_372 VSS_371 VSS_370 VSS_369 VSS_368 VSS_367 VSS_366 VSS_365 VSS_364 VSS_363 VSS_362 VSS_361 VSS_360 VSS_359 VSS_358 VSS_357 VSS_356 VSS_355 VSS_354 VSS_353 VSS_352 VSS_351 VSS_350 VSS_349 VSS_348 VSS_347 VSS_346 VSS_345 VSS_344 VSS_343 VSS_342 VSS_341 VSS_340 VSS_339 VSS_338 VSS_337 VSS_336 VSS_335 VSS_334 VSS_333 VSS_332 VSS_331 VSS_330 VSS_329 VSS_328 VSS_327 VSS_326 VSS_325 VSS_324 VSS_323 VSS_322 VSS_321 VSS_320 VSS_319 VSS_318 VSS_317 VSS_316 VSS_315 VSS_314 VSS_313 VSS_312 VSS_311 VSS_310 VSS_309 VSS_308 VSS_307 VSS_306 VSS_305 VSS_304 VSS_303 VSS_302 VSS_301 VSS_300 VSS_299 VSS_298 VSS_297 VSS_296 VSS_295 VSS_294 VSS_293 VSS_292 VSS_291 VSS_290 VSS_289 VSS_288 VSS_287 VSS_286 VSS_285 VSS_284 VSS_283 VSS_282 VSS_281 VSS_280 VSS_279 VSS_278 VSS_277 VSS_276 MEC6 MEC5 MEC4 MEC3 MEC2 MEC1 51 CPU_IN# R1391 0R/4 R1392 X_0R/4 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 3 2 D GND Vinafix.com PART OF AM4 VSS_275 VSS_274 VSS_273 VSS_272 VSS_271 VSS_270 VSS_269 VSS_268 VSS_267 VSS_266 VSS_265 VSS_264 VSS_263 VSS_262 VSS_261 VSS_260 VSS_259 VSS_258 VSS_257 VSS_256 VSS_255 VSS_254 VSS_253 VSS_252 VSS_251 VSS_250 VSS_249 VSS_248 VSS_247 VSS_246 VSS_245 VSS_244 VSS_243 VSS_242 VSS_241 VSS_240 VSS_239 VSS_238 VSS_237 VSS_236 VSS_235 VSS_234 VSS_233 VSS_232 VSS_231 VSS_230 VSS_229 VSS_228 VSS_227 VSS_226 VSS_225 VSS_224 VSS_223 VSS_222 VSS_221 VSS_220 VSS_219 VSS_218 VSS_217 VSS_216 VSS_215 VSS_214 VSS_213 VSS_212 VSS_211 VSS_210 VSS_209 VSS_208 VSS_207 VSS_206 VSS_205 VSS_204 VSS_203 Date: AK1 AK4 AK10 AK12 AK14 AK22 AK25 AK28 AK31 AK35 AK37 AL9 AL11 AL24 AL27 AL30 AL33 AL35 AL36 AL39 AM5 AM11 AM14 AM26 AM29 AM32 AM35 AM38 AF12 AF10 AF8 AF5 AE31 AE29 AE27 AE13 AE11 AE9 AE7 AD30 AD28 AD12 AD10 AD4 AD1 AC31 AC29 AC27 AC13 AC11 AC9 AC8 AC5 AB30 AB28 AB12 AB10 AB7 AA31 AA29 AA27 AA13 AA11 AA9 AA6 AA4 AA1 Y30 Y28 Y12 Y10 Y8 Y5 C B ZIF-SOCKET1331-HF A A Title AM4 GND MICRO-START INT'L CO.,LTD Size Document Number Custom MS-7C30 Tuesday, November 13, 2018 Sheet of 56 10 Rev DIMMA1A A1 51 52 MA_DM7 MA_DM6 MA_DM5 D MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 132 133 MA_DM6 121 122 MA_DM5 110 111 MA_DM4 99 100 MA_DM3 40 41 MA_DM2 29 30 MA_DM1 18 19 MA_DM0 197 196 3 C MA_DQS_H7 MA_DQS_L7 3 MA_DQS_H6 MA_DQS_L6 3 MA_DQS_H5 MA_DQS_L5 3 MA_DQS_H4 MA_DQS_L4 3 MA_DQS_H3 MA_DQS_L3 3 MA_DQS_H2 MA_DQS_L2 3 3 3 3 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H0 MA_CLK_L0 MA_DQS_H7 MA_DQS_L7 278 277 MA_DQS_H6 MA_DQS_L6 267 266 MA_DQS_H5 MA_DQS_L5 256 255 MA_DQS_H4 MA_DQS_L4 245 244 MA_DQS_H3 MA_DQS_L3 186 185 MA_DQS_H2 MA_DQS_L2 175 174 MA_DQS_H1 MA_DQS_L1 164 163 MA_DQS_H0 MA_DQS_L0 153 152 MA_CLK_H1 MA_CLK_L1 218 219 MA_CLK_H0 MA_CLK_L0 74 75 235 237 93 3 B MA0_CS_L1 MA0_CS_L0 3 MA0_CKE1 MA0_CKE0 3 MA0_ODT1 MA0_ODT0 MA0_CS_L1 MA0_CS_L0 89 84 MA0_CKE1 MA0_CKE0 203 60 MA0_ODT1 MA0_ODT0 91 87 199 54 192 47 201 56 194 49 MA_RESET_L MA_EVENT_L MA_ALERT_L 3 MA_RESET_L 58 MA_EVENT_L 78 MA_ALERT_L 208 MA_ACT_L MA_ACT_L MA_PAROUT MA_PAROUT 62 222 230 VCC_DDR A 1KR/4 MA_EVENT_L DQS15P DQS15N DQS14P DQS14N DQS13P DQS13N DQS12P DQS12N DQS11P DQS11N DQS10P DQS10N DQS9P DQS9N DQS8P DQS8N DQS7P DQS7N DQS6P DQS6N DQS5P DQS5N DQS4P DQS4N DQS3P DQS3N DQS2P DQS2N DQS1P DQS1N DQS0P DQS0N CK1P CK1N CK0P CK0N C2 S3_N_C1 S2_N_C0 BG-1 BG-0 S1_N S0_N BA-1 BA-0 CKE1 CKE0 A17 A16_RAS_N A15_CAS_N A14_WE_N A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ODT-1 ODT-0 CB-7 CB-6 CB-5 CB-4 CB-3 CB-2 CB-1 CB-0 RESET_N EVENT_N 280 135 273 128 282 137 275 130 269 124 262 117 271 126 264 119 258 113 251 106 260 115 253 108 247 102 240 95 249 104 242 97 188 43 181 36 190 45 183 38 177 32 170 25 179 34 172 27 166 21 159 14 168 23 161 16 155 10 148 157 12 150 MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA52 MA_DATA53 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA36 MA_DATA37 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA20 MA_DATA21 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA4 MA_DATA5 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 207 63 MA_BG1 MA_BG0 224 81 MA_BANK1 MA_BANK0 234 82 86 228 232 65 210 225 66 68 211 69 213 214 71 216 72 79 MA_ADD_17 MA_RAS_L MA_CAS_L MA_WE_L MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 141 285 SMB_CLK_DIMM SMB_DATA_DIMM 56~63 D 48~55 40~47 32~39 24~31 C 16~23 8~15 Vinafix.com 0~7 MA_BG1 MA_BG0 MA_BANK1 MA_BANK0 3 3 MA_ADD_17 MA_RAS_L MA_CAS_L MA_WE_L B MA_ADD[13 0] ALERT_N ACT_N SCL SDA PAR SAVE_N_NC SA-2 SA-1 SA-0 RFU-0 RFU-1 RFU-2 238 140 139 A DIMM1(CHANNEL-A)-A0 ADDRESS = 0:0 [SA1:SA0] DDRIV-288P_BLACK-RH-21 R263 144 205 227 DQS16P DQS16N ✗ MA_DM7 DQ-63 DQ-62 DQ-61 DQ-60 DQ-59 DQ-58 DQ-57 DQ-56 DQ-55 DQ-54 DQ-53 DQ-52 DQ-51 DQ-50 DQ-49 DQ-48 DQ-47 DQ-46 DQ-45 DQ-44 DQ-43 DQ-42 DQ-41 DQ-40 DQ-39 DQ-38 DQ-37 DQ-36 DQ-35 DQ-34 DQ-33 DQ-32 DQ-31 DQ-30 DQ-29 DQ-28 DQ-27 DQ-26 DQ-25 DQ-24 DQ-23 DQ-22 DQ-21 DQ-20 DQ-19 DQ-18 DQ-17 DQ-16 DQ-15 DQ-14 DQ-13 DQ-12 DQ-11 DQ-10 DQ-9 DQ-8 DQ-7 DQ-6 DQ-5 DQ-4 DQ-3 DQ-2 DQ-1 DQ-0 ✖ MA_DATA[63 0] DQS17P DQS17N Footprint MICRO-START INT'L CO.,LTD 6,41,51 6,41,51 SCLK0 SDATA0 SCLK0 SDATA0 R427 R431 0R/4 0R/4 SMB_CLK_DIMM SMB_DATA_DIMM Title SMB_CLK_DIMM SMB_DATA_DIMM DDR4 DIMM CH-A 11 11 Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 10 of 56 FOR CPU 1.8V S5 0.5A 5VDUAL_1P8 FOR VCCP_SOC_S5 5VDUAL 5VDUAL_1P8 30L5A-10-RH 5VDUAL_1P8 R479 10K 0.9A 5VDUAL_1P8 2147_MODE2 13 R472 47KR/4 R469 X_10KR/4 CPU_1P8_S5_EN 0.5A + 2.0A + 0.9A =3.4A 6,34,37,39,40 APU_AM4R1 D21 S-LRB520S-40T1G C394 C330p50X4 CPU_1P8_S5 MODE/VCON Ramp FB GND R448 1KR1%/4 R1 CPU_1P8_S5_FB VFB=0.6 R2 R449 487R1%4 12 0.1u16X CPU_1P8_S5 OUT PG 0.1u16X 2147_MODE2 EN D C419 2.0A CPU_1P8_S5_PG CPU_1P8_PHASE C387 40,45 SW-1 SW-2 C22u6.3X6 C423 0.1u16X VIN-1 VIN-2 L17 1.0u4.5A20mS-HF C22u6.3X6 0.1u16X CPU_1P8_S5 OCP:4A C377 C430 U42 C372 FOR CPU 1.8V S0 C434 C22u6.3X6 D L19 MP2147GD-Z_QFN12 CPU_1P8_S5_EN Vout = Vref * (1 +(R1/R2)) = 0.6 * (1 +(1K/487)) = 1.83V 3VSB R1491 10K ENABLE HIGH:1.6V CPU_1P8_S5_EN C R445 X_3.3KR1%/4 C C400 0.1u16X Vinafix.com CPU_1P8_S5 OCP:5A U33 VCC3 B C350 C347 ATX_5VSB C22u6.3X6 C22u6.3X6 VIN1-1 VIN1-2 R379 47KR/4 R389 10K Q89 2N7002D C352 X_1u6.3X Q77 2N7002D 6,22,27,34,35,37,40 SLP_S3# G2 G2 39 CPU_VDDP_EN D2 VCC3 CPU_1P8_EN ON1 ON2 VBIAS CT1 CT2 CPU_1P8 B CPU_1P8 12 10 11 GND 15 Thermal Pad C339 X_C22u6.3X6 C342 C4700p25N04 C332 1u6.3X/4 TPS22976DPUR_WSON14-HF S2 C357 0.1u16X C353 0.1u16X S1 S2 G1 Adijustable Rise Time SR = 0.42*CT+66 SR is the slew rate in (µs/V) CT is constant value on CT pin (in pF) The units for the constant 66 is in (µs/V) S1 DDR_PWRGD CPU_1P8_EN D1 G1 D1 37,40 D2 VIN2-1 VIN2-2 13 VOUT1-1 14 VOUT1-2 VOUT2-1 VOUT2-2 DDR_PWRGD > CPU_VDDP_EN DDR_PWRGD > CPU_1P8 A A MICRO-START INT'L CO.,LTD Title CPU Power 1P8V-MP2147 Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 38 of 56 Input Current= (8.5A*1.05V)/12V/0.8=0.93A CPU_VDDP_S0 1.05V/0.9V@S0:8.5A OCP=14A S0:8.5A S5:1A +12V_VDDP +12V CHOKE21 CH-0.47u7A10.5m OCP=14A D C1835 0.1u16X4 C1842 22u16X/8 C1829 22u16X/8 D C1833 22u16X/8 1.05V,8.5A VCC3 R2293 10KR/4 40 R2357 CPU_VDDP_PG 20171215 VCCSA_PG disconnect MP8712_VCC pull up VCC3 0R/4 CPU_VDDP_PG_R VDDP_VCC 3.5V output C1972 0.1u16X/4 ▼ CPU_VDDP_EN EN H 1.2V +12V_VDDP 6,34,37,38,40 C1831 C0.47u16X5/4 12-27 C1837 C0.022u25X/4 VIN BST EN SW PG VOUT VCC CPU_VDDP_BOOT CPU_VDDP_BOOT_R 0R/6 C1845 C0.1u25X/4 CHOKE17 CH-1.0u11A6.8mS-HF CPU_VDDP_SW CPU_VDDP_SENSE_R 10 C1802 0.1u16X4 CPU_VDDP_FB_R 11 FB R2321 R2294 10KR/4 CPU_VDDP_FB C1803 C1844 C1843 C1828 C1841 C22u6.3X6 C22u6.3X6 C22u6.3X6 C22u6.3X6 X_C22u6.3X6 R2358 X_1R1%6 SS PGND NC-1 NC-2 NC-3 C1998 X_3300p50X 14 AGND CPU_VDDP_EN D48 S-LRB520S-40T1G APU_AM4R1 13 12 R2297 100K1%4 CPU_VDDP U132 CPU_VDDP MP8712 C1971 X_0.1u16X/4 R2298 39.2KR1%/4 C I9C-8712G0C-M03 C R358 6.8R1%4 C1838 TYPE0_CPU_SEL: 1:TYPE 0:TYPE G2 TYPE0_CPU_SEL VDDP_SEL 5,6,28,39,40,45 BR B S2 VDDP_SEL 38 Vinafix.com S1 R2300 X_47K/4 TYPE0_CPU_SEL NA TYPE1_CPU_SEL 0 RV/ZP C1846 AM4_CPU_SEL 0:Type 0/1 =>1.053V 1:Type 2/3 =>0.9V CPU_VDDP_EN SR 0R/4 CPU_VDDP_SENSE CPU_VDDP_FB 5,6,28,39,40,45 16 Q66 2N7002D G2 C0.1U16X/4 R3 R2303 3.83K1%/4 R2345 2K1%/4 R2 Type 0/1: Vout = Vref * (1 +(R1/(R2//R3)) = 0.6 * (1 +(1K/(2K//3.83K)) = 1.056V D2 D1 PM_GPIO_R9 S2 G1 TYPE1_CPU_SEL PM_GPIO_R9 Page 17 pull high 1:Type 0/1 1.05V 0:Type 2/3 0.9V Type 2/3: Vout = Vref * (1 +(R1/R2)) = 0.6 * (1 +(1K/2K)) = 0.9V NOT SUPPORT TYPE2 CPU VDDP VDDP_VSB_FB 1.05V/0.9V S5:1A ATX_5VSB R3 Input Current=0.04A 5VDUAL 3VSB C1407 C319 VDDP_VSB_PG VIN EN PG C1840 X_C0.1u16X/4 MP2143 has an open drain with 500kΩ pull-up resistor pin for power good (PG) indication VDDP_VSB_PHASE SW OUT FB D2 CPU_VDDP_S5 U131 VDDP_VSB_VIN VDDP_VSB_EN Q44 2N7002D G2 D1 I9C-2143D09-M03 C22u6.3X/6 11-15 C1u6.3X/4 C1839 C0.1u16X/4 PGND AGND R2340 10K/4 R2342 X_10K/4 default:0.775V,0.2A L16 L02-3008043-M26 30L5A R2341 1KR1%/4 VDDP_VSB_FB FB: 0.6V R2 5,6,28,39,40,45 Type 2/3: Vout = Vref * (1 +(R1/R2)) = 0.6 * (1 +(1K/2K)) = 0.9V TYPE1_CPU_SEL G1 AM4_CPU_SEL 0:Type 0/1 1:Type 2/3 C283 C22u6.3X/6 Type 0/1: Vout = Vref * (1 +(R1/(R2//R3)) = 0.6 * (1 +(1K/(2K//3.83K)) = 1.058V S2 L15 1.0u4.5A20mS-HF R1 MP2143DJ R2343 3.83KR1%/4 VDDP_VSBFB R2339 47K/4 C301 C22u6.3X/6 S1 5VDUAL 12-27 40 B 1 CPU_VDDP_S5 A R362 1KR1%/4 R1 CPU_VDDP_EN R2344 ATX_5VSB TYPE1_CPU_SEL: 0:TYPE 1:TYPE TYPE CPU_VDDP_EN G1 TYPE1_CPU_SEL CPU D2 D1 CPU_VDDP_SENSE_R C22p50N/4 S1 6,7,40 CPU_VDDP_EN: 0:TYPE 1:TYPE Q340 2N7002D A C298 C0.22u6.3X/4 R285 2KR1%/4 MICRO-START INT'L CO.,LTD Title CPU Power VDDP-RT8125E Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 39 of 56 VRM_Enable circuit 6,34,37,38,39 D10 APU_AM4R1 6,22,27,34,35,37,38 2018-01-02 S-LRB520S-40T1G VR10 47KR/4 VQ2 NN-2N7002DW G2 D2 2018-01-02 VR132 X_22KR/4 VR120 47K/4 VR25 S2 VQ9 1KR/4 VC23 0.1u16X RT8894_EN_C G1 RT8894_EN_R NN-CMKT3904 G S Q93 NN-2N7002DW G2 D2 TYPE0_CPU_SEL 5,6,28,39,45 CPU ALL POWER GOOD MUX BR TYPE NA 3VSB co-lay 3VSB Vinafix.com CPU VDDP NOT SUPPORT TYPE2 3VSB R460 4.7K R461 4.7K R851 X_0R/4 R850 0R/4 C D D C 37,38 SYSREST# D22 X_S-LRB520S-40T1G D23 X_S-LRB520S-40T1G C411 6,7,35,47 B D1 DDR_PWRGD ALL_PWR_MUX 41 16,35 CHIP_PWGD VRM_VRDY PM_PWRGD S-LRB520S-40T1G D25 S-LRB520S-40T1G D26 S-LRB520S-40T1G S1 TYPE1_CPU_SEL TYPE0_CPU_SEL 0 SR 1 RV/ZP VCC ALL_PWR_PWRGD Y B D24 C R382 X_8.2KR/4 U40 A GND 22 0.1u16X VDDP_SEL1 G1 TYPE1_CPU_SEL TYPE1_CPU_SEL: 0:TYPE 1:TYPE VCC3 CPU_VDDP_EN: 0:TYPE 1:TYPE S2 VQ1 2N7002 C VCC3 D 12*(3/12.1)=2.975V >1V VDDP_SEL1 VCC3 41 VC2 C0.1u16X/4 Make sure +12VIN connector plug in 6,7,39 D CPU_VDDP_PG VR3 3KR1%0402 VC9 100p50N VR131 47K/4 TYPE0_CPU_SEL: 1:TYPE 0:TYPE 39 RT8894_EN D1 RT8894_EN_R CPU_1P8 VR1 22KR/4 VR2 9.1KR1%0402 S1 D S-LRB520S-40T1G +12VIN VCC3 VCC5 ATX_5VSB D52 SLP_S3# ATX_5VSB NC7SZ08M5X_SOT23-5 R441 100KR/4 When you use external buffer then you cannot let APU PWR_GOOD pin float in any sleep state If you're buffer use 3.3V_S0 and you need Pull-down 100K If you're buffer use 3.3V_S5 and you don't need PD B To SPI POK_CTRL# use ALL_PWR_MUX S0 PG S5 PG ATX_5VSB 38,45 CPU_1P8_S5_PG NB_S5_PG 6,22 Q76 2N7002 NB_S5_PG G1 S1 VDDP_VSB_PG RSMRST# D G S D1 S2 39 VR55 47KR/4 Q11 NN-2N7002DW G2 D2 A A MICRO-START INT'L CO.,LTD Title CPU PWR-IR3599 Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 40 of 56 Note:VID Override Circuit BOOT VOLTAGE VCC5 12VIN CPU_1P8 Pre_PWROK VRM_VRDY 0R VRMEN 42 VRM_VRDY VR12 0R VRDY 43 VR19 VR31 VR28 VRM_POK X_220R X_220R X_220R VCORE VR54 100R1% VR59 VDDCR_CPU_SENSE+ VC10 VC12 VDDCR_CPU_SENSE- VDDCR_SOC_SENSE- Diff pair C150p50N/4 X_C3300p50X4 VR21 SCLK0 SDATA0 VSEN VR56 VR57 VR58 RLL=1.3mohm 10K/1% VR34 0R X_0R VR33 VCCP_NB VDDCR_SOC_SENSE+ 100R1% VR42 0R VSENA VR43 VC16 VC18 C150p50N0402 X_C3300p50X4 VR46 VR48 100R1% VR_HOT# 30 VRM_SVC VRM_SVD VRM_SVT 23 24 25 26 27 VR29 VR24 0R 0R SCLK_RT8894 SDATA_RT8894 VR36 VC8 0R 0.1u16X VCORE_SEN 14 32.4KR1%0402 VCORE_COMP 16 VR32 340R1%0402 0R VC24 VR37 VR51 VR40 VR38 VR53 22 PROCHOT# VSEN 0R Diff pair C SCLK_RT8894 SDATA_RT8894 VR15 68p50X 0R 100R1%4 0R X_100R1%4 VCORE_FB 15 VC13 17 RGND X_C3300p50X4 VCCP_NB_SEN VR41 VSENA VC15 RLL=2.1mohm 10K/1% VR44 VR45 43KR1%0402 0R VR47 0R VC20 X_0R 0R X_C3300p50X4 2.05KR1%0402 VCCP_NB_COMP 68p50X VCCP_NB_FB VCORE_TSEN VCCP_NB_TSENA 100KR1% VR_IBIAS VR50 VR86 37 35 36 1u6.3X6 VC27 21 PWROK 31 34 VR_HOT# 1KR/4 VCORE_IMON 18 VCCP_NB_IMONA 20 VR16 133KR1% 44 VR60 133KR1% 47 BOOT1 48 UGATE1 49 PHASE1 50 LGATE1 ISEN1P ISEN1N OCP_L/VR_HOT SVC SVD SVT SCL SDA 54 BOOT2 53 UTAGE2 52 PHASE2 51 LGATE2 ISEN2P ISEN2N VSEN COMP BOOT3 UGATE3 PHASE3 56 LGATE3 10 ISEN3P 11 ISEN3N FB RGND VSENA PWM4 13 ISEN4P 12 ISEN4N COMPA FBA 46 41 ISENA1P 40 ISENA1N TSEN TSENA PWMA2 IBIAS 45 38 ISENA2P 39 ISENA2N VRM_VRDY 10K TONSET PWMA1 33 D RTON Fsw=300kHz TONSETA IMON SET1 IMONA SET2 B VRT2 47KRT1% VC29 1u6.3X VCORE_TSEN- CP1 CP2 X_COPPER VCCP_NB_TSENA VR80 VR79 1.62KR1%0402 910R1%0402VCC5 VC26 1u6.3X RIMON3 3.9KR1% VR81 VCORE_ISEN3P ISEN3N VR39 VC14 C VCORE_ISEN3P VCORE_ISEN3N 680R/1% 0.1u16X 42 42 Close to PWM VCORE_PWMA4 VCORE_PWMA4 VCORE_ISEN4P ISEN4N VR123 VC58 43 VCORE_ISEN4P VCORE_ISEN4N 680R1%/4 43 43 20170413 C0.1u16X/4 VCCP_NB_PWMA1 VCCP_NB_PWMA1 VCCP_NB_ISEN1PA ISEN1NA VR49 VC22 44 VCCP_NB_ISEN1PA VCCP_NB_ISEN1NA 680R/1% 0.1u16X 44 44 Close to PWM VCCP_NB_PWMA2 VCCP_NB_PWMA2 VCCP_NB_ISEN2PA ISEN2NA VR52 VC21 Close to PWM VR76 VR78 VR77 VR69 44 VCCP_NB_ISEN2PA VCCP_NB_ISEN2NA 680R/1% 0.1u16X 60.4KR1% 22.1KR1% 127K/1% 2.2K/1% 44 44 VDD OCP 140A, VNB OCP=90A VR121 VR122 2.1KR1% 133R1% VCC5 VCC5 B For VCORE, OCP=200A, TDC=95A, EDC=140A For NB, OCP=90A, EDC=75A.TDC=50A VREF VCCP_NB_NTCN 0R VR63 0R 200R1% VRT4 47KRT1% VR70 A VR65 21.5KR1%0402 RIMON2 VR83 VCORE_BOOT3 42 VCORE_UG3 42 VCORE_PH3 42 VCORE_LG3 42 close to PWM VR66 100R1%0402 VCORE_NTCP 42 42 VC28 1u6.3X VR82 8.2KR1%0402 VRT3 47KRT1% VCORE_ISEN2P VCORE_ISEN2N 680R/1% 0.1u16X Close to PWM X_COPPER A close to phase1 CHOKE VCORE_ISEN2P ISEN2N VR62 VC11 VCCP_NB_TSENA- VREF VR84 42 42 VCORE_BOOT2 42 VCORE_UG2 42 VCORE_PH2 42 VCORE_LG2 42 VCORE_SET2 SMB Address: 0X40 close to PWM VCORE_NTCN VCORE_ISEN1P VCORE_ISEN1N 680R/1% 0.1u16X Close to PWM Close to PWM Close to MOSFET 910R1%0402VCC5 VC57 1u6.3X VCORE_ISEN1P VR22 ISEN1N VC7 VCORE_SET1 ◆ VR64 1.62KR1%0402 12VIN VCORE_BOOT1 42 VCORE_UG1 42 VCORE_PH1 42 VCORE_LG1 42 29 ◆ VRT1 47KRT1% VR85 12VIN SET1 control ICCMAX,OCP setting SET2 control Internal compensation Close to PWM VCORE_TSEN 1R/1% 0.1u16X 1R/1% 0.1u16X Fsw=255kHz 28 VR_HOT# pull low when T>124 VR_HOT# pull high when T drop to 90 Choose VRHOT_LOW=51%*VCC and VRHOT_HYS=5%*VCC Close to MOSFET VR20 VC25 VR61 VC6 RT8894A 57 VR_VDDIO VR87 PGOOD Close to IC Vinafix.com VCC3 EN VC5 0.47u16X6 V064 40 RT8894_EN VDDIO X_2.2K/4 RT8894_EN 6,10,51 6,10,51 X_22p50N X_22p50N VR_PVCC 1KR/4 40 VC4 VR7 1KR/4 VU1 VRM_SVC VRM_SVD VRM_SVT VRM_POK 0R0402 0R0402 0R0402 0R0402 55 VR18 1KR/4 VC3 1u6.3X6 VREF 19 2.2u16X6 VR6 2.2R/8 PVCC VR30 VR26 VR35 VR23 VR8 VR67 design check VC19 VC17 VR5 2.2R/8 VR_VCC D APU_SVC APU_SVD APU_SVT APU_PWROK VR4 2.2R/8 CPU_1P8 VR_VDDIO 1.1 1.0 0.9 0.8 GND 1 32 0 1 SVD Metal VID VCC SVC close to phase1 CHOKE RIMON1 7.32KR1% RIMON2 VR71 10R1% VCORE_IMON VCCP_NB_NTCP VR72 RIMON3 10.7KR1% VR73 VR68 130R1%0402 10R/1% VR74 MICRO-START INT'L CO.,LTD RIMON1 16KR1%/4 VCCP_NB_IMONA 430R1%0402 VR75 Title CPU Power RT8894 4+2 Phase Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 41 of 56 VCORE 95W TDC:80A EDC:125A VCORE 65W TDC:65A EDC:95A VCORE_UG1 41 VCORE_BOOT1 D VCORE_UG1_R VR94 0R/6 VR89 2.2R/8 VQ13 VC33 C1u16X6 VC31 C10u16X8 D VR103 10K 0.00625V~1.55V N-PK616BA VC30 0.1u16X25/4 0R/6 VCORE_LG1_R VQ15 VCORE_LG1_R VQ16 VR100 2.2R1% VC42 C1000p50X4 N-PK632BA N-PK632BA D03-632BA0C-N03 CHOKE5 CH-0.3u50A0.6m-HF VCORE D03-632BA0C-N03 VR105 VCORE X_COPPER X_COPPER ISEN1+ VR139 VCORE_LG1 41 D03-616BA0C-N03 CP11 VCORE_PH1 CP12 41 Close to IC VC44 C 41 VCORE_UG2 VCORE_BOOT2 VR101 0R/6 VR92 2.2R/8 VCORE_UG2_R VCORE_ISEN1P 41 VCORE_ISEN1N 560u6.3SO EC42 1+ 560u6.3SO EC45 1+ 560u6.3SO EC46 1+ 560u6.3SO EC47 1+ 560u6.3SO EC48 1+ 560u6.3SO EC52 1+ 560u6.3SO 0.1u16X 12VIN 41 EC40 1+ 3KR1% VR133 3KR1% 41 12VIN 41 VR104 X_0R 20170416 C VQ14 VC43 C1u16X6 VC34 C10u16X8 VR102 10K N-PK616BA VC32 0.1u16X25/4 VCORE_LG2_R VCORE_LG2_R Vinafix.com VC39 C1000p50X4 N-PK632BA N-PK632BA D03-632BA0C-N03 D03-632BA0C-N03 VR97 VCORE X_COPPER X_COPPER VR95 2.2R1% ISEN2+ 0R/6 VQ18 CP15 VR140 VCORE_LG2 CHOKE6 CH-0.3u50A0.6m-HF CP17 41 VQ17 VCORE_PH2 41 D03-616BA0C-N03 Close to IC 3KR1% VR134 3KR1% VC40 0.1u16X B B 41 VCORE_ISEN2P 41 VCORE_ISEN2N VR96 X_0R 12VIN VCORE_BOOT3 VR88 0R/6 VR93 2.2R/8 VCORE_UG3_R VR90 10K VC37 0.1u16X25/4 VC35 C1u16X6 N-PK616BA VCORE_PH3 0R/6 VCORE_LG3_R VCORE_LG3_R VC38 C1000p50X4 A N-PK632BA N-PK632BA D03-632BA0C-N03 VCORE D03-632BA0C-N03 VR99 X_COPPER VR91 2.2R1% X_COPPER VQ11 CP20 VR141 VCORE_LG3 VQ12 CHOKE4 CH-0.3u50A0.6m-HF CP19 41 VC36 C10u16X8 D03-616BA0C-N03 41 VQ10 ISEN3+ 41 VCORE_UG3 41 Close to IC A 3KR1% VR135 3KR1% VC41 MICRO-START INT'L CO.,LTD Title 0.1u16X CPU Power Phase 1-3 41 VCORE_ISEN3P 41 VCORE_ISEN3N VR98 Size Document Number Custom MS-7C30 X_0R Date: Rev 10 Sheet Tuesday, November 13, 2018 42 of 56 12VIN 12VIN VR124 5.1R1%/6 VC59 D 41 1 VCORE_PWMA4 VCC VU4 1u16X/6 BOOT UGATE PWM PHASE NC GND GND-PAD LGATE VCORE_BOOT4 VCORE_UG4 VCORE_PH4 VCORE_LG4 VCORE_UG4 VR125 0R/6 VCORE_BOOT4 VR130 2.2R/8 VCORE_UG4R VQ29 VC64 C1u16X/6 VC62 C10u16X/8 VR128 10K/4 D 0.75V~1.2V N-PK616BA VC63 0.1u16X25/4 VCORE_PH4 CHOKE16 CH-0.3u50A0.6m-HF D03-616BA0C-N03 0R/6 VCORE_LG4_R VCORE_LG4_R VC61 C1000p50X/4 N-PK632BA D03-632BA0C-N03 N-PK632BA D03-632BA0C-N03 VR129 VCORE L04-03A7151-L65 X_COPPER VR126 2.2R1% X_COPPER VQ28 ISEN4+ VR142 5 VCORE_LG4 VQ27 CP29 I33-9624F0C-R11 CP28 RT9624F Close to IC 3KR1% VR136 3KR1% VC60 41 VCORE_ISEN4P 41 VCORE_ISEN4N 0.1u16X VR127 X_0R/4 C C Vinafix.com B B A A MICRO-START INT'L CO.,LTD Title CPU Power Phase Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 43 of 56 VCCP_NB 95W TDC:50A EDC:75A VCCP_NB 65W TDC:50A EDC:75A D D 12VIN VR119 5.1R1%6 VC56 41 VCCP_NB_PWMA1 VCC VU2 1u16X6 BOOT UGATE PWM PHASE NC GND GND-PAD LGATE VCCP_NB_BOOT1 VCCP_NB_UG1 VCCP_NB_PH1 VCCP_NB_LG1 VCCP_NB_UG1 VR117 0R/6 VCCP_NB_BOOT1 VR116 2.2R/8 VCCP_NB_UG1R VQ20 12VIN VCCP_NB_UG1R VC55 C1u16X6 VC54 C10u16X8 VR118 10K N-PK616BA VC53 0.1u16X25/4 VCCP_NB_PH1 VQ24 0.00625V~1.55V N-PK616BA D03-616BA0C-N03 CHOKE7 CH-0.3u50A0.6m-HF D03-616BA0C-N03 VC52 C1000p50X4 N-PK632BA N-PK632BA D03-632BA0C-N03 VCCP_NB D03-632BA0C-N03 X_COPPER VCCP_NB_LG1_R X_COPPER VR115 2.2R1% ISEN1A+ 0R/6 VCCP_NB_LG1_R 5 VR143 VQ22 CP16 VCCP_NB_LG1 VQ26 CP18 RT9624F Close to IC VR114 3KR1% C C VR137 3KR1% VC45 41 VCCP_NB_ISEN1PA 41 VCCP_NB_ISEN1NA 0.1u16X VR113 X_0R Vinafix.com VCCP_NB 12VIN VR112 5.1R1%6 VC48 VCC VU3 1u16X6 BOOT B 41 VCCP_NB_PWMA2 UGATE PWM PHASE NC GND GND-PAD LGATE VCCP_NB_BOOT2 VCCP_NB_UG2 VCCP_NB_PH2 VCCP_NB_LG2 VCCP_NB_UG2 VR110 0R/6 VCCP_NB_BOOT2 VR109 2.2R/8 VCCP_NB_UG2R VQ21 12VIN VCCP_NB_UG2R VC46 C1u16X6 560u6.3SO B N-PK616BA D03-616BA0C-N03 D03-616BA0C-N03 D03-632BA0C-N03 N-PK632BA D03-632BA0C-N03 ISEN2A+ 5 VC50 C1000p50X4 N-PK632BA VCCP_NB X_COPPER VCCP_NB_LG2_R VR106 2.2R1% X_COPPER VQ23 CP13 VCCP_NB_LG2_R VQ19 CHOKE8 CH-0.3u50A0.6m-HF CP14 RT9624F 0R/6 560u6.3SO EC50 1+ VC47 C10u16X8 VR144 560u6.3SO EC49 1+ VQ25 N-PK616BA VCCP_NB_LG2 560u6.3SO EC44 1+ VR111 10K VC49 0.1u16X25/4 VCCP_NB_PH2 EC43 1+ Close to IC VR108 3KR1% VR138 3KR1% VC51 41 VCCP_NB_ISEN2PA 41 VCCP_NB_ISEN2NA 0.1u16X VR107 X_0R A A MICRO-START INT'L CO.,LTD Title CPU Power NB Phase 1-2 Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 44 of 56 FOR VCCP_SOC_s5 0.9A (VDDCR_SOC_S5 is only used for AMD TYPE0) TYPE0 Only D S5_MUX_CTRL HIGH:S0 LOW: S3/S5 D (VDDCR_SOC_S5 is only used for AMD Family 15h Models 60h-6Fh processors) H: +VDDCR_FCH_ALW will track VDDNB L: If VDDCR_SOC= 0.775V (OR 0.85V) , VDDCR_SOC_S5 will track VDDCR_NB Bristol Ridge TYPE0 5VDUAL C442 C1u16X4 1.8V/3.3V R439 47KR/4 C376 R452 2.94KR1%/4 VCCP_NB Q83 G2 C409 X_0.1u16X D2 CPU_1P8_S5_PG G1 S1 38,40 S5_MUX_CTRL R408 1KR/4 VREF2 0.812V VREF1 VREF2 D1 S2 C 10u6.3X6 2N7002D R447 10K/1% VIN VCNTL U39 PM_1P05_S5 CPU_1P8_S5 5VDUAL VOUT VCCP_NB_S5 VREFSEL NC VREF1IN VREF2IN GND PAD 5,6,28,39,40 NCT3711S C378 C428 X_0.1u16X X_0.1u16X G2 TYPE1_CPU_SEL VREF1 VREF2 Q30 NN-2N7002DW D2 VREF2 D1 VREF1 S2 C G1 CPU TYPE S1 TYPE1_CPU_SEL: 0:TYPE 1:TYPE TYPE1_CPU_SEL TYPE0_CPU_SEL VCCP_NB_S5 C369 X_C22u6.3X6 C363 C22u6.3X6 C392 10u6.3X6 C385 X_4.7u10X6 Vinafix.com BR NA 0 SR 1 RV/ZP CPU VCCP_NB_S5 ONLY SUPPORT TYPE0 B B A A MICRO-START INT'L CO.,LTD Title CPU Power NB Switch Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 45 of 56 D D C C Vinafix.com CPU POWER CONNECTOR B CHOKE1 CH-0.3u50A0.6m-HF 20170416 For NB EC1 270u16SO EC16 270u16SO 2 EC51 270u16SO + EC28 270u16SO + EC10 270u16SO + + PWRCONN4P_BLACK-RH-3 1 For Vcore 12VIN 1 + GND +12VIN 12V GND 12V CPU_PWR1 MEC1 B N93-04M0441-H06 +12VIN A Irms = Iout * SQRT{D/N- (D)^2]} CORE: D=Vout/Vin=1.5/12=0.125 N=Phase number=4 =125A*SQRT(0.0315-0.0156) =15.769A C25 C0.1u16X4 NB: D=Vout/Vin=1.4/12=0.1166 N=Phase number=2 =75A*SQRT(0.0583-0.0136) =15.8A A Close Power Connector MICRO-START INT'L CO.,LTD Title RT9553B CURRENT SENSE Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 46 of 56 14 C324 C0.1u16X/4 15 SIO_PSON# SIO_PSON# R904 PS_ON# 0R0402 C323 22 16 0.1u16X 17 18 D18 X_ESD-0402-L 19 D 20 VCC5 21 C292 X_0.1u16X 22 23 24 3.3V SUS_LED 3.3V -12V 3.3V GND GND P_ON 5V GND GND GND 5V GND GND -5V POK 5V 5VSB 5V +12V 5V +12V GND 3.3V VCC3 C322 0.1u16X C778 X_0.1u16X VCC5 C326 VCC5 VCC5 0.1u16X D47 1N4148S A C PWR_LED R903 330R VCC5 JFP2 JFP1 R286 4.7K C271 X_0.1u16X C247 X_0.1u16X ATX_PWR_OK C782 22,27,34 6,7,35,40 R901 SYSREST# PLED HDD- SLED RESET- PWSW+ RESET+ PWSW- PWR_LED SPEAKER SUS_LED PWSW+ R891 100R/4 PWRBTIN RN4 22 150R/8P4R BUZZER_R D H1X4M_BLACK C766 C0.1u16X/4 C781 NC 0.1u16X H2X5[10]M_COLORS-RH B C770 X_C0.1u16X/4 R885 715R SPKR Q147 2N3904 EC38 560u6.3SO VCC5 + ATX_5VSB + RESET+ HDD+ X_0.1u16X VCC5 33R/4 VCC3 C193 C0.1u16X/4 12 PWRCONN24P +12V C211 HDD+ IDE_LED ATX_5VSB 10 11 X_C0.1u16X/4 C777 X_0.1u16X C X_0.1u16X E -12V 13 C325 VCC3 R361 10K ATX_PWR1 25 ATX_5VSB 25 EC24 100u16SO VCC3 VCC3 R872 5.1K/1%/4 R734 5.1K1%/4 ATX_5VSB Q145 Q101 C 52 R295 X_1KR/4 R737 5.1K1%/4 M.2_DAS M.2_DASR R264 1KR/4 6,14 SATA_LED# R880 5.1K/1%/4 IDE_LED C IDE_LED NN-CMKT3904_SOT363-6-RH NN-CMKT3904_SOT363-6-RH IDE_LEDC Vinafix.com close to output of IC X_Test_Point DDR_VPP X_Test_Point PM_1P05 5VDIMM 3VSB VPP25 PM_1P05 X_Test_Point X_Test_Point VCORE C471 C22u6.3X6 C470 X_C22u6.3X6 C469 X_22u6.3X6 C466 X_22u6.3X6 C468 C22u6.3X6 TPM_LPCCLK0 7,22 LPC_RST# 7,22 LPC_AD0 7,22 LPC_AD1 7,22 LPC_AD2 7,22 LPC_AD3 7,22 LPC_LFRAME# CPU_CORE X_Test_Point VCCP_NB CPU_NB X_Test_Point CPU_VDDP B JTPM1 TPM_LPCCLK0 LPC_RST# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_LFRAME# 11 13 1 LPC_SERIRQ VCC5 R2359 100KR/4 R881 330R/6 7,22 12 14 SUS_LED PWR_LED H2X7[10]M-2PITCH R878 X_1KR/4 PM_1P05_S5 3VSB R879 4.7K R873 4.7K PM_2P5V LED_VSB LED_VCC PM_1P05_S5 X_Test_Point Q144 CPU_V_1P5V X_Test_Point 22 PM_2P5V X_Test_Point VTT_DDR 22 VTT_DDR B X_Test_Point CPU_1P8 NN-CMKT3904_SOT363-6-RH X_Test_Point VCC_DDR VCC3 CPU_VDDP X_Test_Point CPU_1P8 CPU_V_1P5V VCC3 3VSB DRAM R874 1KR/4 3VSB VCCP_NB_S5 R890 CPU_1P8_S5 X_Test_Point 330R/6 C633 0.1u16X CPU_1P8_S5 VCCP_NB_S5 C634 0.1u16X 5VDIMM A A MICRO-START INT'L CO.,LTD Title ATX/Front Panel Size Document Number Custom MS-7C30 Date: Tuesday, November 13, 2018 Rev 10 Sheet 47 of 56 D D C C Vinafix.com B B A A MICRO-START INT'L CO.,LTD Title ALL LED Control Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 48 of 56 D D C C Vinafix.com B B A A MICRO-START INT'L CO.,LTD Title JRGB1/JRGB2 Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 49 of 56 HEAT SINK CPU Socket Simulation CPU2 PM_HS1 MEC1 X_JS3 SIM1 MEC1 X_PIN1*2 E95-0000022-C22 D D X_JS4 RETENTION MODULE SIM2 X_PIN1*2 X_JS1 MEC2 MEC2 SIM3 HS-0436-2490F X_PIN1*2 C C X_MH001 MH1 X_MH001 MH2 X_MH001 4 9 MH6 BAT1_X1 BAT-CR2032-RH HDMI HDMI LABEL G51-M1SPXXA-A09 MH4 Label Vinafix.com HDMI_LA1 UEFI1 Optics Orientation Holes MOS HS(VCORE) MANUAL PART 5010 X_MH001 X_MH001 FM1 FM2 FM8 X_FM120 X_FM120 X_FM120 FM3 FM4 FM7 X_FM120 X_FM120 X_FM120 MH5 4 MH7 PCB1 B B X_MH001 5020 7C30_10 PK0-07C3010-G37 OPT Configure BOM 601-7B84-A01 Function XXXX FM5 FM6 X_FM120 X_FM120 A A MICRO-START INT'L CO.,LTD Title BOM OPTION Size Document Number Custom MS-7C30 Date: Rev 10 Tuesday, November 13, 2018 Sheet 50 of 56 SIO_3VA Moat Cap change to SIO_3VA C1343 0.1u16X SIO_3VA 6,22 CPU_IN# PWRBTN# 0R/4 R1388 0R/4 VDD R1390 U123 R1481 47K/4 D INPUT0 OUTPUT0 INPUT1 OUTPUT1 10 R1382 0R/4 R1384 0R/4 D SLP_S5# 6,22,27,34,36,37 APU_SLP_S3# CPU TEST CASEOPEN# GND NC_1 NC_2 NC_3 OUTPUT2 INPUT3 INPUT2 11 12 SLG4R41485V C C RTC & Clear CMOS Circuit R768 VBAT1 1.5V VDDBT_RTC_DIS X_0R/4 R956 1KR/4 6,10,41 NC GND EN C714 C902 CLRCMOS_EN U67 GS7159S5-1P5 R742 R845 10K C727 X_1u6.3X B 22 VBAT C0.22u6.3X4 1u6.3X Z C740 1u6.3X R960 1KR/4 D1 R25 4.7K G1 6,10,41 R952 X_0R0402 RTC_CLK SDATA0 R954 X_0R0402 RTC_DATA R283 R284 2.2K/4 2.2K/4 RTC_CLK RTC_DATA CLRCMOS_EN R962 INTA# SDA GND OSC2 R677 C743 1u6.3X X_0R/4 Slave Address: 11010000 , Wite , D0 11010001 , Read , D1 B Y5 OSC1 Q105 32.768KHZ12.5p G2 VCC3 RTC_DATA RTC_CLK S2 SCLK0 G1 VCC3 C971 10p50N D2 D1 SDATA0 2N7002D X_1KR/4 S VDDBT_RTC_DIS SCL OSC1 22 C970 10p50N JBAT1 R1486 100R/4 H1X2M_BLACK-RH CLRCMOS_EN R26 X_4.7K CLRCMOS C745 X_1u6.3X G A Q100 X_P-PA002FMG D A SQW/INTB# X2 OSC2 CLRCMOS_EN RSMRST# C744 1u6.3X X1 VBAT S2 R900 100K/4 VCC 1337AGDVGI8_MSOP8-RH D43 S-BAT54C Q99 NN-2N7002DW D2 SCLK0 BAT-2P-RH-1 SIO_3VA G2 CUT_VBAT VDDBT_RTC_DIS 1KR/6 Y Vout X Vin S1 VBAT U124 V_BAT VDDBT_RTC_G BAT1 VBAT S1 4.5uA VBAT 20170413 PIN7floating PIN3 resever pull down Vinafix.com Placement Bottom Side MICRO-START INT'L CO.,LTD Title RTC Circuit Size Document Number Custom MS-7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 51 of 56 M.2 Connector H: PCIE2 M.2_TXN2_C M.2_TXP2_C C491 C0.22u6.3X/4 C1374 C0.22u6.3X/4 M.2_TXN1_C M.2_TXP1_C M2_RXP0 M2_RXN0 R430 R429 M.2_RXN0_C M.2_RXP0_C M2_TXN0 M2_TXP0 C1373 C0.22u6.3X/4 C1372 C0.22u6.3X/4 M2_TXN2 M2_TXP2 4 APU_GPP_TXN1 APU_GPP_TXP1 SATA ❖ H: PCIE0 ◗ APU_GPP_RXN1 APU_GPP_RXP1 4 0R/4 0R/4 7 D31 C R428 VCC3 6,52 M.2_TXN0_C M.2_TXP0_C CLK_M2_DN CLK_M2_DP 67 69 71 73 75 1K/4 M2_DET 4 APU_GPP_TXN2 APU_GPP_TXP2 6,52 R2336 CLK_REQ_M.2 APU_WAKER PLTRST_BU2#_M2 R423 0R/4 R2335 X_0R/4 0R/4 SCREW1 DEVSLP4 SCREW E2B-7984020-A89 16 STANDOFF PLTRST_BU2#_M2 19 CLK_REQ2_M.2 APU_WAKE# 6,16,19,20,24 VCC3 M2TEST H1 H2 H3 TP15 E2B-7B05010 E2B-7B05010 C E2B-7B05010 Footprint: H_R240D173_BR189_PT E2B-7B05010-A89 E2B-7B05010-A89 E2B-7B05010-A89 Vinafix.com SLOT-NGFFCARD67P_BLACK-HF-24 N15-0670330-L06 VDD-1 VDD-2 VDD-3 VDD-4 VDD-5 VDD-6 VDD-7 VDD-8 30 M2_DET M2_TXP0 M2_TXN0 10 11 M2_RXP0 M2_RXN0 14 15 A L: SATA H: PCIE0 76 L: SATA AOa+ AOa- AI+ AI- BOa+ BOa- BI+ BI- AOb+ AObBOb+ BOb- SEL (default) ❱ COa+a- name ❯ ❚ M.2_DET: 0:M.2 SATA 1:M.2 PCIE GND COa+ COa- CI+ CI- DOa+ DOa- DI+ DI- COb+ CObDOb+ DOb- 37 36 GPP_RXN2 GPP_RXP2 33 32 GPP_TXN2 GPP_TXP2 M2_RXN2 M2_RXP2 M2_TXN2 M2_TXP2 H: PCIE2 28 27 24 23 12 13 16 17 APU_GPP_TXP0 APU_GPP_TXN0 4 APU_GPP_RXP0 APU_GPP_RXN0 4 PI3PCIE3415ZHE_TQFN42 H: PCIE0 A PIN 69 Low SATA NC PCIE I98-M14800C-AD0 MICRO-START INT'L CO.,LTD Title M2 Size Document Number Custom MS-7C30 Date: D C0.1u16X/4 19 21 26 31 34 39 41 U36 GND-1 GND-2 GND-3 GND-4 GND-5 GND-6 GND-7 GND-8 GND-9 GND-10 APU_GPP_RXN2 APU_GPP_RXP2 C516 B C495 18 20 22 25 29 35 38 40 42 43 4 C522 VCC3 L: SATA H: PCIE2 TYPE2: PCIE/SATA TYPE0: SATA MEC1 76 77 M.2 Switch C526 47 X_0R/4 DEVSLP4_R 68 NC-1 SUSCLK(32kHz) (O)(0/3.3V) 70 PEDET (NC-PCIe/GND-SATA) 3.3Vaux-7 72 GND-12 3.3Vaux-8 74 GND-13 3.3Vaux-9 GND-14 77 PIN 69 Low SATA NC PCIE B M.2_DAS KEY M ESD-SFI0402 C525 10K/4 M.2_DAS R425 C524 Screw C0.22u6.3X/4 C0.22u6.3X/4 M2_RXN2 M2_RXP2 R426 C0.1u16X/4 C0.1u16X/4 C0.1u16X/4 C0.1u16X/4 C0.1u16X/4 C0.1u16X/4 C492 C424 APU_GPP_TXN3 APU_GPP_TXP3 M.2_DAS C523 10u6.3X/6 Screw M.2_TXN3_C M.2_TXP3_C C520 10u6.3X/6 C0.22u6.3X/4 C0.22u6.3X/4 C496 Screw C494 C493 GND-1 GND-2 PERn3 PERp3 GND-3 PETn3 PETp3 GND-4 PERn2 PERp2 GND-5 PETn2 PETp2 GND-6 PERn1 PERp1 GND-7 PETn1 PETp1 GND-8 PERn0/SATA-B+ PERp0/SATA-BGND-9 PETn0/SATA-APETp0/SATA-A+ GND-10 REFCLKN REFCLKP GND-11 4 APU_GPP_RXN3 APU_GPP_RXP3 MEC2 4 VCC3 3.3Vaux-1 3.3Vaux-2 NC-2 NC-3 10 DAS/DSS# (IO) 12 3.3Vaux-3 14 3.3Vaux-4 16 3.3Vaux-5 18 3.3Vaux-6 20 NC-4 22 NC-5 24 NC-6 26 NC-7 28 NC-8 30 NC-9 32 NC-10 34 NC-11 36 NC-12 38 DEVSLP 40 NC-13 42 NC-14 44 NC-15 46 NC-16 48 NC-17 50 PERST# (O)(0/3.3V) or N/C 52 CLKREQ# (IO)(0/3.3V) or N/C 54 PEWake# (IO)(0/3.3V) or N/C 56 NC-18 58 NC-19 MEC2 D 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 MEC1 VCC3 M2_1 ❙ 3.3V@2.5A 3.3V@2.5A ❘ Rev 10 Sheet Tuesday, November 13, 2018 52 of 56 ... 15,30 D1 R395 R403 R404 R409 S2 L53 15 PS2_USB1A KBDAT MSDAT KBCLK MSCLK KBD MSD KBC MSC 33R/4 33R/4 33R/4 33R/4 KBData MSData KBClock MSClock VCC-3 PM_USB13+ 15 PM_USB13- PMUSB13+ PMUSB13- MINIDIN_USBX2-RH-14... D KBRST# ESPI_EN KBDAT KBCLK MSDAT MSCLK KBC Function GP54/SLP_SUS# DPWROK DSW Interface DEEP_S5_1/CASEOPEN1# USBEN/3VSBSW/PWROK/ATXPGDO KBRST# KBDAT KBCLK MSDAT MSCLK 27 27 27 27 0R/4 0R/4 R744... Number Custom MS- 7C30 Date: Rev 10 Sheet Tuesday, November 13, 2018 20 of 56 D D C C Vinafix.com B B A A MICRO-START INT'L CO.,LTD Title DP to VGA RT6516 Size Document Number Custom MS- 7C30 Date: