Compal LA8661P rev 0 1

A B C D E 1 Compal Confidential 2 Lotus M/B Schematics Document 14": Elise; 15.6" Exige Intel Ivy Bridge ULV Processor with DDRIII + Panther Point Date : 2011/10/27 Version 0.1 3 4 2011/06/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Block Diagrams Size Document Number Custom Rev 0.1 LA-8551P Date: Friday, March 02, 2012 Sheet E of 55 A B C D E Compal Confidential Model Name : Lotus 128Mx16 2011/11/01 PEG 3.0 x16 (2 x8) AMD VRAMx8pcs 128Bit DDRIII P28, P29 DDR3 1333/1600MHz 1.5V DDR3L 1333MHz 1.35V Intel IVY Bridge File Name : LA8661P BANK 0, 1, 2, P12, P13 Dual Channel ULV Processor FCBGA 1023 Thames-XT 25W DDR3-SO-DIMM X 31mm*24mm P22~ P29 P5~ P11 FDI x8 HDMI Conn LVDS Conn DDPB port P30 DMI x4 100MHz 100MHz 2.7GT/s 5GT/s port1,3 port0,2 P35 100MHz X1 X1 X1 port1 P34 JMINI1 WLAN&BT (mini card) port1 P31 port5 port9 X1 RJ45 3.3V 24MHz port8 HD webcam SPI D-MIC(daul) HDA Codec LPC BUS SATA HDD IDT 92HD91 BIOS SPI ROM, 4MB +2 MB P38 P14 33MHz P33 X1 3.3V 48MHz HD Audio P14~ P21 port0 JMINI2 m-SATA (mini card) X2 X1 25mm*25mm (GEN1 1.5Gb/S GEN2 3Gb/S GEN3 6Gb/S) port0 USB 2.0 x4 PCH 989pin BGA 100MHz SATAx2 X2 USB 3.0 x2 Intel Panther Point PCI-Express x (PCIE2.0 5GT/s) X1 USB2.0 x1 port1 USB charger USB3.0 x2 P32 LVDS(1Ch/2ch) HDMI Card Reader /LAN controller RTL8411 Daughter board P33 SPK conn X1 P41 USB 2.0 x2 SD socket Sub Woofer Amp P39 HP Amp Sub Woofer conn P39 HP&MIC jack S/B P40 P34 TPM1.2 SLB9635/9656 Daughter board Accelerometer HP3DC2 P42 P42 Daughter board FAN conn P37 Touch pad daughter board ENE KB932 P36 PS2 LED P37 RTC CKT P14 Power On/Off CKT Lid switch S/B Touch Pad P37 SPI Int.KBD P37 EC ROM, 256kB P36 FAN/LED P37 P37 SM_BUS (PCH) DC/DC interface CKT.P43 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/29 2011/06/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Block Diagrams Size Document Number Custom Rev 0.1 LA-8551P Date: Sheet Friday, March 02, 2012 E of 55 A B C QAU30/50 (LA-8661P Ver:0.1) S1 Description S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.05VS_VCCP +V1.05SP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF +VCCP (1.05V ) power for PCH ON OFF OFF +VCCP SLP_S1# SLP_S3# SLP_S4# SLP_S5# +1.5V +1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V) ON ON OFF +1.5VS +1.5VS switched power rail ON OFF OFF E +VALW +V +VS HIGH HIGH HIGH HIGH ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF Full ON Power Plane SIGNAL STATE Voltage Rails D Clock ON S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Power Plane Description S1 S3 S5 +VGA_CORE GPU power PX OFF OFF +3VGS GPU power PX OFF OFF +1.8VGS GPU power PX OFF OFF +1.5VGS GPU power PX OFF OFF +1.0VGS GPU power PX OFF OFF +1.8VS (+5VALW ) to 1.8V switched power rail to PCH ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VALW_EC +3VALW always to KBC ON ON ON* +LAN_IO +3VALW to +LAN_IO power rail for LAN ON ON +3V_PCH +3VALW to +3V_PCH power rail for PCH (Short Jumper) ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* Device +5V_PCH +5VALW to +5V_PCH power rail for PCH (Short resister) ON ON ON* Smart Battery +5VS +5VALW to +5VS switched power rail ON OFF OFF G-sensor +VSB B+ to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON ON* EC SM Bus1 address EC SM Bus2 address Address Address Device 0x50/0x52 PCH (Reserve) PCH SM Bus address Device Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Address DDR DIMM0 DDR DIMM1 CLKOUT DESTINATION Mini Card1 Mini Card2 TP module PCI0 PCH_LPBACK PCI1 PCI_LPC SMBUS Control Table SOURCE EC_SMB_CK1 EC_SMB_DA1 KB930 EC_SMB_CK2 EC_SMB_DA2 KB930 PCH_SMBCLK PCH_SMBDATA PCH PCH_SML0CLK PCH_SML0DATA PCH PCH_SML1CLK PCH_SML1DATA PCH BATT WLAN MIINI1 V BATT Charger TP PCH_SML1CLK EC_SMB_CK2 SODIMM PCH_SML1DATA EC_SMB_DA2 G-Sensor HP AMP V V V V @ GPU V V None PCI4 None USB Port Table V DESTINATION CLKOUT_PCIE0 PCIE LAN CARD READER FLEX CLOCKS DESTINATION CLKOUTFLEX0 None CLKOUTFLEX1 None CLKOUTFLEX2 None TPM 9656@ CPUUMA1@ CPUUMA2@ CPUDIS@ VRAM X76@ None CLKOUT_PCIE4 None CLKOUT_PCIE5 None UHCI1 EHCI1 SATA2 None SATA3 None UHCI3 SATA4 None UHCI4 SATA5 None UHCI2 H2G@ S2G@ EHCI2 DGPU_PRSNT# UHCI5 UHCI6 Option ✁  ✂ ✄ ☎✆ ✝ ☎✞ ✟✠ CLKOUT_PCIE3 CLKOUTFLEX3 ✡ ☛☞ ✌✍ ✎ ✏ ✒✑✑ ✌✓✔ ✕ ✗✘✖ ✍✙ None UHCI0 USB30@ PX@ UMA @ X CONN@ X V X UMA@ V DIS@ X X DIS X X V V X V V THA@ USB 3.0 CLKOUT_PCIE6 None CLKOUT_PCIE7 None CLKOUT_PEG_B None Project ID 30UMA@ 30DIS@ 50UMA@ LA-8661P PX@ A B Camera Mini Card(WLAN& BT) None None None None External USB Port USB3.0 (left Side) LA-8662P Issued Date None Compal Electronics, Inc Compal Secret Data 2011/06/29 Deciphered Date 2011/06/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC UMA@ C D None USB3.0 (left Side) 50DIS@ None None None None None Security Classification PCB 10 11 12 13 Port ✡ ☛☞ ✌✍ ✎ ✍✌✚ ✗✒✔ ✕ ✗✘✖ ✍✙ CLKOUT_PCIE2 External USB Port USB2.0 (left Side) USB2.0 (right Side) USB2.0 (left Side) USB 2.0 USB 1.1 Port SATA1 m-SATA,JMINI2 9635@ CPU mini WLAN DESTINATION SATA0 SATA, JHDD1 M2G@ PCI3 V BY SKU CLK None SATA DIFFERENTIAL CLKOUT_PCIE1 PCI2 Title Notes List Size C Date: Document Number Rev 0.1 LA-8661P Friday, March 02, 2012 Sheet E of 55 D D C C B B A A Compal Secret Data Security Classification Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PROCESSOR(1/7) DMI,FDI,PEG Size B Date: Document Number Friday, March 02, 2012 Rev 0.1 Sheet of 55 UCPU1 CPUDIS01@ i5-2467M CPU SA00004X000 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohms Sandy Bridge: Intel Core i5-2467M: SA00004X000 (4619HY32L01) UCPU1 CPUDIS02@ i5-2367M CPU SA000051H20 UCPU1 CPUUMA3@ i5-2367M CPU SA000051H20 UCPU1 CPUUMA1@ 17W 1.5GHz GT2 ES2 QBP8 SA00005AZ10 UCPU1 CPUUMA4@ 17W 1.7GHz GT2 ES2 QBP7 SA00005B010 UCPU1 CPUUMA2@ 17W 1.5GHz no cnfg ES2 QBTP SA00005AZ20 Ivy Bridge: 1.5GHz GT2 ES2 QBP8: SA00005AZ10 (4619HZ32L01) 1.5GHz ES2 QBTP: SA00005AZ20(4619HZ32L02) +VCCP D D UCPU1 CPUDIS04@ i5-3317U CPU SA00005K600 M2 P6 P1 P10 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 N3 P7 P3 P11 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 K1 M8 N4 R2 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 K3 M7 P4 T3 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 U7 W11 W1 AA6 W6 V4 Y2 AC9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 FDI_FSYNC0 FDI_FSYNC1 U11 FDI_INT B RC2 24.9_0402_1% AA10 AG8 FDI_LSYNC0 FDI_LSYNC1 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance