COMPAL LA 2411 REV 0 1

A B C D E LA-2411 1 Compal confidential 2 Schematics Document DT TRANSPORT or Prescott uFCPGA with ATI-RC300M+SB200 core logic 2004-06-08 3 REV:0.2 4 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Cover Sheet Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 E of 65 A B C D E Compal confidential File Name :LA2411 Fan Control page Intel Northwood/Prescott Processor uFCBGA-479/uFCPGA-478 CPU page 25 H_A#(3 31) LCD Conn W/O EXT VGA CHIP W/EXT VGA CHIP page page 24 H_D#(0 63) VGA M9 Embeded 868 pin u-BGA AGP BUS ATI-M9+X/M10C PSB 800MHz ATI-RC300M W/O EXT VGA CHIP page 25 W/EXT VGA CHIP page 4,5,6 CRT & TV-OUT Conn CLOCK GENERATOR ICS951402AGT Thermal Sensor ADM1032AR page 8,9,10,11,12,13 Memory BUS(DDR) DDR-SO-DIMM X2 BANK 0, 1, 2, 3page 14,15,16 2.5V DDR- 200/266 USB1.1 USB conn x4 USB2.0 VGA DDR x2 CHB page 35 VGA DDR x2 CHA page 23 page 42 BT page 17,18,19,20,21 Audio Codec ALC 250 A-Link page 22 AMP & Audio Jack page 36 MDC & BT Conn PCI BUS 3.3V 33 MHz IDSEL:AD19 (PIRQD#,GNT#1,REQ#1) CardBus Controller IEEE 1394 Mini PCI LAN ENE 714/1410 RTL 81000CL TI-TSB43AB22 socket page 33 page 34 page 41 page 31 ATI-SB200 BGA 457 pin page 26,27,28,29 IDSEL:AD16 IDSEL:AD18 (PIRQA#,GNT#0,REQ#0)(PIRQC#,GNT#3,REQ#3) Slot RJ45 CONN page 33 page 32 Card slot page 41 HDD Connector Primary IDE page 30 CDROM Connector page Secondary IDE page 32 LPC BUS RTC CKT page 42 Mini-PCI solt AC-LINK ATA-100 RJ11 CONN page 42 IDSEL:AD20 (PIRQA,B#,GNT#2,REQ#2) ATA-100 30 page 26 Power OK CKT page 46 Power On/Off CKT page 46 page 44 page 40 page 41 *RJ45 CONN *LINE IN JACK *DC JACK *COM PORT *USB CONN x1 *SPDIF *5V INPUT *VOLUME ADJUSTMENT +TV-OUT PORT page 38 Int.KBD Touch Pad CABLE CONN SUPER I/O SMC 207 ENE910 page 43 FIR page 43 DC/DC Interface CKT EC I/O Buffer BIOS page 45 page 37 KEY page 45 page 47 Power Circuit DC/DC Compal Electronics, Inc Title page 50,51,52,53,54,55,56,57 Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 E of 65 A Voltage Rails Power Plane Description S0-S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +VCC_CORE Core voltage for CPU ON OFF OFF +VCCVID The voltage for Processor VID select ON OFF OFF +1.25VS 1.25V switched power rail for DDR Vtt ON OFF OFF +1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P ON OFF OFF OFF +1.5VS 1.5V I/O power rail for ATI-RS300M/RC300M NB AGP ON OFF +1.8VS 1.8V switched power rail for ATI-RS300M/RC300M NB ON OFF OFF +2.5VALW 2.5V always on power rail ON ON ON* +2.5V 2.5V system power rail for DDR ON ON OFF +2.5VS 2.5V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V system power rail for SB,LAN,CardReader and HUB ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5V 5V system power rail ON ON OFF +5VS 5V switched power rail ON OFF OFF +12VALW 12V always on power rail ON ON ON* RTCVCC RTC power ON ON ON Symbol Note : : means Digital Ground : means Analog Ground @ : means just reserve , no build NAGP@ : means just build when no external AGP VGA chip build in (UMA) M10@ : means build VGA M10 M9@ : means build VGA M9+X M9-M10@ : means build VGA M9 or M10 1520@ : means build Cardbus PCI1520 1620@ : means build Cardbus PCI1620 ATI@ : means build ATI SB USB2.0 related to turn on the function NEC@ : means build NEC USB2.0 related to turn on the function Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Board ID Table for AD channel External PCI Devices Vcc Ra DEVICE IDSEL # REQ/GNT # PIRQ NB Internal VGA N /A N /A AGP BUS AGP_DEVSEL N /A A SOUTHBRIDGE AD31 (INT.) N /A N /A Board ID A USB AD30 (INT.) N /A D AC97 AD31 (INT.) N /A B ATA 100 AD31 (INT.) N /A A ETH ERNET AD24(INT.) N /A C 1394 AD16 A L AN AD19 D CARD BUS AD20 A B Wireless LAN(MINI PCI) AD18 C Board ID I2C / SMBUS ADDRESSING DEVICE HEX ADDRESS DDR SO-DIMM A0 1010000X DDR SO-DIMM A2 1010001X CLOCK GENERATOR (EXT.) D2 1101001X 3.3V +/- 5% 100K +/- 5% Rb 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V PCB Revision 0.1 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Size Date: Notes List Document Number Rev 0.1 LA-2411 Tuesday, June 08, 2004 Sheet of 65 +VCC_CORE K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 V3 W2 Y1 AB1 C H_REQ#[0 4] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADS# R230 51_0402_5% AP#0 AP#1 BINIT# IERR# H6 D2 G2 G4 BR0# BPRI# BNR# LOCK# AF22 AF23 BCLK0 BCLK1 51_0402_5% CK_BCLK CK_BCLK# F3 E3 E2 HIT# HITM# DEFER# H1 H4 H23 H26 A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AD4 AD8 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 H_HIT# H_HITM# H_DEFER# H_D#[0 63] H _D#0 H _D#1 H _D#2 H _D#3 H _D#4 H _D#5 H _D#6 H _D#7 H _D#8 H _D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 C +5VS +5VS R1099 R1100 47K_0402_5% 47K_0402_5% B AMP_3-1565030-1_Prescott B B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 CK_BCLK CK_BCLK# VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_80 VCC_79 VCC_78 VCC_77 VCC_76 VCC_75 VCC_74 H_BR0# H_BPRI# H_BNR# H_LOCK# AC1 V5 AA3 AC3 BOOTSELECT R231 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 ADS# F13 F15 F17 F19 F9 F11 E8 E20 E18 E16 E14 E12 +VCC_CORE H_ IERR# J1 K5 J4 J3 H3 G1 D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9 D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63 Prescott AD1 +VCC_CORE A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#[3 31] D A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 JP8A VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 D H_BOOTSELECT C +VCC_CORE TESTHI11 B6 FERR# Prescott Pin name Commend Pull-up 62ohm to +VCC_CORE Pull-up 200ohm to +VCC_CORE TESTHI11 Pull-up 62ohm to +VCC_CORE FERR#/PBE# Pull-up 62ohm to +VCC_CORE Northwood MT Pin name Commend Connect to PLD CPUPREF through 0ohm GHI FERR# Pull-up 62ohm to +VCC_CORE Northwood Prescott Northwood MT Pop Pop Pop Pop Pop Pop Pop AA20 ITPCLKOUT0 Pull-up56ohm to +VCC_CORE TESTHI6 Pull-up 62ohm to +VCC_CORE ITPCLKOUT0 Pull-up56ohm to +VCC_CORE Pop Pop AB22 ITPCLKOUT1 Pull-up 56ohm to +VCC_CORE TESTHI7 Pull-up 62ohm to +VCC_CORE ITPCLKOUT1 Pull-up 56ohm to +VCC_CORE Pop Pop Pop AD2 NC float VIDPWRGD Pull-up 2.43K ohm to +VCCVID NC float Depop Pop Depop AD3 NC float VID5 Pull-up1Kohm to +3VRUN & connect to PWRIC NC float Depop Pop Depop AF3 NC float VCCVIDLB Connect to +VCCVID NC float Depop Pop Depop Pop Depop Pop Pop Depop Pop Pop Pop Pop A VCCA Connect to CPU Filter VCCIOPLL Connect to CPU Filter VCCA Connect to CPU Filter Connect to CPU Filter VCCA Connect to CPU Filter VCCIOPLL Connect to CPU Filter AD1 VSS Connect to GND BOOTSELECT CPU determine VSS Connect to GND AE26 VSS Connect to GND OPTIMIZED/ float COMPAT# VSS Connect to GND AD25 TESTHI12 Pull-up 200ohm to +VCC_CORE AD20 TESTHI12 E Q106 2SC2411K_SC59 Pull-up 62ohm to +VCC_CORE MMBT3904_SOT23 R900 100K_0402_5% A VCCIOPLL AE23 Q107 A6 Commend Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5 Pin number Northwood Pin name 22K_0402_5% R899 B Reference Intel document Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0 Connect to PLD through 0ohm DPSLP Compal Electronics, Inc Title Prescott Processor in uFCPGA478 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 of 65 +VCC_CORE Place near SB200 (U6) 56_0402_5% H_F ERR# R515 56_0402_5% H_THERMTRIP# H_TRDY# 56_0402_5% H_RESET# H_A20M# H_FERR# H_IGNNE# H_SMI# H_PWRGOOD H_STPCLK# H_F ERR# H _PWRGOOD H_INTR H_NMI H_INIT# H_RESET# H_RESET# C6 B6 B2 B5 AB23 Y4 A20M# FERR# IGNNE# SMI# PWRGOOD STPCLK# D1 E5 W5 AB25 LINT0 LINT1 INIT# RESET# H5 H2 AD6 AD5 H_DBSY# H_DRDY# BSEL0 BSEL1 H_THERMDA H_THERMDC H_THERMTRIP# R529 R530 C 1 56_0402_5% 56_0402_5% RP137 56_0804_8P4R_5% Note: Please change to 10uH, DC current of 100mA parts and close to cap +VCC_CORE L36 LQG21F4R7N00_0805 33U_D2_8M_R35 C544 + L37 2 LQG21F4R7N00_0805 + H_THERMTRIP# A2 R1017 BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# D4 C1 D5 F7 E6 TCK TDI TDO TMS TRST# A5 A4 AF3 0_0402_5% AD22 CK_ITP CK_ITP# AC26 AD26 COMP0 COMP1 1 1.Place cap within 600 mils of the VCCA and VSSA pins DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 F21 J23 P23 W23 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 ADSTB#0 ADSTB#1 L5 R5 H_ADSTB#0 H_ADSTB#1 E21 G25 P26 V21 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 COMP0 COMP1 +VCC_CORE R521 56_0402_5% H_TESTHI2_7 R522 56_0402_5% 1 56_0804_8P4R_5% 300_0402_5% 56_0402_5% RP136 H_TESTHI8 H_TESTHI9 H_TESTHI10 H_TESTHI11 H_DPSLP# H_TESTHI12 R990 R527 CPU_GHI# AE25 ITP_DBRESET# PROCHOT# MCERR# SLP# C3 V6 AB26 H_PROCHOT# NC1 NC2 NC3 NC4 NC5 A22 A7 AF25 AF24 AE21 for mobile CPU C W/O ITP H_PROCHOT# H_CPUSLP# AMP_3-1565030-1_Prescott +VCCVID C932 0.1U_0402_10V6K R_E R541 680_0603_5% RE Pop: Prescott Depop: Northwood B +VCCVID +3VALW R545 H_ VID_PWRGD H_ VID_PWRGD S P D 14 4.7K_0402_5% I SN74LVC14APWLE_TSSOP14 O G U32A 2 G Q45 VID_PWRGD V ID0 V ID1 V ID2 V ID3 V ID4 V ID5 +3VS If CPU is P4 , Change the resistor R 546 va lue to 75_0603_1% H_TESTHI0_1 DBR# ITP_CLK0 ITP_CLK1 R546 @54.9_0603_1% ITP_TDO Close to the ITP AF26 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 R547 @54.9_0603_1% ITP_DBRESET# SKTOCC# E22 K22 R22 W22 DBI#0 DBI#1 DBI#2 DBI#3 +VCC_CORE 2N7002 1N_SOT23 +3VS R993 4.7K_0402_5% GTL Reference Voltage Layout note : CPU_STP# +CPU_GTLREF Trace wide 12mils(min),Space 15mils ITP_TMS CPUCLK_STP# Q96 MMBT3904_SOT23 +3VS VID5 R553 100_0402_1% VID4 R_A +CPU_GTLREF VID3 VID2 VID1 VID0 12K_0402_5% R1125 2 Place R_A and R_B near CPU Place decoupling cap 220PF near CPU +VCC_CORE Q95 MMBT3904_SOT23 1K_0402_5% ITP_TDI R552 DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 Prescott B R550 1K_0402_5% AE26 VSSA 51.1 Ohm for Northwood, 61.9 Ohm for Prescott @0_0402_5% AD24 AA2 AC21 AC20 AC24 AC23 AA20 AB22 U6 W4 Y3 A6 AD25 VCCSENSE VSSSENSE VCCVIDLB R540 61.9_0603_1% R539 61.9_0603_1% L24 P1 Pop: Northwood Depop: Prescott R520 TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9 TESTHI10 TESTHI11 TESTHI12 VCCIOPLL VCCA width= 10mil AA21 AA6 F20 F6 D +CPU_GTLREF CPU_STP# THERMTRIP# AC6 AB5 AC4 Y6 AA5 AB4 CK_ITP CK_ITP# 2.H_VCCIOPLL,HVCCA,HVSSA trace wide 12 mil s(min) THERMDA THERMDC J26 K25 K26 L25 OPTIMIZED/COMPAT# DBSY# DRDY# BSEL0 BSEL1 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 AD20 AE23 H_VSSA R1017-> Pop: Prescott Depop: Northwood PLL Layout note : B3 C4 H _VCCA C854 VCCSENSE VSSSENSE +VCCVID 33U_D2_8M_R35 H_THERMDA H_THERMDC DP#0 DP#1 DP#2 DP#3 GTLREF0 GTLREF1 GTLREF2 GTLREF3 F8 G21 G24 G3 G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5 +VCC_CORE RS#0 RS#1 RS#2 RSP# TRDY# @0_0402_5% VCCVID F1 G5 F4 AB2 J6 AF4 H_RS#0 H_RS#1 H_RS#2 VIDPWRGD H_RS#[0 2] AD2 R519 Place near CPU VID0 VID1 VID2 VID3 VID4 VID5 300_0402_5% H _PWRGOOD AE5 AE4 AE3 AE2 AE1 AD3 130_0402_5% H_PROCHOT# R518 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 R517 JP8B AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 D R514 R513 V ID5 R542 1K_0402_5% V ID4 R543 1K_0402_5% V ID3 V ID2 V ID1 V ID0 RP94 1K_1206_8P4R_5% A A ITP_TCK 1K_0402_5% R556 R558 R_B 169_0402_1% Close to the CPU R559 1K_0402_5% 2 C546 1U_0603_10V4Z C547 220P_0402_25V8K Compal Electronics, Inc ITP_TRST# Title Between the CPU and ITP Prescott Processor in uFCPGA478 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 of 65 Place 11 North of Socket(Stuff 6) +VCC_CORE C131 22U_1206_16V4Z C132 22U_1206_16V4Z C133 22U_1206_16V4Z C134 22U_1206_16V4Z C135 22U_1206_16V4Z C136 22U_1206_16V4Z C137 22U_1206_16V4Z C138 22U_1206_16V4Z C139 22U_1206_16V4Z C140 22U_1206_16V4Z C141 22U_1206_16V4Z D D Place 12 Inside Socket(Stuff all) +VCC_CORE C142 22U_1206_16V4Z C143 22U_1206_16V4Z C144 22U_1206_16V4Z C145 22U_1206_16V4Z C146 22U_1206_16V4Z C147 22U_1206_16V4Z C148 22U_1206_16V4Z C149 22U_1206_16V4Z C150 22U_1206_16V4Z C151 22U_1206_16V4Z +VCC_CORE C152 22U_1206_16V4Z C153 22U_1206_16V4Z C C Place South of Socket(Unstuff all) +VCC_CORE C154 22U_1206_16V4Z C155 22U_1206_16V4Z C156 22U_1206_16V4Z C157 22U_1206_16V4Z C158 22U_1206_16V4Z C159 22U_1206_16V4Z C160 22U_1206_16V4Z C161 22U_1206_16V4Z C162 22U_1206_16V4Z B B SANYO OS-CON 820uF H:13*3 (C163,C164,C165) SANYO OS-CON 820uF H:9*2 (C166,C167) +VCC_CORE 1 + C163 + C164 820U_E9_2_5V_M_R7 820U_E9_2_5V_M_R7 + C165 Place Inside Socket around the edge 820U_E9_2_5V_M_R7 +VCC_CORE + C166 + C167 820U_E9_2_5V_M_R7 820U_E9_2_5V_M_R7 C168 0.22U_0603_10V7K C169 0.22U_0603_10V7K C170 0.22U_0603_10V7K C171 0.22U_0603_10V7K C172 0.22U_0603_10V7K C173 0.22U_0603_10V7K +VCC_CORE + C174 + 470U_D2_2.5VM C175 470U_D2_2.5VM + C176 @470U_D2_2.5VM + C177 + @470U_D2_2.5VM C178 @470U_D2_2.5VM +VCC_CORE A A + C179 + 470U_D2_2.5VM C180 470U_D2_2.5VM + C181 470U_D2_2.5VM + C182 + 470U_D2_2.5VM C183 @470U_D2_2.5VM Compal Electronics, Inc Title CPU Decoupling THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 of 65 Thermal Sensor ADM1032AR +3VALW H_THERMDA H_THERMDA H_THERMDC W= 15mil H_THERMDC C251 1 0.1U_0402_10V6K R283 U8 @10K_0402_5% D C253 2200P_0402_25V7K VDD SCLK EC_SMC_2 H_THERMDA D+ SDATA EC_SMD_2 H_THERMDC D- ALERT# THERM# GND D ADM1032AR_SOP8 Address:1001_100X R286 +VCC_CORE 300_0402_5% C256 2 B E @1U_0603_10V6K C H_THERMTRIP# H_THERMTRIP# MAINPWON Q17 2SC2411K_SC59 C C FAN CONN.1 8.2K_0402_5% FA N1 C265 10U_0805_10V4Z +IN OUT -IN C R914 LM358A_SO8 C855 JP10 1 R918 100_0402_5% C841 B E 1 U10B R916 10K_0402_5% 1N4148_SOD80 EN_FAN2 EN_FAN2 C838 10U_0805_16V4Z FMMT619_SOT23 FA N2 0.1U_0402_10V6K 8.2K_0402_5% D26 C266 1N4148_SOD80 10U_0805_10V4Z R919 ACES_85205-0300 2 FANSPEED1 +3VS JP11 C856 ACES_85205-0300 1000P_0402_16V7K 10K_0402_5% B C839 10U_0805_16V4Z 1SS355_SOD323 1000P_0402_16V7K +3VS D68 Q91 E 0.1U_0402_10V6K D25 R917 D67 Q90 1 FMMT619_SOT23 LM358A_SO8 B -IN R915 10K_0402_5% 100_0402_5% C840 R913 1 C OUT U10A +IN G +5VS 1SS355_SOD323 P EN_FAN1 EN_FAN1 FAN CONN +5VS +12VALW R920 FANSPEED2 C907 1000P_0402_16V7K 10K_0402_5% C908 1000P_0402_16V7K B A A Compal Electronics, Inc Title CPU Thermal Sensor&FAN CTRL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 of 65 H_A#[3 31] H_A#[3 31] H_REQ#[0 4] H_REQ#[0 4] H_D#[ 63] H_D#[0 63] U27A CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADSTB0# H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1 U30 T30 R28 R25 U25 T28 V29 T26 U29 U26 V26 T25 V25 U27 U28 T29 CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_ADSTB1# H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRD Y# H_DBSY# H_BR0# H_LOCK# L27 K25 H26 J27 L26 G27 F25 K26 CPU_ADS# CPU_BNR# CPU_BPRI# CPU_DEFER# CPU_DRDY# CPU_DBSY# CPU_BR0# CPU_LOCK# H_RESET# H_RS#2 H_RS#1 H_RS#0 A17 G25 G26 J25 CPU_CPURSET# CPU_RS2# CPU_RS1# CPU_RS0# H_TRDY# H_HIT# H_HITM# F26 J26 H25 CPU_TRDY# CPU_HIT# CPU_HITM# A9 AH5 AG5 C7 CPU_RSET# SUS_STAT# SYSRESET# POWERGOOD 24.9_0402_1% COMP_N V28 CPU_COMP_N R382 49.9_0402_1% COMP_P L34 CPVDD @1U_0603_10V6K HB-1M2012-121JT03_0805 2CPVSS C361 10U_0805_10V4Z C996 W29 CPU_COMP_P H23 CPVDD J23 CPVSS > 412_0402_1% R380 L Note: PLACE CLOSE TO RC300M, USE 10/10 WIDTH/SPACE +VCC_CORE PLACE CLOSE TO U27 Ball W28, USE 20/20 WIDTH/SPACE B R383 +VCC_CORE +1.8VS H_RESET# H_RS#2 H_RS#1 H_RS#0 H_TRDY# H_HIT# H_HITM# 330_0402_5% NB_SUS_STAT# NB_RST# NB_PWRGD R381 W28 CPU_VREF 100_0402_1% R384 169_0402_1% 2 C362 1U_0603_10V6K C363 DATA GROUP ADDR GROUP Y29 Y28 THERMALDIODE_N THERMALDIODE_P B17 TESTMODE 1 NB_GTLREF DATA GROUP 0.1U_0402_10V6K C974 DATA GROUP H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# H_LOCK# 220P_0402_25V8K R385 C363 CLOSE TO Ball W28 CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_DBI0# CPU_DSTBN0# CPU_DSTBP0# L30 K29 J29 H28 K28 K30 H29 J28 F28 H30 E30 D29 G28 E29 D30 F29 E28 G30 G29 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DINV#0 H_DSTBN#0 H_DSTBP#0 CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_DBI1# CPU_DSTBN1# CPU_DSTBP1# B26 C30 A27 B29 C28 C29 B28 D28 D26 B27 C26 E25 E26 A26 B25 C25 A28 D27 E27 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DINV#1 H_DSTBN#1 H_DSTBP#1 CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_DBI2# CPU_DSTBN2# CPU_DSTBP2# F24 D24 E23 E24 F23 C24 B24 A24 F21 A23 B23 C22 B22 C21 E21 D22 D23 E22 F22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DINV#2 H_DSTBN#2 H_DSTBP#2 CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# CPU_DBI3# CPU_DSTBN3# CPU_DSTBP3# B21 F20 A21 C20 E20 D20 A20 D19 C18 B20 E18 B19 D18 B18 C17 A18 F19 E19 F18 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#3 H_DSTBN#3 H_DSTBP#3 PENTIUMAGTL+ I/F IV H_ADSTB#1 CONTROL C MISC H_ADSTB#0 ADDR GROUP M28 P25 M25 N29 N30 M26 N28 P29 P26 R29 P30 P28 N26 N27 M29 N25 R26 L28 L29 R27 DATA GROUP PART OF H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 D D H_DINV#0 H_DSTBN#0 H_DSTBP#0 C H_DINV#1 H_DSTBN#1 H_DSTBP#1 H_DINV#2 H_DSTBN#2 H_DSTBP#2 B H_DINV#3 H_DSTBN#3 H_DSTBP#3 4.7K_0402_5% 216RC300M_BGA_718 +VCC_CORE 0.1U_0402_10V6K C364 22U_1206_16V4Z_V1 A C365 C366 2 0.1U_0402_10V6K C367 0.1U_0402_10V6K C368 C369 0.1U_0402_10V6K C370 2 0.1U_0402_10V6K 0.1U_0402_10V6K C371 1 2 0.1U_0402_10V6K C372 0.1U_0402_10V6K A Compal Electronics, Inc Title ATI RC300M-AGTL+ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 of 65 U27B DDRA_RAS# DDRA_CAS# DDRA_WE# MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 DDRA_DM0 DDRA_DM1 DDRA_DM2 DDRA_DM3 DDRA_DM4 DDRA_DM5 DDRA_DM6 DDRA_DM7 AH7 AF10 AJ14 AF21 AH23 AK28 AD29 AB26 MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7 DDRA_RAS# DDRA_CAS# AF24 AF25 MEM_RAS# MEM_CAS# DDRA_WE# AE24 MEM_WE# AJ8 AF9 AH13 AE21 AJ23 AJ27 AC28 AA25 MEM_DQS0 MEM_DQS1 MEM_DQS2 MEM_DQS3 MEM_DQS4 MEM_DQS5 MEM_DQS6 MEM_DQS7 DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7 C DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_CLK3 DDRA_CLK3# DDRA_CLK4 DDRA_CLK4# B AH19 AJ17 AK17 AH16 AK16 AF17 AE18 AF16 AE17 AE16 AJ20 AG15 AF15 AE23 AH20 AE25 +1.8VS DDRA_CLK0 DDRA_CLK0# AK10 AH10 MEM_CK0 MEM_CK0# DDRA_CLK1 DDRA_CLK1# AH18 AJ19 MEM_CK1 MEM_CK1# AG30 AG29 MEM_CK2 MEM_CK2# DDRA_CLK3 DDRA_CLK3# AK11 AJ11 MEM_CK3 MEM_CK3# DDRA_CLK4 DDRA_CLK4# AH17 AJ18 MEM_CK4 MEM_CK4# AF28 AG28 MEM_CK5 MEM_CK5# AF13 AE13 AG14 AF14 MEM_CKE0 MEM_CKE1 MEM_CKE2 MEM_CKE3 DDRA_CS#0 DDRA_CS#1 DDRA_CS#2 DDRA_CS#3 AH26 AH27 AF26 AG27 MEM_CS#0 MEM_CS#1 MEM_CS#2 MEM_CS#3 MPVDD AC18 MPVDD DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R2 DDRA_CKE_R3 DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R2 DDRA_CKE_R3 DDRA_CS#0 DDRA_CS#1 DDRA_CS#2 DDRA_CS#3 PART OF L35 HB-1M2012-121JT03_0805 C375 2MPVSS AD18 MPVSS MEM I/F D DDRA_ADD0 DDRA_ADD1 DDRA_ADD2 DDRA_ADD3 DDRA_ADD4 DDRA_ADD5 DDRA_ADD6 DDRA_ADD7 DDRA_ADD8 DDRA_ADD9 DDRA_ADD10 DDRA_ADD11 DDRA_ADD12 DDRA_ADD13 DDRA_ADD14 DDRA_ADD15 DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63 AG6 AJ7 AJ9 AJ10 AJ6 AH6 AH8 AH9 AE7 AE8 AE12 AF12 AF7 AF8 AE11 AF11 AJ12 AH12 AH14 AH15 AH11 AJ13 AJ15 AJ16 AF18 AG20 AG21 AF22 AF19 AF20 AE22 AF23 AJ21 AJ22 AJ24 AK25 AH21 AH22 AH24 AJ25 AK26 AK27 AJ28 AH29 AH25 AJ26 AJ29 AH30 AF29 AE29 AB28 AA28 AE28 AD28 AC29 AB29 AC26 AB25 Y26 W26 AE26 AD26 AA26 Y27 MEM_CAP1 AF6 C373 0.47U_0603_16V7K MEM_CAP2 AA29 C374 0.47U_0603_16V7K MEM_COMP AK19 MEM_DDRVREF 2 0_0404_4P2R_5% RP31 DDRA_SDQ9 DDRA_SDQ13 DDRA_DQ37 DDRA_DQ33 0_0404_4P2R_5% RP30 DDRA_SDQ37 DDRA_SDQ33 DDRA_DQ10 DDRA_DQ14 0_0404_4P2R_5% RP34 DDRA_SDQ10 DDRA_SDQ14 DDRA_DQ38 DDRA_DQ34 0_0404_4P2R_5% RP33 DDRA_SDQ38 DDRA_SDQ34 DDRA_DQ11 DDRA_DQ15 0_0404_4P2R_5% RP37 DDRA_SDQ11 DDRA_SDQ15 DDRA_DQ39 DDRA_DQ35 0_0404_4P2R_5% RP36 DDRA_SDQ39 DDRA_SDQ35 DDRA_DQS4 R386 0_0404_4P2R_5% DDRA_SDQS4 0_0402_5% DDRA_DQ9 DDRA_DQ13 2 C376 DDRA_DQ1 DDRA_DQ5 DDRA_DQ45 DDRA_DQ41 DDRA_DQ3 DDRA_DQ7 0_0404_4P2R_5% RP45 DDRA_SDQ3 DDRA_SDQ7 DDRA_DQ46 DDRA_DQ42 0_0404_4P2R_5% RP46 DDRA_SDQ46 DDRA_SDQ42 DDRA_DQ2 DDRA_DQ6 0_0404_4P2R_5% RP47 DDRA_SDQ2 DDRA_SDQ6 DDRA_DQ47 DDRA_DQ43 0_0404_4P2R_5% RP48 DDRA_SDQ47 DDRA_SDQ43 0_0404_4P2R_5% DDRA_SDQS0 0_0402_5% DDRA_DQS5 R395 0_0404_4P2R_5% DDRA_SDQS5 0_0402_5% DDRA_DQ21 DDRA_DQ17 C377 DDRA_DQ19 DDRA_DQ23 +2.5V L 1 R409 1K_0603_1% @0.1U_0402_10V6K DDR_VREF trace width of 20mils and space 20mils(min) C858 C859 C860 1 2 @0.1U_0402_10V6K 2 DDRA_DQ62 DDRA_DQ58 0_0404_4P2R_5% RP54 DDRA_SDQ62 DDRA_SDQ58 0_0404_4P2R_5% RP55 DDRA_SDQ19 DDRA_SDQ23 DDRA_DQ63 DDRA_DQ59 0_0404_4P2R_5% RP56 DDRA_SDQ63 DDRA_SDQ59 0_0404_4P2R_5% DDRA_SDM2 0_0402_5% DDRA_DQS7 R404 0_0404_4P2R_5% DDRA_SDQS7 0_0402_5% DDRA_SDQS2 0_0402_5% RP57 DDRA_DQ24 DDRA_DQ28 DDRA_DQ25 DDRA_DQ29 0_0404_4P2R_5% RP59 DDRA_SDQ25 DDRA_SDQ29 DDRA_DM7 R407 RP58 DDRA_DQ53 DDRA_DQ49 0_0404_4P2R_5% RP60 DDRA_SDQ53 DDRA_SDQ49 DDRA_DQ26 DDRA_DQ30 0_0404_4P2R_5% RP61 DDRA_SDQ26 DDRA_SDQ30 DDRA_DQ50 DDRA_DQ54 0_0404_4P2R_5% RP62 DDRA_SDQ50 DDRA_SDQ54 DDRA_DQ27 DDRA_DQ31 0_0404_4P2R_5% RP63 DDRA_SDQ27 DDRA_SDQ31 DDRA_DQ51 DDRA_DQ55 0_0404_4P2R_5% RP64 DDRA_SDQ51 DDRA_SDQ55 DDRA_DQS3 R412 0_0404_4P2R_5% DDRA_SDQS3 0_0402_5% DDRA_DQS6 R413 0_0404_4P2R_5% DDRA_SDQS6 0_0402_5% DDRA_SDM3 0_0402_5% DDRA_SDM[0 7] DDRA_SDQ[0 63] DDRA_DM6 R416 DDRA_SDM[0 7] DDRA_SDQ[0 63] B DDRA_SDM7 0_0402_5% DDRA_DQ52 DDRA_DQ48 DDRA_SDQ24 DDRA_SDQ28 DDRA_SDQ60 DDRA_SDQ56 DDRA_SDQS[0 7] DDRA_ADD[0 15] DDRA_SDQ52 DDRA_SDQ48 DDRA_SDQS[0 7] DDRA_ADD[0 15] Layout note Place these resistor closely DIMM0, all trace length Max=0.75" DDRA_SDM6 0_0402_5% 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K A 0.1U_0402_10V6K C861 C378 0.1U_0402_10V6K DDRA_SDQ18 DDRA_SDQ22 +2.5V 0.1U_0402_10V6K 0_0404_4P2R_5% RP52 DDRA_SDQ61 DDRA_SDQ57 DDRA_DM3 R415 A C857 DDRA_DQS2 R406 1K_0603_1% DDRA_DQ61 DDRA_DQ57 C DDRA_SDM5 0_0402_5% RP50 RP53 DDRA_DM2 R403 0.1U_0402_10V6K DDRA_SDQ20 DDRA_SDQ16 DDRA_SDQ44 DDRA_SDQ40 DDRA_DQ60 DDRA_DQ56 Group sweep Group R408 4 DDRA_DM5 R398 0_0404_4P2R_5% RP51 DDRA_SDQ21 DDRA_SDQ17 DDR_VREF DDR_VREF DDRA_SDM0 0_0402_5% RP49 +2.5V RP41 0_0404_4P2R_5% RP44 DDRA_SDQ45 DDRA_SDQ41 DDRA_DQ20 DDRA_DQ16 D DDRA_SDM4 0_0402_5% 0_0404_4P2R_5% RP43 DDRA_SDQ1 DDRA_SDQ5 DDRA_SDQ0 DDRA_SDQ4 DDRA_SDQ36 DDRA_SDQ32 DDRA_DQ18 DDRA_DQ22 0.1U_0402_10V6K DDRA_DM4 R389 0_0404_4P2R_5% AK20 DDRA_DQ44 DDRA_DQ40 216RC300M_BGA_718 DDRA_SDQ8 DDRA_SDQ12 0_0404_4P2R_5% DDRA_SDQS1 0_0402_5% DDRA_SDM1 0_0402_5% DDRA_DM0 R397 2.2U_0805_10V4Z +2.5V RP40 DDRA_DQ0 DDRA_DQ4 DDRA_DQS0 R394 49.9_0402_1% RP27 DDRA_DQ36 DDRA_DQ32 RP28 DDRA_DQ8 DDRA_DQ12 DDRA_DQS1 R387 DDRA_DM1 R388 MEN_COMP R405 1 @0.1U_0402_10V6K 150U_D2_6.3VM @0.1U_0402_10V6K + C379 C380 0.1U_0402_10V6K C381 C382 0.1U_0402_10V6K C383 C384 0.1U_0402_10V6K C385 C386 0.1U_0402_10V6K C387 C388 0.1U_0402_10V6K C389 C390 0.1U_0402_10V6K 1 2 C391 0.1U_0402_10V6K Compal Electronics, Inc Title ATI RC300M-DDR I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 of 65 U27C PCI_PAR/ALINK_NC PCI_FRAME#/ALINK_STROBE# PCI_IRDY#/ALINK_ACAT# PCI_TRDY#/ALINK_END# INTA# ALINK_DEVSEL# PCI_STOP#/ALINK_OFF# A_SBREQ# A_SBGNT# W5 W6 R570 8.2K_0402_5% +3VS AGP_GNT# AGP_REQ# AGP_GNT# AGP_REQ# AGP8X_DET# AGP8X_DET# AGPREF_8X VREF_8X_IN ALINK_SBREQ# ALINK_SBGNT# V5 V6 PCI_REQ#0/ALINK_NC PCI_GNT#0/ALINK_NC K5 K6 AGP2_GNT#/AGP3_GNT AGP2_REQ#/AGP3_REQ M5 J6 PCI BUS / AGP Bus (GPIO , TMDS , ZVPort) A_SBREQ# A_SBGNT# AGP_SBSTB AGP_SBSTB# AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1# AGP2_CBE#0/AGP3_CBE0/TMD2_D7 AGP2_CBE#1/AGP3_CBE1/TMD2_DE AGP2_CBE#2/AGP3_CBE2 AGP2_CBE#3/AGP3_CBE3/TMD1_D5 R3 M1 L3 H1 AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA AGP_PAR AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA AGP2_PIPE#/AGP3_DBI_HI AGP2_NC/AGP3_DBI_LO AGP2_RBF#/AGP3_RBF AGP2_WBF#/AGP3_WBF P5 R6 T6 T5 P6 R5 C1 D3 N6 N5 AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_FRAME# AGP_DEVSEL# AGP_DBI_HI/PIPE# AGP_DBI_LO AGP_RBF# AGP_WBF# +1.5VS R575 AGP8X_DET# AGP_VREF/TMDS_VREF 0.1U_0402_10V6K AGP_COMP J5 AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0 AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1 AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON# AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP# AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY# AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN C3 C2 D4 E4 F6 F5 G6 G5 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_ST0 AGP_ST1 AGP_ST2 L6 M6 L5 AGP_ST0 AGP_ST1 AGP_ST2 AGP_COMP 169_0402_1% R576 Rb ENAVDD AGP_SBA4 R562 NAPG@0_0402_5% AGP_STP# AGP_SBA5 R563 NAPG@0_0402_5% AGP_SBA1 R994 NAPG@0_0402_5% DDC_DAT AGP_SBA0 R995 NAPG@0_0402_5% DDC_CLK ENBKL# D AGP_BUSY# DDC_DAT DDC_CLK Pop for internal AGP Depop for M11P AGP_AD[0 31] AGP_AD[0 31] AGP_SBA[0 7] AGP_SBA[0 7] AGP_CBE#[0 3] AGP_CBE#[0 3] AGP_ST[0 2] AGP_ST[0 2] AGP_SBSTB AGP_SBSTB# AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1# +3VS AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_FRAME# AGP_DEVSEL# AGP_DBI_HI/PIPE# AGP_DBI_LO AGP_RBF# AGP_WBF# R567 NAGP@10K_0402_5% +3VS R568 R569 NAPG@10K_0402_5% NAGP@2N7002_SOT23 D S S ENBKL NAGP@0_0402_5% G D Q1 Q2 NAGP@2N7002_SOT23 G NB_PWRGD ENBKL# Pop for internal AGP 216RC300M_BGA_718 +3VS 8X(M9+M10@) PLACE CLOSE TO CONNECTOR Ra Rb Rc 2 AGPREF_8X R577 Rc NAPG@0_0402_5% B 324_0402_1% B Ra NAPG@0_0402_5% C C550 1 R561 AD5 AC6 AC5 AD2 W4 AD3 AD6 E5 E6 T3 U2 G3 H2 R560 AGP_SBA3 A_PAR A_STROBE# A_ACAT# A_END# 0_0402_5% A_DEVSEL# A_OFF# AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK# AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK# AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK AGP_SBA2 ALINK_CBE#0 ALINK_CBE#1 ALINK_CBE#2 ALINK_CBE#3 AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 AG4 AE2 AC3 AA3 Y2 W3 W2 V3 V2 V1 U1 U3 T2 R2 P3 P2 N3 N2 M3 M2 L1 L2 K3 K2 J3 J2 J1 H3 F3 G2 F2 F1 E2 E1 D2 D1 A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3 AGPAND LVDS MUXED SIGNALS AGP_AD0/TMD2_HSYNC AGP_AD1/TMD2_VSYNC AGP_AD2/TMD2_D1 AGP_AD3/TMD2_D0 AGP_AD4/TMD2_D3 AGP_AD5/TMD2_D2 AGP_AD6/TMD2_D5 AGP_AD7/TMD2_D4 AGP_AD8/TMD2_D6 AGP_AD9/TMD2_D9 AGP_AD10/TMD2_D8 AGP_AD11/TMD2_D11 AGP_AD12/TMD2_D10 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16/TMD1_VSYNC AGP_AD17/TMD1_HSYNC AGP_AD18/TMD1_DE AGP_AD19/TMD1_D0 AGP_AD20/TMD1_D1 AGP_AD21/TMD1_D2 AGP_AD22/TMD1_D3 AGP_AD23/TMD1_D4 AGP_AD24/TMD1_D7 AGP_AD25/TMD1_D6 AGP_AD26/TMD1_D9 AGP_AD27/TMD1_D8 AGP_AD28/TMD1_D11 AGP_AD29/TMD1_D10 AGP_AD30/TMDS_HPD AGP_AD31 PART OF ALINK_AD0 ALINK_AD1 ALINK_AD2 ALINK_AD3 ALINK_AD4 ALINK_AD5 ALINK_AD6 ALINK_AD7 ALINK_AD8 ALINK_AD9 ALINK_AD10 ALINK_AD11 ALINK_AD12 ALINK_AD13 ALINK_AD14 ALINK_AD15 ALINK_AD16 ALINK_AD17 ALINK_AD18 ALINK_AD19 ALINK_AD20 ALINK_AD21 ALINK_AD22 ALINK_AD23 ALINK_AD24 ALINK_AD25 ALINK_AD26 ALINK_AD27 ALINK_AD28 ALINK_AD29 ALINK_AD30 ALINK_AD31 AK5 AJ5 AJ4 AH4 AJ3 AJ2 AH2 AH1 AG2 AG1 AG3 AF3 AF1 AF2 AF4 AE3 AE4 AE5 AE6 AC2 AC4 AB3 AB2 AB5 AB6 AA2 AA4 AA5 AA6 Y3 Y5 Y6 A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 PCI Bus / A-Link I/F A_PAR A_STROBE# A_ACAT# A_END# R1005 PCI_PIRQA# A_DEVSEL# A_OFF# +1.5VS A_CBE#[0 3] D ? A_AD[0 31] A_AD[0 31] A_CBE#[0 3] C R945 100_0402_1% Depop for M11P Depop 324_0402_1% 1K_0402_1% 100_0402_1% 1K_0402_1% NAGP@47K_0402 4X(NAGP@) 169_0402_1% ATI request AGP8X_DET# +1.5VS +3VS 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K +1.5VS 10U_0805_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z C551 47U_B_6.3VM + C553 C554 0.1U_0402_10V6K C555 C556 0.1U_0402_10V6K C557 C558 0.1U_0402_10V6K +1.5VS C559 C560 0.1U_0402_10V6K 1 C561 C632 0.1U_0402_10V6K C562 C563 C564 1 C565 2 0.1U_0402_10V6K 0.1U_0402_10V6K C566 C567 2 0.1U_0402_10V6K C568 1 C569 C947 2 0.1U_0402_10V6K C948 C864 C949 C950 C935 C936 C933 C934 1 C951 2 2 2 2 2 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z +1.5VS 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K A C552 47U_B_6.3VM + C570 C571 0.1U_0402_10V6K C572 1 2 0.1U_0402_10V6K C573 C574 0.1U_0402_10V6K C575 C576 2 0.1U_0402_10V6K C577 C578 C937 C938 2 0.1U_0402_10V6K 0.1U_0402_10V6K L C939 1 C940 2 0.1U_0402_10V6K C941 C942 2 0.1U_0402_10V6K C943 C944 2 0.1U_0402_10V6K C945 C946 A 2 0.1U_0402_10V6K Note: PLACE CLOSE TO U27 (NB RC300M) Title Compal Electronics, Inc ATI RC300M-AGP, ALINK BUS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 10 of 65 A B C D B+ 1 1 PC46 4.7U_1206_25V6K 2 47P_0402_50V8J2 PR243 698_0402_1% PC72 4.7U_1206_10V7K 10.2K_0603_1% PC75 100P_0402_50V8J 2 1 + PC76 150U_D2_6.3VM PR96 PR95 0_0402_5% +5VALWP PR99 47K_0402_5% 2M_0402_1% PC65 2 PR82 G S S S 1 D D D D G S S S PC56 4.7U_1206_25V6K PC58 2 0.47U_0603_16V7K MAX1902EAI_SSOP28 PR94 @0_0402_5% PR79 0_0402_5% PC68 PR78 1.54K_0603_1% PD18 SKS10-04AT_TSMA VL 4.7U_1206_25V6K PC57 2 DL5 2.5VREF PQ13 SI4800DY-T1_SO8 PC73 680P_0402_50V7K VS 2 PR97 10K_0402_1% PQ15 SI4810DY_SO8 RUN/ON3 DH51 PR80 0_0402_5% TIME/ON5 28 DH5 PR92 @300K_0402_5% PR89 10K_0402_5% 12OUT VDD BST5 DH5 LX5 DL5 PGND CSH5 CSL5 FB5 SEQ REF SYNC RST# CSH3 CSL3 FB3 SKIP# SHDN# 10 23 PR2422 620_0402_5% VL LX3 DL3 PR77 0_0402_5% 21 22 26 24 DH3 PC71 100P_0402_50V8J PR91 3.32K_0603_1% ACIN BST3 27 18 16 17 19 20 14 13 12 15 11 GND 0.47U_0603_16V7K PR85 0_0402_5% 25 V+ PC67 PR241 1.27K_0603_1% 1 S B++++ 1 2 S S S G PU6 1.27K_0603_1% PR83 1M_0402_1% 2 PD17 SKUL30-02AT_SMA + + D AC IN G PR81 PC61 4.7U_1206_25V6K D D D D PC63 2 1 PC70 @150U_D2_6.3VM PC69 150U_D2_6.3VM +3VALWP DL3 PQ51 2N7002_SOT23 10U_SPC-1204P-100_4.5A_20% PC60 0.1U_0805_25V7K DH3 PL6 47P_0402_50V8J PQ14 SI4810DY_SO8 0.1U_0805_25V7K +12VALWP PC54 4.7U_1206_10V7K 1SS355_SOD323 LX3 PR75 0_0402_5% 9U_SDT-1204P-9R0-120_4.5A_20% LX5 2200P_0402_50V7K PD19 PR74 0_0402_5% 1 DH31 FLYBACK PT1 PC53 PR239 2.7K_1206_5% VS PR73 22_1206_5% PD16 DAP202U_SOT323 VL PQ12 SI4800DY-T1_SO8 S S S G D D D D 4.7U_1206_25V6K PC52 4.7U_1206_25V6K PC51 PC50 2200P_0402_50V7K 0.1U_0805_25V7K PD15 EC11FS2_SOD106 SNB D D D D BST51 470P_0805_100V7K BST31 PC47 PC48 B++++ 2 PL5 FBM-L18-453215-900LMA90T_1812 PR100 10K_0402_1% 1 VL PC79 @0.047U_0603_16V7K PR101 806K_0603_1% MAINPWON PC80 0.47U_0603_16V7K 4 Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Title OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS Size Document Number AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, Date: Tuesday, June 08, 2004 INC 5V/3.3V/12V A B C Rev 0.1 Sheet D 51 of 65 PL7 B+ D +5VALWP FBM-L18-453215-900LMA90T_1812 PR102 0_0603_5% +1.25VSP PJP2 JUMP_43X118 2 +2.5VALWP PJP4 JUMP_43X118 1 2 1 2 PJP3 JUMP_43X118 2 PJP5 JUMP_43X118 2 4.7U_1206_25V6K 220U_D2_4VM PC95 4.7U_0805_6.3V6K PC96 1 PR267 @0_0603_5% C + 2 PC211 @100P_0402_50V8K PR117 100K_0603_1% 1 PR268 0_0603_5% PD23 SKS10-04AT_TSMA G S S S +5VALWP 1 +5VALWP B +5VALW +1.25VS PJP6 +VCCVIDP +2.5VALW PC99 PR249 0_0402_5% PJP1 JUMP_43X118 1 2 13 PR115 100K_0603_1% PR116 127K_0603_1% 0.22U_0603_16V7K B PQ19 SI4810DY_SO8 PR114 16.9K_0603_1% 2 PR248 VCC_MAX1845 @0_0402_5% PR108 0_0603_5% 2 ILIM2 ILIM1 +2.5VALWP 4.7U_SPC-1204P4R7_5.7A_20% 15 14 12 PR236 PL9 PC92 0.1U_0805_25V7K D D D D PC91 22 UVP VCC PGOOD TON ON1 11 REF 0_0603_5% DH1 SKIP +5VALWP BST2 DH2 LX1 LX2 DL1 DL2 MAX1845EEI_QSOP28 CS2 CS1 OUT1 OUT2 FB2 FB1 ON2 19 18 17 20 16 28 PU7 21 10 27 24 PR106 0_0603_5% VDD BST1 GND 26 V+ 1U_0805_16V7K 25 PR107 0_0603_5% OVP 2 PQ17 SI4800DY_SO8 VCC_MAX1845 23 1 PC88 4.7U_0805_10V4Z PR105 0_0603_5% PC90 0.1U_0805_25V7K D D D D PQ18 SI4810DY_SO8 S S S G 2 SKS10-04AT_TSMA C + 1 4.7U_SPC-1204P4R7_5.7A_20% PC94 4.7U_0805_6.3V6K PD21 PC89 0.1U_0805_25V7K PL8 2 PC93 220U_D2_4VM 1 20_0603_1% SI4800DY_SO8 +1.5VSP 1 PR104 PQ16 PC87 4.7U_1206_25V6K PC184 PR103 0_0603_5% 4.7U_1206_25V6K PC84 PD20 DAP202U_SOT323 PC85 2200P_0402_50V7K 2 2 PC183 4.7U_1206_25V6K 2 D PC83 4.7U_1206_25V6K PC81 2200P_0402_50V7K +VCCVID +3VALWP +3VALW JUMP_43X39 PJP10 JUMP_43X118 2 +1.8VS PJP21 JUMP_43X118 2 +VGA_CORE PJP22 JUMP_43X118 2 PJP8 +12VALWP 1 2 +12VALW +1.8VSP JUMP_43X39 A +1.2VS_VGA A Compal Electronics, Inc Title DDR POWER 2.5V & 1.5V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 B Date: Tuesday, June 08, 2004 Sheet 52 of 65 A B C D PR262 LGATE +1.2VS_VGA D D D D @0.1U_0402_16V7K GND G S S S PC206 22U_1206_6.3V PC205 22U_1206_6.3V PC204 22U_1206_6.3V D D D D PL16 2.2UH_SPC-1205P-2R2B_13A_30% 2 + PR217 0_0603_5% +3VALWP +VCCVIDP VID_PWRGD PC210 0.1U_0402_16V7K VR_ON PG PR123 0_0603_5% 3.4K_0603_1% IN EN OUT GND 2 MIC5258_SOT23-5 2 PR266 PU27 PC172 4.7U_0805_10V4Z PR265 1.74K_0603_1% 2 APW7057KC-TR_SOP8 + PQ60 SI4810DY_SO8 PC189 10U_1206_25VAK PHASE PC188 220U_D2_4VM 2 G S S S UGATE +5VALW PQ58 SI4800DY-T1_SO8 PC187 220U_D2_4VM S 1 FB BOOT VCC 1 OCSET PC209 7 PU31 PQ59 2N7002_SOT23 PD43 1N4148_SOD80 PC207 470P_0402_50V7K D G SUSP PR264 0_0402_5% 1U_0603_6.3V6M JUMP_43X118 PC203 PC208 0.1U_0402_16V7K PR263 8.45K_0603_1% PJP20 2 10_0603_1% 2 1 E PC171 4.7U_0805_10V4Z PR218 100K_0402_1% M11P: 1.2V > PR265=1.74K ohm M9-X: 1.5V >PR265=3K ohm PJP18 JUMP_43X118 2 +2.5V PC193 10U_1206_6.3V7K PR257 1K_0402_1% GND NC VREF NC VOUT NC TP +3VALW VCNTL PC194 1U_0603_6.3V6M +1.25VSP + PC199 @150U_D2_6.3VM PC197 0.1U_0402_16V7K PC200 @0.1U_0402_16V7K PR260 1K_0402_1% PC201 10U_1206_6.3V7K PQ57 2N7002_SOT23 S G D PR259 0_0402_5% SUSP 37,42 PR261 44.2_0402_1% 2 VIN APL5331KAC-TR_SO8 PC198 100P_0402_50V8J PC195 10U_1206_6.3V7K PC196 4.7U_0805_6.3V6K PR258 100_0402_1% 1 1 +1.8VSP ADJUST PU29 +3VS PU30 APL1085UC-TR_TO252 VIN VOUT 2 PJP19 JUMP_43X118 1 2 4 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D VGA/1.8V/VCCVID/1.25V Size Document Number Rev 0.1 B Date: Tuesday, June 08, 2004 Sheet E 53 of 65 PR269 @100K_0402_1% 1CORE_REF +5VS_CORE For Prescott: Pop PR167 For Northwood: Pop PR269 PR1612 CM0_0402_5% PR163 CM+ 0_0402_5% PR166 2 1 PC202 100U_25V_M PC130 100U_25V_M PC120 0.1U_0805_25V7K + PC119 2200P_0402_50V7K 10U_1206_25VAK PC118 10U_1206_25VAK 2 G S D 2 PC135 0.1U_0805_25V7K 2 PC134 2200P_0402_50V7K 10U_1206_25VAK PC133 OAIN- 10U_1206_25VAK PC132 10U_1206_25VAK PC131 + PC141 0.47U_0603_16V7K When mode control signal is high/ low, the VR will operate to Northwood/ Prescott load line VID5(12.5) should be pulled high, when the VR operates to Nothwood load line +VCC_CORE PR162 1K_0603_1% H_BOOTSELECT=1 PRESCOTT FB H_BOOTSELECT=0 NORTHWOOD S B+ +VCC_CORE D G PQ45 2N7002_SOT23 PC117 10U_1206_25VAK PC116 1 1 PD27 SKS30-04AT_TSMA PL13 0.5U_CXZM1350-R50_35A_20% CORE_REF VCCSENSE @0_0402_5% PR245 PR164 499_0402_1% OAIN+ PR165 100K_0402_1% PQ33 PR244 0_0402_5% +VCC_CORE 2N7002_SOT23 150K_0402_1% PR168 9.31K_0603_1% PQ44 2N7002_SOT23 PR133 10K_0402_5% B CM PR159 OAIN+ 100K_0402_1% 2 PR160 20K_0402_1% 1 C E 0_0402_5% PC138 PR156 0_0402_5% PR157 PR155 0_0603_5% 2 PD29 SKS30-04AT_TSMA 100P_0402_50V8J CS- PQ30 SI7392DP_SO8 DLS CS+ PQ32 SI7886DP_SO8 PC140 1 MAX1546 PC142 @100P_0603_50V8G PR167 100K_0402_1% 1 22.6_0402_1% PR111 150_0402_1% PC124 CM+ +CPU_B+ 37 CMP PR145 0.001_2512_5% H_BOOTSELECT PR110 38 PC129 @4700P_0402_25V7K 100P_0603_50V8J PC139 2200P_0402_50V7K VROK OFS 39 PR173 1K_0603_1% 0.47U_0603_16V7K PR153 PQ43 499_0402_1% D0 CSN CMN PC180 BSTM PC128 0.22U_0603_16V7K PQ31 SI7886DP_SO8 D1 VCORE_PWRGD OAIN- 40 CSP PR146 1K_0603_1% SKS30-04AT_TSMA D2 PR15 0_0402_5% PGND 31 PD26 D3 32 PC182 1000P_0402_50V7K D4 DLS OAIN+ 2 D5 34 PL12 0.5U_CXZM1350-R50_35A_20% PQ29 SI7886DP_SO8 @100K_0402_1% PR109 2 19 0_0402_5% PR220 20 0_0402_5% PR221 21 0_0402_5% PR222 22 0_0402_5% PR223 23 0_0402_5% PR224 24 0_0402_5% PR225 25 33 LXS +5VS_CORE DAP202U_SOT323 PD28 2 OAIN+ OAIN- DHS G PQ40 S 2N7002_SOT23 PL11 FBM-L18-453215-900LMA90T_1812 100K_0402_1% FB DLM PQ28 SI7886DP_SO8 15 PR154 CCI 30 35 14 VDD BSTS S PQ27 SI7392DP_SO8 PR143 0_0603_5% GNDS 29 BSTM 0.22U_0603_16V7K GND 13 DLM S G D +CPU_B+ PC115 1 PR158 2.87K_0603_1% PQ26 11 27 28 PR141 0_0402_5% CCV LXM DHM 12 26 G D PC181 470P_0402_50V7K VCC BSTM 1 2 10 PC122 1 PC126 1000P_0402_50V7K VCCSENSE OAIN+ ILIM SUS V+ 36 OAIN- 1K_0603_1% SKIP# 100P_0603_50V8J VID5 VID4 VID3 VID2 VID1 VID0 PR152 @1.74K_0402_1% 18 PC125 PC136 470P_0402_50V7K FB PR170 0_0402_5% REF SKIP PR148 PR149 0_0402_5% 17 16 @0_0402_5% S1 2.2U_0805_16V4Z PC123 1U_0603_16V6K SHDN# 0_0402_5% VSSSENSE +VCCVID 270P_0402_50V7K 47K_0402_1% PR147 10_0603_1% S0 PR171 OAIN+ D 12 PR144 +5VS_CORE TON PR140 100K_0402_1% 0.22U_0603_16V7K PC114 TIME CORE_REF 1 VID_PWRGD PR138 @0_0402_5% PR139 0_0402_5% CORE_REF PR246 PU9 PQ20 2N7002_SOT23 PR180 30.1K_0603_1% PR137 PR227 0_0402_5% DPRSLPVR S G PR136 100K_0402_1% 2.87K_0603_1% PR132 0_0402_5% MMBT3904_SOT23 PR135 100K_0402_1% +5VS_CORE FB D SKIP# CPUCLK_STP# 2N7002_SOT23 PJP14 +5VS 1 2 +5VS_CORE JUMP_43X79 Title CPU_CORE(1) Size A3 Date: Document Number Tuesday, June 08, 2004 Rev 0.1 Sheet 54 of 65 +5VS_CORE DLM PR172 PD33 2 +CPU_B+ 12 CM+ CM- PC144 0.1U_0805_25V7K PC148 2200P_0402_50V7K 10U_1206_25VAK PC147 10U_1206_25VAK PC146 PC145 PR181 1K_0603_1% +CPU_B+ GND 12 PR210 49.9K_0402_1% CS- CM+ CM- PC168 1000P_0603_16V7K PC169 CS+ MAX1980 1000P_0603_16V7K PD42 SKS30-04AT_TSMA PR204 CS+ PC162 10U_1206_25VAK PC161 10U_1206_25VAK PC160 10U_1206_25VAK PC159 2200P_0402_50V7K 1K_0603_1% 200K_0603_1% PGND PC163 0.1U_0805_25V7K +VCC_CORE PC166 0.47U_0603_16V7K ILIM 13 2 PC167 PR206 19 2200P_0402_50V7K 20K_0402_1% DD/ PQ39 SI7886DP_SO8 10 PL15 0.5U_CXZM1350-R50_35A_20% 15 DL LX TON 0.22U_0603_16V7K COMP POL PR199 0_0603_5% PC164 PQ38 SI7886DP_SO8 14 16 DH BST PR200 0_0603_5% VCC PQ37 SI7392DP_SO8 17 LIMIT 12 V+ PD41 @1SS355_SOD323 18 PU11 PR2012 0_0603_5% VDD TRIG 1 PC165 0.22U_0603_16V7K 2 1 11 1 2 PR196 0_0603_5% PR198 10_0603_1% PR188 0_0603_5% +VCC_CORE 1000P_0603_16V7K 0.47U_0603_16V7K SKS30-04AT_TSMA PD39 1SS355_SOD323 20 PC158 2.2U_0805_16V4Z 1 PC155 MAX1980 DLS +5VS_CORE PC170 1000P_0603_16V7K PC152 SKIP# PR207 CM- 13 PR189 49.9K_0402_1% CM+ +VCC_CORE CS- PD36 PC156 GND 100P_0603_50V8J ILIM DD/ 2 PC153 PR183 19 2200P_0402_50V7K 20K_0402_1% 200K_0603_1% PR184 PC154 PQ36 SI7886DP_SO8 10U_1206_25VAK CS+ 1 PGND PL14 0.5U_CXZM1350-R50_35A_20% 10 PQ35 SI7886DP_SO8 DL LX 15 PR177 0_0603_5% PC150 0.22U_0603_16V7K 14 16 DH PR174 0_0603_5% 2 BST PR17827 POL 0_0603_5% PC151 TON 0.22U_0603_16V7K COMP PD35 @1SS355_SOD323 6> CORE_REF VCC PQ34 SI7392DP_SO8 17 V+ +VCC_CORE PR187 0_0603_5% LIMIT PU10 10_0603_1% 18 PR176 12 VDD 2.2U_0805_16V4Z 2 PC149 11 TRIG 20 0_0603_5% 1SS355_SOD323 100P_0603_50V8J 2 CS- SKIP# Compal Electronics, Inc Title +CPU_CORE(2) Size Document Number Date: Tuesday, June 08, 2004 Rev 0.1 Sheet 55 of 65 Version Change List ( P I R List ) for Power Circuit Item Page# D C Title 54,55, wrong layout 56,57 pad 56 DPRSLPVR Date Request Owner 03/25/2003 03/25/2003 Compal Issue Description Solution Description Rev change to correct layout pad on PU7, PU11, PU16 and PQ24 Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234 for deeper-sleeper mode voltage setting Compal Reserve a jumper for power consumption measurement Add PJP14 0.2 Compal Change the netname +5VS_CORE for power consumption measurement Change Netname of +5VS_CORE 0.2 0.2 Compal PU8, PU9, PU10, 0.2 56 CPU VR-Cont 57 CPU VR-Cont 51 RTC charger 03/25/2003 Compal use two resistors for RTC charger protection Add PR230 55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry Add PJP15 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power +1.5VALWP 03/27/2003 Compal Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal 54 03/25/2003 03/25/2003 D 0.2 wrong layout pad C 0.2 0.2 Change VD, and VDD of PU16 from +2.5VALWP to +2.5VS; Connect PR235.2 to +2.5VS add a resistor PR235 for Stand/By pin for test Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal 0.2 0.2 B B A A Compal Electronics, Inc Title Changed-List History-1 Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 56 of 65 BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify 1.Add an independent power source for VGA chip because of ATI request 92.03.17 -Add U53(SI9185),C913,R1023,C912,C914 and related net (Modify CKT,BOM&Layout) 2.Modify the Audio related schematic for Customer request 92.03.17 -Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) (Modify CKT,BOM&Layout) 3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request 92.03.18 -Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929, U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 (Modify CKT,BOM&Layout) -Add R1048,R1050,R1052 (Modify CKT&Layout) 4.Modify the Audio related schematic for Customer request 92.03.20 -Add R1063(39K_0603_1%);Del R768(0_1206_5%) (Modify CKT,BOM&Layout) -Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K (Modify CKT&BOM) -Change R974 from @100K_0402_5% to 100K_0402_5% (Modify CKT&BOM) -Change R972 from 100K_0402_5% to @100K_0402_5% (Modify CKT&BOM) -Change JP41.3 from GNDA to +5VAMP (Modify CKT&Layout) 5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request 92.03.21 -Add R1083,R1084,R1085(@0_0402_5%) (Modify CKT&Layout) -Change R300 from 100_0402_5% to @100_0402_5% (Modify CKT&BOM) 6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request 92.03.21 -Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) (Modify CKT,BOM&Layout) -Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net (Modify CKT,BOM&Layout) -Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) (Modify CKT&Layout) 7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request 92.03.21 -Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) (Modify CKT,BOM&Layout) Reserve the SMBus1/2 swap Resistors for ATI request 92.03.23 -Add RP150(0_0404_4P2R_5%) (Modify CKT,BOM&Layout) -Add RP149(@0_0404_4P2R_5%) (Modify CKT&Layout) Add the power source +5V and +1.5VS discharge circuit for ATI request 92.03.23 -Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) (Modify CKT,BOM&Layout) 10 Modify the ON1 related to speed up the power sequence for ATI request 92.03.23 -Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59); Del PR113(47K),PC183(0.1U) (Modify CKT,BOM&Layout) 11 Modify power source CAP.'s value by Brian 92.03.24 -Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348 from 0.01U_0402_16V7K to 2200P_0402_25V7K (Modify CKT&BOM) -Add C956(180P_0603_50V8J) (Modify CKT,BOM&Layout) 12 Del Via Hole on schematic for ME modify 92.03.24 -Del H15(H_C374D295),H29(H_C197D91) (Modify CKT,BOM&Layout) 13.Modify the MiniPCI and BlueTooth conn related for Customer request 92.03.24 -Change R1083,R1084 from @0_0402_5% to 100_0402_5% (Modify CKT&BOM) -Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) (Modify CKT,BOM&Layout) 14.Swap the USB20*P3* and USB20*P5* for Customer request 92.03.24 A-TEST SMT BUILT -Modify R1079~R1082,JP43,R980,R981's connection (Modify CKT&Layout) 15.Modify the schematic after rev0.1 debug by Brian 92.03.24 -Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%; Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%; R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%; R833 from @0_0402_5% to 0_0402_5% (Modify CKT&BOM) 16.Modify the schematic H_BOOTSELECT related by Power Team 92.03.25 -Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) (Modify CKT,BOM&Layout) -Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% (Modify CKT&BOM) 17.Add a power transfer circuit to fix +1.5VS leakage issue 92.03.25 -Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K), C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) (Modify CKT,BOM&Layout) 18 Modify power source Resistor and CAP.'s value for power sequence 92.03.26 -Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K (Modify CKT&BOM) -Change R903,R362 from 100K_0402_5% to 91K_0402_5% (Modify CKT&BOM) -Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% (Modify CKT,BOM&Layout) 19 Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT 92.03.26 -Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) (Modify CKT,BOM&Layout) 20 Add the power source +3VS discharge circuit by Brian 92.03.26 -Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 (Modify CKT&BOM) 21 Change the Resistor's value for ATI recommend 92.03.26 -Change R264 from 169_0603_1% to 2N7002 1N_SOT23 (Modify CKT&BOM) 22 Correct material layout footprint and pin define 92.03.26 -Change Y1,Y3 PCB Footprint and JP32 pin define (Modify CKT&Layout) 23 Add the power source +3V discharge circuit for ATI request 92.03.27 -Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) (Modify CKT,BOM&Layout) 24 Change the power sequence related part's power source by Brian 92.03.27 -Change U32's power source from +3VS to +3VALW (Modify CKT&Layout) 25 Modify the power sequence related schematic for timing by Brian 92.03.27 -Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K (Modify CKT&BOM) -Add Q110(2N7002_SOT23) (Modify CKT,BOM&Layout) 26 Modify the SPDIF related schematic for Customer request 92.03.28 -Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) (Modify CKT,BOM&Layout) 27 Modify the NEC USB2.0 Controller Chip related schematic for Customer request 92.03.28 -Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) (Modify CKT,BOM&Layout) -Add R1104(@0_0402_5%) (Modify CKT&Layout) -Change R1024 from 0_0402_5% to @0_0402_5% (Modify CKT&BOM) 28 Update the material's Layout Footprint for error correction 92.03.28 -Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 (Modify CKT&Layout) 29 Modify the related schematic after Brian Review 92.03.31 -Del R288(56_0402_5%) (Modify CKT,BOM&Layout) 2 30 Modify the related schematic after Layout check 92.03.31 -Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC (Modify CKT&Layout) 31 Update the material's Layout Footprint for error correction 92.04.02 -Update JP40 (Modify CKT&Layout) 32 Modify the schematic for cost down 92.04.04 -Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) (Modify CKT&BOM) PLEASE SEE NEXT PAGE Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(1) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 1 Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 57 of 65 BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify define sequence error 92.04.08 1.1394 Connector JP33 Pin -Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4 (Modify EE Circuit) 2.LED Circuit to Power Button(PRES)modify 92.04.09 -Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES) (Modify EE Circuit) -Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119 (Modify EE Circuit) 3.Add +1.2VS_VGA Discharge Circuit 92.04.09 -Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP) (Modify EE Circuit) 4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit 92.04.09 -Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC (Modify EE Circuit) BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify Footprint error 92.04.09 1.FDD Connector JP38 PCB -Check JP38 ACES_85201-2605_26P (Modify Layout) 2.Power Switch U53 PCB Footprint error 92.04.09 -Change U53 SI9185_MLP33-8->MSOP8 (Modify Layout) 3.Crystal Y4 PCB Footprint error 92.04.09 -Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA (Modify Layout) 4.USB Key Connector JP46 Part error 92.04.09 -Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES 85201-0405 4P P1.0(ACES_85201-0405_4P) (Modify Layout) 5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep 92.04.09 Change BOM & Layout LED D57 Footprint 92.04.15 -Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8 (Modify Layout) MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In 92.04.10 -Update BOM add R326 (Modify EE Circuit) Change Layout Keyboard Connector JP13 Footprint 92.04.15 -Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P (Modify Layout) Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule 92.04.11 -Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2) (Modify EE Circuit) -Del R399(DDRA_CS#0), R400(DDRA_CS#2) (Modify EE Circuit) Change Layout FrontSideboard Connector JP42 Footprint 92.04.15 -Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P (Modify Layout) Check BOM USB OUVUR R893&R895 470K change to 330K 92.04.12 2 Add SUSP# pull Down 92.04.14 -Add EC U15.115 to SUSP# pull Down @R1123 to GND (Modify EE Circuit) 10 Add CPUCLK_STP# pull High Circuit 92.04.14 -BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3 (Modify EE Circuit) -Add CPUCLK_STP# pull High @R1126 to +3VS (Modify EE Circuit) -Add CPUCLK_STP# serial resistor R1125 to Q96.2 (Modify EE Circuit) 11 Change BOM R585 75 -> & R996 33 -> 68(REFCLK1_NB) 92.04.15 12 SIO Circuit All Power Plan +3V -> +3VS 92.04.15 13 Add NEC USB Corstralor U54.P19(SRMOD) pull Low 92.04.16 -Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND (Modify EE Circuit) -Update BOM R1046 -> @ (Modify EE Circuit) 14 Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#) 92.04.16 3 15 Change BOM C364, C23, C24, C40, C798 47U -> 22U 92.04.17 16 Change BOM R380 430 -> 412(U27.A9/CPU_RSET#) 92.04.17 17 Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @ 92.04.17 18 Change BOM C191 4.7U -> 2.2U 92.04.17 19 Change BOM C202,C931 10U -> 2.2U 92.04.17 20 Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @ 92.04.17 21 Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22) 92.04.17 22 Add R1135 -> VTT_PWRGD(U15.165) 92.04.18 23 Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#) 92.04.18 24 Change BOM Q67 -> @, R884 -> @(CARD_LED#) 92.04.18 25 Change BOM C966 22U -> 0.1U 92.04.18 4 26 Change BOM C916 -> @, C917 -> @ 92.04.18 27 Change BOM R1019 -> @(U47.17 JS1) pull High 92.04.18 28 Change BOM R264 47 -> 137(U6.PM27 AGPTEST) 92.04.18 PLEASE SEE NEXT PAGE Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 58 of 65 BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify 29 Change U13.P1 U13.P5, U14.P1 U14.P5 92.04.21 30 Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# -> AGP_SBA0(DDC_CLK) 92.04.21 1 31 Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P 92.04.21 32 Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, 92.04.21 33 Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23 92.04.21 34 Del @R1104, @R1089, @C953(CLK_SB_48M) 92.04.21 35 Add @R1142 pull High(DOCK_LOUT_R) 92.04.21 36 Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull High +3V 92.04.21 37 Add R520 @ -> Del @(JP8.AE26 COMPAT#) 92.04.23 38 Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1) 92.04.23 39 Change BOM R553 100 -> 49.9, R558 169 -> 100 92.04.23 40 Change BOM R383 100 -> 49.9, R384 169 -> 100 92.04.23 2 41 Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR) 92.04.23 42 Change BOM R40 @ -> Del @, R53 -> @ 92.04.23 43 Change BOM R792 -> @, R795 @ -> Del @ 92.04.23 44 Change BOM R230 -> @ 92.04.23 45 EMI add R1144 for SSOUT 92.04.24 46 EMI change D73, D74, D75, D76 part 92.04.24 47 Add C974 pull Low for +NB_AGP 92.04.24 48 Change BOM R623 10K -> 92.04.28 49 Change BOM R622, R619 10K ->@ 92.04.28 BHR60 SI STEP LA-1811 REV:0.4 EE MEN Change C781 SE077106M00 -> SE054106Z10 92.04.28 Change C963 -> @ 92.04.28 Change C974 -> @ 92.04.28 Change C742 -> (SD028000000) Ohm 92.04.28 Add R771 -> (SD028470100) 4.7K Ohm 92.04.28 Add C747 -> (SE070104Z00) 0.1U 92.04.28 DEL R761,R762 92.04.28 4 PLEASE SEE NEXT PAGE Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(3) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 59 of 65 BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR It em Fixed Issue Reason for change PAGE Prevent CPUCLK_STP# abnormal state happened Prevent power leakage M.B V er Modify List 5 Cha nge R1125 from 4.7K to 12K 26 Delete R1126 29 Change R40 from 10K to 1K Change the power of U8 from +3VS to +3VALW 1 Power saving Change the power of Fans from +5VALW to +5VS ATI recommendation Add C9 74 5 Add VGA DRAM size detect function 17 Add R 1149 for 128MB VGA DRAM (un-populate for 64MB) Add CS1# for Hynix 8Mx32 VGA DRAM Add Nets: NMCSA1# and NMCSB1# Change M9+X VGA_CO RE from +1.5VS to individual power source 21 Delete JOPEN3 Delete useless components Delete R538 25 Delete C96 27 Delete Q114, Add R1145 , 19, 2 , 23 2 Update with Item23 Solve power leakage from CRT 25 Change R619.1 and R622.1 net from +5VS to CRT_VCC 10 Prevent DPRSLPVR abnormal state happened 26 Change R 1001 from 100K to 47K, R1002 from to 47K 11 Using rechargeable RTC battery for HP's request 26 Delete D66, D71 and D72; Add D9 (BAS40-04, the same as LA-1761 D30); Change BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1) 12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798 from 2u to @10u; Change C801 from 1000p to @1000p 13 Enhance brightness of blue LEDs , 45 Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882, R885, R 888, R889, R890, R925 and R1136 to 220 44 14 Solve PWR_ACTIVE LED function fail issue Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C to +5VALW; Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 to PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS 42 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 46 Add R1147 and R1148; Change U15.76 net from N.C to PWR_ACTIVE_PRES#; Change U15.87 net from N.C to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to PWR_ACTIVE _PAV# 15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 16 Add discharge components 49 Add R372, R1095 , R1102, Q36, Q103 and Q109 17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-176 JP2) 18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 19 Increase MONO_IN voltage level 37 Ch ange R738 from 2.4K to 10K 20 Decrease Audio AMP Gain 38 C hange R971 from 100K to @100K; Change R973 from @100K to 100K Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(4) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 60 of 65 BHR60 from SI-1 to DB(15.4") REV:0.4 -> 0.5 It em LA-1811 Fixed Issue HW PIR Reason for change 21 PAGE RTL8 101L no need transistor for 3.3V to 2.5V anymore 34 REALTEK recommendation M.B V er Modify List Delete Q55, R944 and C668 Change R704 f rom 5.6K_0402_5% to 5.6K_0402_1% 22 Connector Spec change for ME's request 44 Change PC B Footprint from SUYIN_020167MR004SX01ZR_4P to suyin_020167mr004s511zu_4p for JP18 , JP19 and JP20 23 Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 24 Delete useless components with BOM 1 Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1 151 26 Add components for EMI 37 Add R1 152 40 Add L65 ~ L78 40 Add L79 ~ L97 Solve DOS cold-boot shunt down issue Delete C256 Decrease overshoot & undershoot 25 Add R1153 a nd R1154 29 Change SB GPIO and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 30 Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 31 The pin-definition of FDD conn was error on rev0.5 M/B 40 Correct the pin-definition for JP38 32 VIA recommendation 40 Change RP119 from 1K to 330; Delete RP121; Add R? and R? 33 Enhance brightness of Docking LEDs 41 Ch ange R880 from 10K to 470 34 To support wake-up function with TP 44 Change TP power from +5VS to +5V 35 Delete useless components Delete R535, R536, R9 91 and R992 12 Delete U 53, C912~C914, D79~D82, R954, R1010~R1012 and R1023 17 Delete Q15 and R251 20 Delete R1022 24 Delete R211 and R216 25 Delete C93~C95 a nd C930 BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6 HW PIR Delete R574, R1086 and C952 Delete R210 for UMA only 25 27 10 24 26 Delete Q113, R1124 and D91; Add D93 27 Delete RP149, RP150, R1145 and Q114 29 Delete R53 37 Delete L45, R1019, Y6, R756, C740 and C741 38 Delete R1142 39 Delete RP153 and R1132 36 To improve RTC accuracy 26 Change Y1 f rom +/-20ppm to +/-10ppm 37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37 C11 to G_RST# 38 Add components for EMI 37 Add L98 and L99 39 Improve Audio quality 40 Add components for ID & ME 41 Modify +5V power-up timing to lead +3V 6 40 Add C97 5, C976, CP15~CP17 37 Delete C753~C756; Add R1165~R1168 and C979 38 Add R1158 and R116 4; Exchange the nets of JP41.2 and JP41.3 41 Add R1 161 42 Add D92 49 Ch ange R904 from 91K to 47K Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(5) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 61 of 65 BHR60 from SI-1 to PV LA-1811 REV:0.6 It em Fixed Issue-> 0.7 HW PIR Reason for change 42 PAGE Correct Y1 and Y3 pin-out Modify List 26 M.B V er Using pin-1 and pin-2 of these crystals 46 Delete R65, R66, R67, R70, R72, R75, R79, R82, R86 R89, R94 and R95 43 ATI Product Advisory, refer to PA_218IXP0T1 44 44 Solve CD-ROM audio noise issue 30 Delete C11 45 Solve audio noise issue 37 Change R733 from +5VS to +5VAMP_CODEC 46 F or E MI 38 Add L100, L101, L102 and L103 47 For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 48 ATI recommendation 27 Change RP12 from 10K to 2.2K 46 Add R1 175 1 49 Delete useless components 46 Delete D69 and D70 50 To support wake-up function with TP 46 Delete RP154; Add R1169, R1170 , R1171 and R1172 51 Solve M10 can't power up issue 49 Delete C844 52 Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 53 Modify brightness of LEDs 42 Ch ange R901 from 27K to 6.8K 2 Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre 45 54 Fast power on for battery only 55 Change R306 from 100K to 470; Delete Q112 Improve contact Move JP2(CD- ROM conn.) right 0.65mm 56 Correct Caps LED and Numl LED placement Exchange the placement of these LEDs 57 Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 58 Reserve for EMI 37 Add JOPEN6, JOPE N7 and JOPEN8 59 Improve USB2.0 signal quality 36 Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2 60 Reserve VRAM detect function for ATI recommendation 17 Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS 61 F or E MI 38 48 36 24 26 28 37 41 25 Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A)1 Delete C110~C115 C hange L89, R1079 & R1080 to CHB1608U301 Ad d C855, C856, C907 and C908 Change L11 & L12 to MBV2012301YZT Change PCI clock damping resisters to 39 ohm Add C873~C881, C980~C 983; Change R60~R62 to MBV2012301YZT Delete R769 & R770; Add C984 ~C992 & L104 Add L105 Add C993 & C994 62 Reduce GHI# "LOW" voltage level Change R527 to 300 ohm 63 Fix "Pop" sound during boot up 64 For PCBA skew reducing 65 TI recommendation 66 Solve audio L/R swap issue 67 45 37 Improve NIC transmit return loss Add C9 79 Change R885, R888, R890, R1136 and R925 to 130 32 Add R1 177 37 Change R750 & R753 to 27 ohm 44 Delete R327 & C305 34 Ch ange U41 to NS0019 45 42 Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(6) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 62 of 65 BHR60 LA-1811 REV:1.0 ->1A It em HW PIR Fixed Issue Reason for change 67 PAGE M.B V er Modify List reserve Hynix DDR blue screen issue when boot to Win XP 16 Add R1 180 1A F or E MI 43 Connect MiniPCI clamp (pin1 27 and pin128) to GND 1A For EC NS97551 +3VALW undershoot issue 46 Add D94 a nd R1178 1A 46 Delete JP21 47 Delete JP22 Reserve for when you connect the dock station cable in unit playing an audio occur a speaker switch 46 Add R1179 a nd C995 1A The region is ME height limited zero 54 Delete PJP10 than short it directly 1A 68 1 69 Delete unnecessary component 70 71 72 1A 73 74 75 76 2 77 78 79 80 81 82 83 3 84 85 86 87 88 89 90 91 4 Title Compal Electronics, Inc H/W2 EE Dept PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 63 of 65 Version Change List ( P I R List ) for Power Circuit Item Page# D C 56 DPRSLPVR Request Owner 03/25/2003 03/25/2003 Compal Compal Issue Description Solution Description Rev wrong layout pad change to correct layout pad on PU7, PU11, PU16 and PQ24 Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234 for deeper-sleeper mode voltage setting Reserve a jumper for power consumption measurement Add PJP14 0.3 CPU VR-Cont 57 CPU VR-Cont 51 RTC charger 03/25/2003 Compal use two resistors for RTC charger protection Add PR230 55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry Add PJP15 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power 54 +1.5VALWP 10 54 +1.5VALWP 11 56 CPU DPRSLPVR 12 54 55 56 13 56 15 50 50 16 51 17 51 18 52 19 20 PWR JUMP CPU DPRSLPVR Vin DETECTOR Precharge Battery OTP 03/25/2003 03/25/2003 03/27/2003 Compal Compal Compal 04/16/2003 Compal 04/16/2003 Compal 04/16/2003 Compal 04/18/2003 Compal 04/30/2003 04/30/2003 Compal Compal D 0.2 PU8, PU9, PU10, 56 14 A 54,55, wrong layout 56,57 pad Date B Title Change the netname +5VS_CORE for power consumption measurement Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal change 1.5V time sequence 0.3 Change Netname of +5VS_CORE 0.3 0.3 C 0.3 0.3 Change VD, and VDD of PU16 from +2.5VALWP to +2.5VS; Connect PR235.2 to +2.5VS add a resistor PR235 for Stand/By pin for test Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal 0.3 0.3 0.4 Change power time-sequence of 1.5VSP input power Change DPRSLPVR design Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode0.4 For DFX issuse Change power JUMP SIZE to follow new jump role to make ACIN to enable to pull low Reserve DPRSLPVR function and add a PR136 for +5VS_CORE signal Change PR8 form 10k_0603 to 0K_0603 BOM error Change PR1 from 10k_0603 to 100k_0603 Change DPRSLPVR design 0.4 0.4 0.4 Change PC20 from 22u to 1u ;PR40&PR42 from 100k to 150k; PC80 from 1u to 47u To change feekbeck time 04/30/2003 Compal 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 53 5V/3.3V/12V 04/30/2003 Compal To improve the 3V output ripple Voltage B 0.4 0.4 to S-812C33AUA-C2N 0.4 0.4 to EC11FS2 0.4 Delet PC77 A 0.4 Compal Electronics, Inc Title Changed-List History-1 Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 64 of 65 Version Change List ( P I R List ) for Power Circuit Item Page# Title Date Request Owner Issue Description Solution Description Rev D 55 1.2VS_VGA 22 50 Precharge detector 23 51 21 24 56,57 25 52 26 55 C 27 B Colok THROTTLING CPU_CORE(1&2) 04/30/2003 05/16/2003 Compal Compal BOM errors Add PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70) System can't power on by battery 05/16/2003 Compal 05/16/2003 Compal Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form 84.5K to 11.5K To modify the circuit Change the freqeuce 300k to 200k To modify the charger circuit 1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA 07/4/2003 Compal 56 CPU_CORE 29 56,57 CPU_CORE(1&2) 30 50 DC_in 31 52 Charger 32 53 3V/5V/12V 07/4/2003 07/4/2003 08/4/2003 08/4/2003 08/4/2003 Compal To modify the DCR sense To improve the CPU_CORE effecient Compal For Gibson issue ,add two schottky diodes Compal To modify the Precharge circuit Compal C add PR124(11.5k_0603) 0.5 Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402) ,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet PR86,PR88,PR90,PR93 To modify THE CPU Load line form -1.5mV/A to -2.2mV/A Compal 0.5 Add PR194(1K) 0.5 ,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355) Compal 28 0.6 Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6 add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3) 0.7 Add PD30(1SS355_SOD323) To solve the DCR sense for 5V OCP issue ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA_S 0.7 change PR81(1.27k) ,PR78(1.54K),PR79(0_0402) ,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add PR241(1.24k),PR242(620 ohm),PR243(698 ohm) 56 CPU_CORE 08/4/2003 Compal 34 52 Charger 08/4/2003 Compal To improve the charger feedback loop for charger noise issueChange PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 52 2004.05.31 To modify THE CPU Load line form -2.2mV/A to -1.5mV/A, and senes CPU VCC and VSS change 2.5V from fix to adjust 0.6 Change PR158,PR180 from 2k to 3.4k 33 35 0.5 delet PR138 ; add PR187(0_0603)&PR188(0_0603) 05/16/2003 3V/5V/12V 0.5 Change PR5 from 150k to 180k Charger 53 D 0.4 Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k B 0.7 Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm) and PR245(0 ohm) 0.7 0.7 Add pr267, PR268 and PC211 A A Compal Electronics, Inc Title Changed-List History-1 Size Document Number Rev 0.1 LA-2411 Date: Sheet Tuesday, June 08, 2004 65 of 65 ... 99 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5... 0. 1U _04 02 _16 V4Z 0. 1U _04 02 _16 V4Z C 111 1 C 111 2 2 2 C 10 9 5 0. 1U _04 02 _16 V4Z C1 10 3 0. 1U _04 02 _16 V4Z 0. 1U _04 02 _16 V4Z C1 10 4 0. 1U _04 02 _16 V4Z C1 10 8 0. 1U _04 02 _16 V4Z C 111 3 C 10 9 6 C 10 9 7 0. 1U _04 02 _16 V4Z C 10 9 8 0. 1U _04 02 _16 V4Z... caps C 413 0. 1U _04 02 _10 V6K C 414 0. 1U _04 02 _10 V6K C 415 0. 1U _04 02 _10 V6K C 416 0. 1U _04 02 _10 V6K C 417 0. 1U _04 02 _10 V6K C 418 0. 1U _04 02 _10 V6K C 419 0. 1U _04 02 _10 V6K C4 20 0.1U _04 02 _10 V6K C4 21 0. 1U _04 02 _10 V6K