1131 compal nm a281p

A B C D E 1 LCFC Confidential G Project M/B Schematics Document 2 AMD FT3B Beema SOC with DDRIIIL AMD JET-LE 2014-2-12 REV:0.4 3 4 Title LC Future Center Secret Data Security Classification Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet E of 60 A B C D E LCFC confidential File Name : ACLU5&6 AMD Jet LE/ Topaz XT S3 Package: 23mmX23mm PCI-Express 4x Gen2 Page 18~24 PEG 0~3 VRAM 256/128*16 DDR3L*4 2GB/1GB Memory BUS (DDR3L) Single Channel DDR3L-SO-DIMM X2 Page 14,15 1.35V DDR3L 1600 MT/s UP TO 8G x Page 25~26 HDMI HDMI Conn USB Left Page 34 USB 3.0 1x AMD FT3b APU VGA CRT Conn USB 2.0 2x USB 2.0 Port8 USB 3.0 Port0 JUSB2 USB 2.0 Port3 Page 36 JUSB1 Page 41 eDP x2 Lane eDP Conn Beema 15W /2.4G USB2.0 1x Int Camera USB 2.0 1x Touch Screen Page 33 USB2.0 Port5 USB2.0 Port4 (Integrated FCH) 2 Int MIC Conn Page 33 USB2.0 1x USB Right USB2.0 Port0 JUSB3 (Debug Port) SATA HDD Page 42 SATA Gen3 SATA Port0 SATA ODD Page 42 USB2.0 1x BGA-769 24.5mm*24.5mm SATA Gen1 USB 2.0 1x RTL8111GUL (1G) RTL8106EUL (10M/100M) Page 38 Page 37 SD/MMC Conn USB Board SATA Port1 LAN Realtek RJ45 Conn Cardreader Realtek RTS5170 USB2.0 Port2 PCIe 1x PCIe 1x NGFF Card WLAN&BT PCIe Port1 USB2.0 Port6 Page 40 PCIe Port2 SPI BUS HD Audio Page 4~9 Codec SPI ROM 8MB Page 07 Sub-board ( for 14") POWER BOARD NS-A272 USB Board  NS-A271 SPK Conn Conexant CX20752 Page 43 Page 43 Sub-board ( for 15") EC ITE IT8586E-LQFP Page 44 HP&Mic Combo Conn USB Board Touch Pad Page 45 Int.KBD Page 45 Thermal Sensor NCT7718W POWER BOARD  NS-A273 USB Board  NS-A275 ODD Board NS-A274 Page 39 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D E Sheet of 60 A B Voltage Rails ( O > Means ON C E , X > Means OFF ) Board ID need to be update! +5VS +1.8VS +1.5VS B+ +5VALW VL +3VALW +3VL +1.8VALW SIGNAL STATE +3VS power plane D +1.35V +0.95VS (+VSYSMEN) +0.675VS +APU_CORE +APU_CORE_NB SLP_S3# SLP_S5# +VALW +V +VS Clock BOARD Config GPIOxx HIGH HIGH ON ON ON ON S1 (Power On Suspend) HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF S5 (Soft OFF) LOW LOW ON OFF OFF OFF GPIOxx GPIOxx S0 (Full ON) Function +VGA_CORE State +0.95VALW +3VGS +1.8VGS +1.35VGS USB Port Table +0.95VGS USB 2.0 USB 3.0 S0 O O O S3 O O O S5 S4/AC O S5 S4/ Battery only S5 S4/AC & Battery don't exist O X X O EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 APU_SCLK0 APU_SDATA0 X O X X X X X X X xHCI BOM Structure Table External USB Port RIGHT USB (2.0) N/A Card Reader LEFT USB (2.0) Touch Screen Camera Blue Tooth N/A LEFT USB (3.0) N/A BOM Structure @ ME@ 14@ 15@ UMA@ PX@ 8106EUL@ 8111GUL@ GIGA@ TS@ ZODD@ AOAC@ HDT@ Kabini@ SDV@ PCIE PORT LIST GPU IT8586E X BATT V IT8586E IT8586E SODIMM Port WLAN Thermal Sensor X X X X X V V V X +3VALW +3VALW IT8586E V +3VS +3VS_VGA X IT8586E +3VS APU X +3VS EHCI SMBUS Control Table SOURCE Port X X APU X APU_SIC APU_SID V APU_SIC APU_SID APU Charger 3 GPP V X GFX Device Address Battery 0X16 Thermal Sensor 1001_100xb Charger 0001 0010 b GPU 0x41(default) APU Thermal Diode TBU For 15" part UMA SKU ID part Discrete GPU SKU ID part 8106EUL LAN part 8111GUL LAN Part Giga LAN Part Touch Screen part Zero Power ODD part AOAC support part HDT Debug part Kabini APU part SDV PWR part GPU X EC SM Bus2 address Address For 14" part Device VRAM Device Connector N/A WLAN LAN N/A +3VS EC SM Bus1 address BTO Item Not stuff X76 SAMSUNG 2G S2G@ M2G@ H2G@ S1G@ M1G@ H1G@ X76 MICRON 2G X76 HYNIX 2G X76 SAMSUNG 1G X76 MICRON 1G X76 HYNIX 2G APU SM Bus address Device Address DDR DIMMA 1001 000Xb DDR DIMMB 1001 010Xb WLAN RSVD Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D E Sheet of 60 Beema (MEM & PCIE I/F) D D UC1A OK MEMORY DDRA_MA[15 0] DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15 AG38 W35 W38 W34 U38 U37 U34 R35 R38 N38 AG34 R34 N37 AN34 L38 L35 DDRA_BS0# DDRA_BS1# DDRA_BS2# AJ38 AG35 N34 M_ADD0 M_DATA0 M_ADD1 M_DATA1 M_ADD2 M_DATA2 M_ADD3 M_DATA3 M_ADD4 M_DATA4 M_ADD5 M_DATA5 M_ADD6 M_DATA6 M_ADD7 M_DATA7 DDRA_BS0# DDRA_BS1# DDRA_BS2# DDRA_DM[7 0] M_ADD9 M_DATA8 M_ADD10 M_DATA9 M_ADD11 M_DATA10 M_ADD12 M_DATA11 M_ADD13 M_DATA12 M_ADD14 M_DATA13 M_ADD15 @ TC10 B32 B38 G40 N41 AG40 AN41 AY40 AY34 Y40 M_DATA14 C OK DDRA_DQS[0 7] OK DDRA_DQS#[0 7] DDRA_DQS[0 7] DDRA_DQS#[0 7] TC15 TC16 M_DATA16 M_BANK2 M_DATA17 M_DM0 M_DATA19 M_DM1 M_DATA20 M_DM2 M_DATA21 M_DM3 M_DATA22 M_DM4 OK OK SODIMM1 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_CLK2 DDRA_CLK2# DDRA_CLK3 DDRA_CLK3# DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_CLK2 DDRA_CLK2# DDRA_CLK3 DDRA_CLK3# AC35 AC34 AA34 AA32 AE38 AE37 AA37 AA38 M_DATA23 M_DM6 M_DATA24 M_DM7 M_DATA25 M_DM8 M_DATA26 M_DQS_H0 M_DATA28 M_DQS_L0 M_DATA29 M_DQS_H1 M_DATA30 M_DQS_L1 G38 MEM_MA_RST# MEM_MA_EVENT#AE34 MEM_MA_RST# MEM_MA_EVENT# M_DATA31 M_DQS_L2 M_DATA32 M_DQS_H3 M_DATA33 M_DQS_L3 M_DATA34 M_DQS_H4 M_DATA35 M_DQS_L4 M_DATA36 M_DQS_H5 M_DATA37 M_DQS_L5 M_DATA38 M_DQS_H6 SODIMM0 OK SODIMM1 DDRA_CKE0 DDRA_CKE1 DDRA_CKE2 DDRA_CKE3 L34 J38 J37 J34 DDRA_ODT0 DDRA_ODT1 DDRA_ODT2 DDRA_ODT3 AN38 AU38 AN37 AR37 DDRA_CS0# DDRA_CS1# DDRA_CS2# DDRA_CS3# AJ34 AR38 AL38 AN35 DDRA_RAS# DDRA_CAS# DDRA_WE# AJ37 AL34 AL35 +MEM_VREF T_APU_M_VREFDQ AD40 AC38 DDRA_CKE0 DDRA_CKE1 DDRA_CKE2 DDRA_CKE3 M_DATA39 M_DQS_H7 M_DATA40 M_DQS_L7 M_DATA41 M_DQS_H8 M_DATA42 M_DQS_L8 M_DATA43 M_CLK_H0 M_DATA45 M_CLK_L0 M_DATA46 M_CLK_H1 M_DATA47 OK SODIMM0 OK SODIMM1 OK SODIMM0 DDRA_ODT0 DDRA_ODT1 DDRA_ODT2 DDRA_ODT3 DDRA_CS0# DDRA_CS1# DDRA_CS2# DDRA_CS3# OK OK OK OK DDRA_RAS# DDRA_CAS# DDRA_WE# SODIMM1 M_CLK_H2 M_DATA48 M_CLK_L2 M_DATA49 M_CLK_H3 M_DATA50 M_CLK_L3 M_DATA51 M_RESET_L M_DATA53 M_EVENT_L M_DATA54 M41 N40 T41 U40 L40 M40 R40 T40 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 AF40 AF41 AK40 AK41 AE40 AE41 AJ40 AJ41 DDRA_DQ36 DDRA_DQ37 DDRA_DQ34 DDRA_DQ35 DDRA_DQ32 DDRA_DQ33 DDRA_DQ38 DDRA_DQ39 OK WLAN PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 LAN PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 OK P_GPP_RXP0 P_GPP_TXP0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 R5 R4 P_GPP_RXP1 P_GPP_TXP1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 N5 N4 P_GPP_RXP2 P_GPP_TXP2 P_GPP_RXN2 P_GPP_TXN2 N10 N8 P_GPP_RXP3 P_GPP_TXP3 P_GPP_RXN3 P_GPP_TXN3 +0.95VS_GFX_APU RC7 1.69K_0402_1% P_TX_ZVDD W8 L2 L1 ACLU1 PCIE_PTX_DRX_P4 PCIE_PTX_DRX_N4 1U_0402_10V6-K 1U_0402_10V6-K CC21 CC22 PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 J2 J1 PCIE_PTX_DRX_P3 PCIE_PTX_DRX_N3 1U_0402_10V6-K 1U_0402_10V6-K CC19 CC20 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 H2 H1 P_RX_ZVDD_095 W7 P_TX_ZVDD_095 Net name changed to same as K2 K1 +0.95VS_GFX_APU P_RX_ZVDD 1K_0402_1% PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 WLAN OK LAN OK OK swap DQ32/33 and DQ36/37 @ 09/06 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 L5 L4 RC8 C P_GFX_RXP0 P_GFX_TXP0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 J5 J4 P_GFX_RXP1 P_GFX_TXP1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 G5 G4 P_GFX_RXP2 P_GFX_TXP2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 D7 E7 P_GFX_RXP3 P_GFX_TXP3 G2 G1 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 1U_0402_10V6-K 1U_0402_10V6-K CC11 PX@ CC12 PX@ PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 F2 F1 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 1U_0402_10V6-K 1U_0402_10V6-K CC13 PX@ CC14 PX@ PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 E2 E1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 1U_0402_10V6-K 1U_0402_10V6-K CC15 PX@ CC16 PX@ AM41 DDRA_DQ40 AN40 DDRA_DQ41 AT41 DDRA_DQ42 AU40 DDRA_DQ43 AL40 DDRA_DQ44 AM40 DDRA_DQ45 AR40 DDRA_DQ46 AT40 DDRA_DQ47 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 D2 D1 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 1U_0402_10V6-K 1U_0402_10V6-K CC17 PX@ CC18 PX@ PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 GPU OK OK P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_P[0 3] OK PCIE_CTX_C_GRX_N[0 3] OK ROUTE PCIE-LINK DIFF PAIR @ 85 OHM +/- 10% PCIE_CRX_GTX_P[0 3] FT3 REV 0.53 PCIE_CRX_GTX_N[0 3] @ Beema FT3-REV-0P53_BGA769 AV41 DDRA_DQ48 AW40 DDRA_DQ49 BA38 DDRA_DQ55 AY37 DDRA_DQ51 AU41 DDRA_DQ52 AV40 DDRA_DQ53 AY39 DDRA_DQ54 AY38 DDRA_DQ50 swap DQ55 and DQ50 @ 09/06 M0_CKE0 M0_CKE1 M_DATA56 M1_CKE0 M_DATA57 M1_CKE1 M_DATA58 M0_ODT0 M_DATA60 M0_ODT1 M_DATA61 M1_ODT0 M_DATA62 M1_ODT1 M_DATA63 M0_CS_L0 M_CHECK0 M0_CS_L1 M_CHECK1 M1_CS_L0 M_CHECK2 M1_CS_L1 M_CHECK3 BA36 AY35 BA32 AY31 BA37 AY36 BA33 AY32 M_CHECK7 V41 W40 AB40 AC40 U41 V40 AA41 AB41 M_ZVDDIO_MEM_S AD41 M_CHECK4 @ OK R10 R8 M_CLK_L1 M_DATA59 B UC1B M_DQS_L6 M_DATA55 OK DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 M_DQS_H2 M_DATA52 F40 F41 K40 K41 E40 E41 J40 J41 M_DM5 M_DATA44 SODIMM0 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 PCIE M_BANK1 M_DATA27 B33 DDRA_DQS0 A33 DDRA_DQS#0 B40 DDRA_DQS1 A40 DDRA_DQS#1 H41 DDRA_DQS2 H40 DDRA_DQS#2 P41 DDRA_DQS3 P40 DDRA_DQS#3 DDRA_DQS4 AH41 DDRA_DQS#4 AH40 AP41 DDRA_DQS5 DDRA_DQS#5 AP40 BA40 DDRA_DQS6 DDRA_DQS#6 AY41 AY33 DDRA_DQS7 DDRA_DQS#7 BA34 @ 1T_DDRA_DQS8 AA40 @ 1T_DDRA_DQS#8 Y41 B37 A38 D40 D41 B36 A37 B41 C40 OK DDRA_DQ[63 0] M_BANK0 M_DATA18 DDRA_DM0 DDRA_DM1 DDRA_DM2 DDRA_DM3 DDRA_DM4 DDRA_DM5 DDRA_DM6 DDRA_DM7 T_DDRA_DM8 DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 M_ADD8 M_DATA15 OK OK OK OK B30 A32 B35 A36 B29 A30 A34 B34 M_RAS_L M_CHECK5 M_CAS_L M_CHECK6 M_WE_L DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 B ECC +VSYSMEM_APU OK M_VREF M_VREFDQ TC35 RC1 39.2_0402_1% FT3 REV 0.53 @ Beema FT3-REV-0P53_BGA769 R103 connection to VDDIO_SUS should be directly to the plane without a long trace OK +VSYSMEM_APU MEM Reference Voltage RC4 1K_0402_1% EVENT# pull high +MEM_VREF @ 2 CC2 1000P_0402_50V7K CC1 1U_0402_10V6-K RC5 1K_0402_1% CC115 47U_0402_6.3V6K +VSYSMEM_APU RC6 OK 1K_0402_5% UC1 UC1 UC1 UC1 BEEMA AM6400ITJ44JB 2.4G ZM181103J4470 1.8G ZM151103J4470 1.5G ZM1332M2J2370 1.35G SA000065O10 SA000067O00 SA000067P00 MEM_MA_EVENT# Layout: Place within 1000 SA000067Q00 mils of the APU socket A ZZZ A PCB NM-A281 DA60000U810 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (MEM & PCIE I/F) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet of 60 Beema (DISPLAY/CLK/MISC) S0 @ APU_SIC RC2281 TB RS APU_SID RC2291 TB RS 0_0402_5% @ 0_0402_5% EC_SMB_CK2 EC_SMB_DA2 +3VS APU_CRT_HSYNC RC67 RC66 @ 1K_0402_5% 1K_0402_5% NOTE: APU_CRT_HSYNC PU FOR AMD INTERNAL,PD FOR CUSTOMER D D +3VS UC1C DISPLAY/SVI2/JTAG/TEST OK OK HDMI APU_HDMI_TX2+ APU_HDMI_TX2- APU_HDMI_TX1+ APU_HDMI_TX1- APU_HDMI_TX0+ APU_HDMI_TX0- APU_HDMI_CLK+ APU_HDMI_CLK- eDP Net name changed to same as A9 B9 TDP1_TXP0 DP_150_ZVSS TDP1_TXN0 DP_2K_ZVSS APU_HDMI_TX1+ APU_HDMI_TX1- A10 B10 TDP1_TXP1 DP_DIGON B16 DP_150_ZVSS A21 DP_2K_ZVSS B17 O PCH_ENBKL A17 O PCH_ENVDD DP_VARY_BL A18 O PCH_EDP_PWM TDP1_TXN1 APU_HDMI_TX0+ APU_HDMI_TX0- A11 B11 TDP1_TXP2 APU_HDMI_CLK+ APU_HDMI_CLK- A12 B12 TDP1_TXP3 CPU_EDP_TX0+ CPU_EDP_TX0- A4 B4 LTDP0_TXP0 LTDP0_AUXP LTDP0_TXN0 LTDP0_AUXN CPU_EDP_TX1+ CPU_EDP_TX1- A5 B5 LTDP0_TXP1 LTDP0_HPD TDP1_TXN2 TDP1_AUXP TDP1_TXN3 TDP1_HPD OK OK APU_PWROK H_PROCHOT# TB RS B14 A6 B6 LTDP0_TXP2 LTDP0_TXN2 DAC_GREEN A14 T_TDP0_TXP3 T_TDP0_TXN3 A7 B7 LTDP0_TXP3 DAC_BLUE B15 TC17 TC18 @ @ T_DISP_CLKP T_DISP_CLKN K15 H15 APU_SVT APU_SVC APU_SVD APU_SVT APU_SVC APU_SVD I G31 O D27 I/O E29 B22 B21 APU_SIC APU_SID 3.3V Level DISP_CLKIN_H DAC_VSYNC SVT SVD A16 DAC_ZVSS SIC H27 H29 D25 A27 B27 A26 B26 B28 I A28 I B24 I A24 I AV35 AU35 E33 APU_TEST4_THERMDA APU_TEST5_THERMDC APU_TEST6 NC APU_TEST14_BP0 RC55 APU_TEST15_BP1 RC56 APU_TEST16_BP2 RC57 APU_TEST17_BP3 RC58 APU_TEST18_PLLTEST1 RC44 APU_TEST19_PLLTEST0 RC45 APU_TEST25_H_BYPASSCLK RC59 APU_TEST25_L_BYPASSCLK RC1491 @ APU_TEST28_H_PLLCHARZ @ APU_TEST28_L_PLLCHARZ @ APU_TEST31_MEM_TEST A29 H21 H25 APU_TEST34_L_TSTCLKIN_L APU_TEST36 APU_TEST37 @ TC28 AJ10 AJ8 R32 N32 AP29 APU_TEST42_USB_ATEST0 APU_TEST43_USB_ATEST1 APU_TEST39 APU_TEST40 APU_TEST41_TMON_CAL 1 1 TC25 TC26 TC29 TC30 TC27 TEST4 SID TEST5 TEST6 LDT_RST_L TEST15 APU_PWROK APU_PWROK_R I B19 OD A19 APU_PWROK TEST16 TEST17 LDT_PWROK TEST18 PROCHOT_L TEST25_H TEST19 ALERT_L TEST25_L TDI TEST28_L TDO TEST31 OK @ TC31 APU_VDD_SEN_L @ @ TC60 TC61 VDDIO_MEM & VDD_0.95 D23 G23 VDDIO_SUS_SENSE E25 E23 VDD_095_FB_H VDD_095_FB_L AV33 AU33 RC31 RC32 OK APU_CRT_G OK APU_CRT_B OK CPU_EDP_HPD APU_CRT_DDC_CLK APU_CRT_DDC_DATA 4.7K_0402_5% 4.7K_0402_5% 2.2K_0402_5% 4.7K_0402_5% 4.7K_0402_5% RC13 RC14 2 1 1K_0402_5% 1K_0402_5% 2 300_0402_5% 300_0402_5% RC163 APU_RST# APU_PWROK 100K_0402_5% STUDY C OK 499_0402_1% @ @ @ @ @ @ @ TC19 TC20 Thermal Sensor? TC21 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% +1.8VS_APU 510_0402_1% 510_0402_1% TC22 TC23 TC24 OK +1.8VS_APU A29 For STAMP APU_TEMPIN0 TCK TMS RSVD TRST_L TEST36 DBRDY TEST37 DBREQ_L TEST42 APU_VDDNB_SEN_H APU_VDD_SEN_H RC18 2 1 +1.8VS_APU OK APU_CRT_HSYNC APU_CRT_VSYNC DAC_ZVSS 1.8V 1.8V OK OK 150_0402_1% ALERT# APU_PROCHOT#_R 1 2 OK APU_CRT_R G19 I/OAPU_CRT_HSYNC E19 O DAC_SDA TEST14 D29 D31 D35 D33 G27 B25 A25 150_0402_1% SVC APU_RST_L APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# 150_0402_1% RC22 APU_CRT_DDC_CLK APU_CRT_DDC_DATA I B20 OD A20 OK RC21 OK OK RC160 RC161 @ RC162 RC53 RC54 The processor asserts PROCHOT_L when the hardware thermal control (HTC) is active External hardware can assert PROCHOT_L to reduce APU power consumption by forcing HTC activation OK OK CPU_EDP_HPD D19 D21 DAC_SCL APU_RST# APU_RST#_R CC4 150P_0402_50V8-J @ APU_HDMI_HPD DISP_CLKIN_L 1.8V APU_PROCHOT#_R A22 OD B18 ALERT# OK OK APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA CPU_EDP_AUX CPU_EDP_AUX# RC23 LTDP0_TXN3 DAC_HSYNC CPU_EDP_HPD DAC_RED TEST28_H H17 IPD T_TDP0_TXP2 T_TDP0_TXN2 A19 For STAMP APU_TEMPIN2 CC3 150P_0402_50V8-J @ CPU_EDP_AUX CPU_EDP_AUX# @ @ A20 For STAMP APU_TEMPIN1 RC29 Kabini@ 0_0402_5% @ 0_0402_5% RC147 D15 E15 @ @ RC28 Kabini@ 0_0402_5% Output to APU Vcore VR SVID EN Pin APU_HDMI_HPD TC52 TC53 OK OK OK APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA H19 IPD TC62 TC63 OK OK OK Avoid plane splits and signal plane changes, route on single routing layer D17 E17 APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA APU_HDMI_HPD APU_CRT_DDC_CLK APU_CRT_DDC_DATA +3VS OK OK OK PCH_ENBKL PCH_ENVDD PCH_EDP_PWM SDA LTDP0_TXN1 Lane is OK to support FHD Panel SVID I/F: Do not terminate OK OK 150_0402_1% 2K_0402_1% In I2C mode AUXP pins change to SCL, and AUXN pins change to DisplayPort Auxiliary Channel pins are dual-mode pins TDP1_AUXN CPU_EDP_TX1+ CPU_EDP_TX1- C RC10 RC11 DP_BLON CPU_EDP_TX0+ CPU_EDP_TX0- ACLU1 APU_HDMI_TX2+ APU_HDMI_TX2- OK OK OK OK OK VDDCR_NB_SENSE TEST43 VDDCR_CPU_SENSE TEST39 VDDIO_MEM_S_SENSE TEST40 VSS_SENSE TEST41 DP_STEREOSYNC E21 VDD_095_FB_H VDD_095_FB_L @ @ @ @ @ O APU_TEST35_STEREOSYNC To drive active shutter glasses for stereoscopic 3D viewing on 120-Hz panels RC60 RC61 RC62 RC63 1 1 @ @ @ @ 2 2 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% OK +1.8VS_APU RC65 RC64 @ @ 1K_0402_5% 1K_0402_5% return path is optional, so remove FT3 REV 0.53 @ B Beema FT3-REV-0P53_BGA769 B OK +1.8VS_APU +1.8VS_APU +1.8VS_APU +1.8VS_APU HDT+ Header +1.8VS_APU JHDT1 @ APU_RST# 2A 2Y GND VCC 1 HDT@ RC38 1K_0402_5% UC2 HDT@ APU_PWROK RC33 300_0402_5% HDT@ RC27 300_0402_5% HDT@ APU_PWROK_BUF APU_TRST# 1A 1Y SN74LVC2G07YZPR_WCSP6 Change to APU_RST#_BUF SN74LVC2G07DCK SOT 11 13 15 APU_PWROK RC2031 APU_RST# RC1931 10K_0804_8P4R_5% RCP1 HDT@ 0_0402_5% APU_PWROK_BUF 0_0402_5% APU_RST#_BUF @ @ 17 19 10 11 12 13 14 15 16 17 18 19 20 APU_TCK APU_TMS APU_TDI APU_TDO 10 APU_PWROK_BUF 12 APU_RST#_BUF 14 APU_DBRDY 16 APU_DBREQ# 18 APU_TEST19_PLLTEST0 20 APU_TEST18_PLLTEST1 1K_0804_8P4R_5% CC29 SAMTE_ASP-136446-07-B Zx05 A 1U_0402_10V6-K A 1 CC5 1U_0402_10V6-K HDT@ RCP4 HDT@ Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (DISPLAY/CLK/MISC) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Symbol Sheet of 60 +3VS 1 RC170 2.2K_0402_5% RC171 2.2K_0402_5% DIMM1, DIMM2, Mini CARD Default is H RC210 10K_0402_5% @ SMB_CLK_S3 RC187 10K_0402_5% 14@ 1 CC6 150P_0402_50V8-J SMB_CLK_S3 RC189 10K_0402_5% PX@ RC188 10K_0402_5% RC209 10K_0402_5% @ D SMB_DATA_S3 LPC_RST#_R RC190 10K_0402_5% @ 2 33_0402_5% RC74 APU_LPC_RST# D RC185 10K_0402_5% UMA@ 1 BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 GPIO49 GPIO51 GPIO71 GPIO70 CC121 150P_0402_50V8-J 2 RC186 10K_0402_5% 15@ RC78 100K_0402_5% @ ID1 HI is UMA , LO is DIS PCIE_RST#_R 2 33_0402_5% RC75 PLT_RST# SMB_CLK_S3 OK +3VS ID0 HI is 15' , LO is 14' PLT_RST# & APU_LPC_RST OK Broad ID OK Beema (GEVENT/GPIO/SD/AZ) SMB_DATA_S3 GPIO49/51/71 require external PH or PL, so used for Board ID GPIO70 is reserved and has interanl PH RSMRST# OK +3VS 10K_0402_5% 10ms T RC86 EC_RSMRST# DC2 RSMRST#_R Need update symobol 2 10K_0402_5% SYS_RESET# PM_SLP_S3# PM_SLP_S5# EC_SYS_PWRGD IPU S5 PM_SLP_S3# PM_SLP_S5# RC87 RC88 TB @ RS 0_0402_5% 1.8V Strap Pin PH TB RS TB @ RS 0_0402_5% 0_0402_5% @ I AY5 I BA8 IAM19 I PU AY7 PCIE_WAKE#_RA I PUAW11 PWRBTN#_R SYS_PWRGD_R O AY3 O BA5 PM_SLP_S3#_R PM_SLP_S5#_R TB RS S4/S5 is Low SD_PWR_CNTL SD_PWR_CTRL BA23 SD_CLK/GPIO73 AY22 I PU SD_CLK_R LPC_RST_L PCIE_RST_L RSMRST_L SD_CMD/GPIO74 SD_CD/GPIO75 PWR_BTN_L SD_WP/GPIO76 PWR_GOOD SYS_RESET_L/GEVENT19_L WAKE_L/GEVENT8_L SLP_S3_L SLP_S5_L AU13 AY10 AY6 APU_TEST0 APU_TEST1 APU_TEST2 @ TC36 @ TC37 AY23 I PUSD_CMD_R AY20 I PU SD_CD# BA20 I PU SD_WP SD_DATA0/GPIO77 BA22 I SD_DATA1/GPIO78 AY21 I SD_DATA2/GPIO79 AY24 I SD_DATA3/GPIO80 BA24 I SD_LED/GPIO45 TC51 @ TC64 @ TC65 @ RC85 10K_0402_5% DC4 RB751V-40_SOD323-2 SYS_PWRGD_R Need update symobol AY25 O @ TC38 @ TC39 @ TC40 PUSD_DATA0_R PUSD_DATA1_R PUSD_DATA2_R PUSD_DATA3_R @ TC41 @ TC42 @ TC43 @ TC44 CC9 1U_0402_6.3V6K @ OK OK RC192 @ 0_0402_5% PCIE_WAKE#_RA APU_GEVENT22# @ 0_0402_5% RC184 DC3 1 TEST1/TMS SCL0/GPIO43 TEST2 SDA0/GPIO47 @ TC45 SD_LED AU25 AV25 EC_WAKE# I I I I KBRST# GATEA20 EC_SCI# PU PU PU PU AR23 AR31 AN5 AL7 KBRST_L SCL1/GPIO227 GA20IN/GEVENT0_L SDA1/GPIO228 ODD_EN WLAN_CLKREQ# LAN_CLKREQ# GPU_CLKREQ# HDA_SDIN0 IPU S5 I I I I I CLK_REQ#0 WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ#3 GPU_CLKREQ# OC1# for USB2.0x1 OC1# for USB3.0x2 SDM10U45LP-7_DFN1006-2-2 @ I PU IPU S5 AC_PRESENT_R ODD_DETECT# GPI TC48 @ IR_TX1 TC49 @ IR_RX1 =>GPO ODD_EN ODD_DETECT# LPC_PME_L/GEVENT3_L LPC_SMI_L/GEVENT23_L GPIO49 USB_OC1# USB_OC2# RC1021 0_0402_5% @ GPIO51 AP15 AV13 BA9 BA10 AV15 PU AU29 PU AW29 PU AR27 PU AV27 PU AY29 USB_OC0# USB_OC1# USB_OC2# USB_OC3# AY8 AW1 AV1 AY1 HDA_BITCLK HDA_SDOUT HDA_SDIN0_R HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SYNC HDA_RST# AN2 AN1 AK2 AK1 AM1 AL2 AM2 AL1 +3VS 32K_X1 AJ2 32K_X2 AJ1 AY11 BA11 OK OK SMB_CLK_S3 SMB_DATA_S3 AC_PRES/IR_RX0/GEVENT16_L DEVSLP[0]/GPIO55 IR_TX0/GEVENT21_L GPIO57 IR_TX1/GEVENT6_L GPIO58 IR_RX1/GEVENT20_L DEVSLP[1]/GPIO59 IR_LED_L/LLB_L/GPIO184 GPIO64 SPKR/GPIO66 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 CLK_REQ1_L/GPIO61 GPIO69 CLK_REQ2_L/GPIO62 GPIO70 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 CLK_REQG_L/GPIO65/OSCIN GPIO174 AP27 AY28 BA28 AV23 AP21 BA26 AV19 AY27 BA27 AU21 AY26 AV21 AM21 BA3 AV17 GEVENT4_L BA4 GEVENT7_L AR15 GEVENT10_L AP17 GEVENT11_L AP11 GEVENT17_L AN8 BLINK/GEVENT18_L AU17 GEVENT22_L BA6 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L USB_OC1_L/TDI/GEVENT13_L USB_OC2_L/TCK/GEVENT14_L USB_OC3_L/TDO/GEVENT15_L AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 APU_SCLK1 APU_SDATA1 RC164 RC165 I S0 GPI I S0 GPI IPU S0 =>GPO RC194 IPU S0 =>GPO IPU S0 =>GPO IPU S0 GPI IPU S0 =>GPO IPU S0 IPU S0 IPU S0 I S0 I S5 =>GPO =>GPO GPI GPI 1 BOARD_ID0 OK CMOS_ON# BOARD_ID1 OK 0_0402_5% @ PCH_BT_OFF# PCH_WLAN_OFF# APU_GPIO59 PXS_RST#_R @ TC57 @TC57 GENINT1_L/GPIO32 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 BA29 AP23 OK OK 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 2 PCIE_WAKE#_RA PBTN_OUT# PM_SLP_S3# PM_SLP_S5# AC_PRESENT_R ODD_EN ODD_DETECT# APU_SCLK1 APU_SDATA1 ODD_DA# APU_GEVENT22# USB_OC0# USB_OC1# USB_OC2# USB_OC3# 100K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 2 2 1 2 2 APU_TEST2 APU_TEST1 APU_TEST0 GPU_CLKREQ# 15K_0402_5% 15K_0402_5% 15K_0402_5% 10K_0402_5% @ @ @ @ @ 1 1 1 RC168 RC169 RC172 RC173 RC174 RC230 CMOS_ON# SATA0_DEVSLP PCH_BT_OFF# PCH_WLAN_OFF# OK OK OK OK OK @ @ 1 1 1 1 2 1 1 RC91 RC83 RC89 RC90 RC208 RC214 RC218 RC109 RC110 RC219 RC216 RC94 RC95 RC96 RC97 @ @ @ @ @ C RC16 RC3 RC2 RC204 RSMRST#R PD is support Mirror core GEVENT2# APU_GEVENT4# APU_GEVENT7# @ TC54 @ TC55 ODD_DA# S5 APU_GEVENT22# APU_GPIO321 @ TC56 IPU S0 GPI VR_VGA_PWRGD OK PCH_BEEP Strap Pin PL AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 S0 PWR Domain S5 PWR Domain 10K_0402_5% 10K_0402_5% PXS_PWREN_R VGA_PWROK_R BOARD_ID3 BOARD_ID2 APU_GPIO174 APU_GEVENT10#1 APU_GEVENT11#1 IPU S5 IPU Strap Pin PH IPU S5 GPI LAN_CLKREQ# WLAN_CLKREQ# CLK_REQ#0 CLK_REQ#3 GPU_CLKREQ# VGA_PWROK_R +3VALW_APU TEST0 GPIO50 EC_WAKE# RC79 PBTN_OUT# PBTN_OUT# ACPI/SD/AZ/GPIO/RTC/MISC RC93 2 100K_0402_5% +1.8VALW_APU @ RC84 Panjit: BSS138 NXP: BSH111 Other one: FDV301N OR AO3414 +3VALW_EC +3VALW C 1.8V RSMRST#_R CC122 1U_0402_6.3V6K @ OK OK Provided test points or other means to allow access for debug purposes UC1D O AY4 O AY9 LPC_RST#_R PCIE_RST#_R RB751V-40_SOD323-2 SB00000PF0J SB50111001J (CRB PWR Dealy: 47K/1uF) RC81 10K_0402_5% RCP2 CMOS_ON# PCH_BT_OFF# PCH_WLAN_OFF# 10K_0804_8P4R_5% @ RC82 OK OK OK +1.8VALW_APU 2 100K_0402_5% +3VALW_EC +3VALW RSMRST#_R SYS_PWRGD_R HDA_BITCLK HDA_SDIN0_R HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 OK 100K_0402_5% 100K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 1 1 1 2 2 @ @ @ @ @ @ RC206 RC207 RC103 RC104 RC105 RC106 RC107 Integrated PU is not supported when the pin is configured for USB over current function ODD_DA# BLINK OK OK OK VR_VGA_PWRGD OK AZ_SYNC AZ_RST_L FANIN0/GPIO56 AV31 AU31 RTCCLK AV11 FANOUT0/GPIO52 APU_GPIO521 @ TC58 APU_GPIO561 @ TC59 X32K_X1 These GPIO pin use same one as Kabini CRB RC221 PX@ 10K_0402_5% PXS_PWREN_R RC222 PX@ 10K_0402_5% PXS_RST#_R RC223 @ 10K_0402_5% YC1 VR_VGA_PWRGD 32.768KHZ_12.5PF_200458-PG14 X32K_X2 @ IPU S5 Strap Pin PH SUSCLK OK FT3 REV 0.53 Beema FT3-REV-0P53_BGA769 VGA VR side has PH to +3VS B B RC108 1 20M_0402_5% RC224 @ 100K_0402_5% PXS_PWREN_R RC225 @ 100K_0402_5% PXS_RST#_R RC205 UMA@ 2K_0402_5% 2 CC118 20P_0402_50V8 @ @ @ CC119 20P_0402_50V8 RC226 RC227 RC211 RCP3 APU_GPIO174 APU_GEVENT4# APU_GEVENT7# @ PX@ PX@ PX@ RC92 RC12 RC9 RC15 AC_PRESENT PXS_PWREN PXS_RST# VGA_PWROK 2 2 0_0402_5% 1K_0402_5% 0_0402_5% 0_0402_5% AC_PRESENT_R PXS_PWREN_R PXS_RST#_R VGA_PWROK_R Output to GPU Vcore VR SVID EN Pin +3VALW_APU 10K_0402_5% 10K_0402_5% 10K_0402_5% VIL Max is 0.7V VR_VGA_PWRGD OK OK OK OK APU_GEVENT4# APU_GEVENT7# APU_GPIO174 CC141 1U_0402_10V6-K @ 10K_0804_8P4R_5% A A RCP6 HDA_RST_AUDIO# HDA_SYNC_AUDIO HDA_BITCLK_AUDIO HDA_SDOUT_AUDIO HDA_RST# HDA_SYNC HDA_BITCLK HDA_SDOUT 33_0804_8P4R_5% T PN change Idea pad PN:SD300003700 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (GEVENT/GPIO/SD/AZ) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet of 60 Beema (SATA/USB/LPC/SPI/CLK) D D Net name changed to same as ACLU1 UC1E CLK/SATA/USB/SPI/LPC OK HDD SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 OK SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 BA14 AY14 SATA_TX0P SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 BA16 AY16 SATA_RX0N SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 AY19 BA19 SATA_TX1P SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 AY17 BA17 SATA_RX1N AR19 AP19 SATA_ZVSS W4 USBCLK/14M_25M_48M_OSC SATA_RX0P USB_ZVSS AG4 USB_RCOMP USB_HSD0P AL4 AL5 USB20_P0 USB20_N0 USB_HSD0N SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P USB_HSD1N ODD SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 +0.95VS_APU SATA_RX1P USB_HSD2P USB_HSD2N RC114 RC115 OK 1 1K_0402_1% 1K_0402_1% SATA_CALRN SATA_CALRP SATA_ZVDD_095 USB_HSD3P USB_HSD3N +3VS OK RC113 @ 10K_0402_5% APU_GPIO67 O BA30 SATA_ACT_L/GPIO67 USB_HSD4P USB_HSD4N AY12 USB_HSD5P USB_HSD5N SATA_X2 USB_HSD6P USB_HSD6N CLK_PCIE_GPU CLK_PCIE_GPU# CLK_PCIE_WLAN CLK_PCIE_WLAN# CLK_PCIE_LAN CLK_PCIE_LAN# OK OK C OK CLK_PCIE_GPU CLK_PCIE_GPU# RC116 RC117 1 @ @ 0_0402_5% CLK_PCIE_GPU_R 0_0402_5% CLK_PCIE_GPU#_R CLK_PCIE_WLAN CLK_PCIE_WLAN# RC118 RC119 1 @ @ 0_0402_5% CLK_PCIE_WLAN_R 0_0402_5% CLK_PCIE_WLAN#_R CLK_PCIE_LAN CLK_PCIE_LAN# RC120 RC121 1 @ @ 0_0402_5% CLK_PCIE_LAN_R 0_0402_5% CLK_PCIE_LAN#_R TC32 U4 U5 GFX_CLKP USB_HSD7P GFX_CLKN USB_HSD7N AC8 AC10 GPP_CLK0P USB_HSD8P GPP_CLK0N USB_HSD8N AE4 AE5 GPP_CLK1P USB_HSD9P GPP_CLK1N USB_HSD9N AC4 AC5 GPP_CLK2P AA5 AA4 GPP_CLK3P USB_SS_0TXP GPP_CLK3N USB_SS_0TXN X14M_25M_48M_OSC USB_SS_0RXP X14M_25M_48M_OSC O AP13 @ 48M_X1 N2 USB_SS_ZVSS CLK_PCI_EC LPC_CLK1 RC122 RC123 OK OK OK OK OK OK 1 33_0402_5% 0_0402_5% Strap Pin PL AY2 Strap Pin PH AW2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# SERIRQ TC33 TC46 USB20_P5 USB20_N5 AD1 AD2 USB20_P6 USB20_N6 USB20_P0 USB20_N0 OK OK RIGHT USB (2.0) USB20_P3 USB20_N3 OK OK Card Reader P2 USB20_P2 USB20_N2 OK OK LEFT USB (2.0) P3 USB20_P4 USB20_N4 OK OK Touch Screen USB20_P5 USB20_N5 OK OK Camera USB20_P6 USB20_N6 OK OK Blue Tooth USB20_P1 USB20_N1 OK LEFT USB (3.0) X48M_X2 USB_SS_1RXP P2&P3 exchanged as layout request @ 09/12 AC1 AC2 AB1 AB2 USB20_P1 USB20_N1 AA1 AA2 Net name changed to same as AE10 USBSS_CALRN USBSS_CALRP USB30_RX_P1 USB30_RX_N1 R1 R2 1 RC130 RC131 1K_0402_1% 1K_0402_1% USB30_TX_P1 USB30_TX_N1 USB30_RX_P1 USB30_RX_N1 P8 ACLU1 +0.95VALW_USB3 C OK OK LEFT USB (3.0)OK Net name changed to same as ACLU1 W1 W2 LPCCLK0 AU7 AW9 AR4 AR11 SPI_DI/GPIO164 AR7 10 AU11 SPI_HOLD_L/GEVENT9_L SPI_WP_L/GPIO161 AU9 LPCCLK1 SPI_CLK/GPIO162 SPI_CS1_L/GPIO165 TC47 AE1 AE2 X48M_X1 @ AT2 AT1 AR2 AR1 Strap Pin PH AP2 AP1 @ AV29 AP25 @ AV2 @ USB20_P4 USB20_N4 USB30_TX_P1 USB30_TX_N1 USB_SS_1TXN LPCCLK0 LPCCLK1 AF1 AF2 V2 USB_SS_0RXN V1 USB_SS_1RXN OK OK USB20_P2 USB20_N2 T2 T1 USB_SS_1TXP N1 USB20_P3 USB20_N3 AG1 AG2 OK 11.8K_0402_1% AMD Debug port! AG7 AG8 AE8 USB_SS_ZVDD_095_USB3_DUAL GPP_CLK2N OK 48M_X2 AJ4 AJ5 RC138 SATA_X1 If the integrated clock generator is used, these pins are left unconnected BA12 @ TC34 CLK_USB48M SATA_TX0N LAD0 SPI_CS2_L/GPIO166 10 SPI_DO/GPIO163 LAD1 LAD2 LAD3 LFRAME_L SPI_CLK_R SPI_CS0#_R RC135 RC134 1 @ @ 0_0402_5% 0_0402_5% SPI_CLK SPI_CS0# SPI_SI_R SPI_SO_R SPI_HOLD#_R SPI_WP#_R RC136 RC137 RC178 RC179 1 1 @ @ @ @ 2 2 SPI_SI SPI_SO SPI_HOLD# SPI_WP# 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% SPI_CLK SPI_CS0# SPI_SI SPI_SO OK LDRQ0_L SERIRQ/GPIO48 LPC_CLKRUN_L LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L FT3 REV 0.53 @ Beema FT3-REV-0P53_BGA769 OK +3VALW_APU +3VS +3V_SPI APU SPI is ALW PWR B RC175 RC125 @ 0_0402_5% @ 0_0402_5% B +3V_SPI TB RS 8M ROM +3V_SPI 1 RC127 RC128 RC129 10K_0402_5% 10K_0402_5% 10K_0402_5% SPI_WP# SPI_HOLD# SPI_CS0# Change to PR??? 48MHz/10pF Crystal @ SPI_CLK RC126 @ 10_0402_5% CC127 10P_0402_50V8J For EMI OK 48M_X1 48M_X2 OK +3V_SPI 8MB SPI ROM SA000039A2J 64M W25Q64FVSSIG RC191 A OSC1 NC1 SA00005Z100 64M GD25B64BSIGR 1M_0402_5% UC5 YC2 NC2 OSC2 SPI_CS0# SPI_SO SPI_WP# 48MHZ_10PF_7V48000017 CC123 12P_0402_50V8-J CC124 12P_0402_50V8-J CS# DO CC10 1U_0402_10V6-K VCC HOLD# WP# CLK GND DI SPI_HOLD# SPI_CLK SPI_SI A W25Q64FVSSIG_SO8 Issued Date Change to 15pF as vendor suggest Title LC Future Center Secret Data Security Classification SJ10000IO00 TXC: 7V48000017 (48MHz) 2013/08/15 Deciphered Date 2013/08/15 Beema (SATA/USB/LPC/SPI/CLK) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet of 60 Beema (POWER & DECOUPLING) +1.35V APU GND +VSYSMEM J10 @ 1 JUMP_43X118 Need Short +3VS +3VS_APU RC30 0_0603_5% TB RS CC69 CC71 1 +VSYSMEM_APU +VSYSMEM 180P_0402_50V8-J +APU_CORE UC1F POWER J35 L32 L37 N35 R31 R37 U32 U35 W31 W32 W37 AA31 AA35 AC32 AC37 AE31 AE35 AG32 AG37 AJ35 AL32 AL37 AR35 PAD-OPEN 4x4m Need Short +3VALW_APU @J13 @ J13 PAD-OPEN 4x4m CC101 +1.8VALW Need Short 1U_0402_6.3V6K +1.8VALW_APU @ 0_0603_5% VDDIO_MEM_S_1 VDDCR_CPU_1 L21 VDDIO_MEM_S_2 VDDCR_CPU_2 L23 VDDIO_MEM_S_3 VDDCR_CPU_3 L25 VDDIO_MEM_S_4 VDDCR_CPU_4 L27 VDDIO_MEM_S_5 VDDCR_CPU_5 L29 CC117 CC126 VDDCR_CPU_8 N27 VDDIO_MEM_S_8 VDDIO_MEM_S_10 VDDCR_CPU_10 R23 VDDIO_MEM_S_11 VDDCR_CPU_11 R27 VDDIO_MEM_S_12 VDDCR_CPU_12 U21 CC97 CC98 CC99 C VDDIO_MEM_S_13 VDDCR_CPU_13 U23 VDDIO_MEM_S_14 VDDCR_CPU_14 U27 VDDIO_MEM_S_15 VDDCR_CPU_15 W21 CC100 VDDIO_MEM_S_16 VDDIO_MEM_S_17 VDDIO_MEM_S_18 VDDIO_MEM_S_19 VDDIO_MEM_S_20 VDDIO_MEM_S_21 VDDIO_MEM_S_22 VDDIO_MEM_S_23 180P_0402_50V8-J 4.7U_0603_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CC68 1U_0402_6.3V6K CC74 1U_0402_6.3V6K CC75 1U_0402_6.3V6K 1 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 180P_0402_50V8-J AL10 AL11 +1.8VALW_APU +0.95VALW 0.5A +0.95VALW_USB3 @ 13/17A 0_0603_5% TB RS +0.95VS_APU 0_0603_5% @ CC103 10U_0603_6.3V6M CC106 10U_0603_6.3V6M CC105 1U_0402_6.3V6K CC107 1U_0402_6.3V6K CC108 CC104 0.2A AL13 AM13 +0.95VALW_USB3 1A AR5 AU4 AV7 AW5 +0.95VALW_APU 0.5A 1U_0402_6.3V6K AE11 AE13 AJ11 AJ13 180P_0402_50V8-J 4.5uA 2 0_0402_5% @ CC109 1U_0402_6.3V6K CC111 1U_0402_6.3V6K CC112 1U_0402_6.3V6K CC113 1U_0402_6.3V6K VDD_33_ALW_1 VDD_33_1 VDD_33_ALW_2 VDD_33_2 VDD_095_1 VDD_095_USB3_DUAL_2 VDD_095_2 VDD_095_USB3_DUAL_3 VDD_095_3 VDD_095_USB3_DUAL_4 VDD_095_4 VDD_095_ALW_1 VDD_095_ALW_2 VDD_095_ALW_3 VDD_095_ALW_4 180P_0402_50V8-J C91,C89,C90 PLACE ON TOP LAYER CC91 1U_0402_6.3V6K CC92 1U_0402_6.3V6K +0.95VS_APU 1.5A CC79 +3VS_APU AM15 AM17 0.2A +0.95VS_APU 1U_0402_6.3V6K CC84 1U_0402_6.3V6K CC85 1U_0402_6.3V6K CC86 1U_0402_6.3V6K CC87 1U_0402_6.3V6K CC78 10U_0603_6.3V6M CC83 10U_0603_6.3V6M 0_0402_5% CC88 1U_0402_6.3V6K CC80 180P_0402_50V8-J +0.95VS @ J9 3A GND VSS_1 VSS_63 VSS_2 VSS_64 VSS_3 VSS_65 VSS_4 VSS_66 VSS_5 VSS_67 VSS_6 VSS_68 VSS_7 VSS_69 VSS_8 VSS_70 VSS_9 VSS_71 VSS_10 VSS_72 VSS_11 VSS_73 VSS_12 VSS_74 VSS_13 VSS_75 VSS_14 VSS_76 VSS_15 VSS_77 VSS_16 VSS_78 VSS_17 VSS_79 VSS_18 VSS_80 VSS_19 VSS_81 VSS_20 VSS_82 VSS_21 VSS_83 VSS_22 VSS_84 VSS_23 VSS_85 VSS_24 VSS_86 VSS_25 VSS_87 VSS_26 VSS_88 VSS_27 VSS_89 VSS_28 VSS_90 VSS_29 VSS_91 VSS_30 VSS_92 VSS_31 VSS_93 VSS_32 VSS_94 VSS_33 VSS_95 VSS_34 VSS_96 VSS_35 VSS_97 VSS_36 VSS_98 VSS_37 VSS_99 VSS_38 VSS_100 VSS_39 VSS_101 VSS_40 VSS_102 VSS_41 VSS_103 VSS_42 VSS_104 VSS_43 VSS_105 VSS_44 VSS_106 VSS_45 VSS_107 VSS_46 VSS_108 VSS_47 VSS_109 VSS_48 VSS_110 VSS_49 VSS_111 VSS_50 VSS_112 VSS_51 VSS_113 VSS_52 VSS_114 VSS_53 VSS_115 VSS_54 VSS_116 VSS_55 VSS_117 VSS_56 VSS_118 VSS_57 VSS_119 VSS_58 VSS_120 VSS_59 VSS_121 VSS_60 VSS_122 VSS_61 VSS_123 VSS_62 VSS_124 J3 J7 J8 J39 K11 K13 K17 K19 K21 K23 K25 K27 K29 K31 L3 L7 L8 L10 L11 L15 L19 L31 L39 L41 M1 M2 N3 N7 N15 N19 N25 N29 N31 N39 P1 P2 R3 R7 R15 R19 R25 R29 R39 R41 U1 U2 U3 U7 U8 U11 U15 U19 U25 U29 U31 U39 W3 W5 W11 W15 W19 W25 W29 W39 W41 Y1 Y2 AA3 AA7 AA8 AA11 AA15 AA19 AA25 AA29 AA39 AC3 AC7 AC11 AC15 AC19 AC25 AC29 AC31 AC39 AC41 AE3 AE7 AE25 AE29 AE32 AE39 AG3 AG5 AG10 AG11 AG13 AG15 AG19 AG25 AG29 AG31 AG39 AG41 AH1 AH2 AJ3 AJ7 AJ15 AJ17 AJ19 AJ23 AJ25 AJ29 AJ31 AJ32 AJ39 AL3 AL8 AL15 AL17 AL19 AL25 AL29 VSS_125 VSS_187 VSS_126 VSS_188 VSS_127 VSS_189 VSS_128 VSS_190 VSS_129 VSS_191 VSS_130 VSS_192 VSS_131 VSS_193 VSS_132 VSS_194 VSS_133 VSS_195 VSS_134 VSS_196 VSS_135 VSS_197 VSS_136 VSS_198 VSS_137 VSS_199 VSS_138 VSS_200 VSS_139 VSS_201 VSS_140 VSS_202 VSS_141 VSS_203 VSS_142 VSS_204 VSS_143 VSS_205 VSS_144 VSS_206 VSS_145 VSS_207 VSS_146 VSS_208 VSS_147 VSS_209 VSS_148 VSS_210 VSS_149 VSS_211 VSS_150 VSS_212 VSS_151 VSS_213 VSS_152 VSS_214 VSS_153 VSS_215 VSS_154 VSS_216 VSS_155 VSS_217 VSS_156 VSS_218 VSS_157 VSS_219 VSS_158 VSS_220 VSS_159 VSS_221 VSS_160 VSS_222 VSS_161 VSS_223 VSS_162 VSS_224 VSS_163 VSS_225 VSS_164 VSS_226 VSS_165 VSS_227 VSS_166 VSS_228 VSS_167 VSS_229 VSS_168 VSS_230 VSS_169 VSS_231 VSS_170 VSS_232 VSS_171 VSS_233 VSS_172 VSS_234 VSS_173 VSS_235 VSS_174 VSS_236 VSS_175 VSS_237 VSS_176 VSS_238 VSS_177 VSS_239 VSS_178 VSS_240 VSS_179 VSS_241 VSS_180 VSS_242 VSS_181 VSSBG_DAC VSS_182 VSS_243 VSS_183 VSS_244 AL39 AL41 AM11 AM27 AM31 AN3 AN7 AN39 AP31 AR3 AR13 AR17 AR21 AR25 AR29 AR39 AR41 AU1 AU2 AU3 AU15 AU19 AU23 AU27 AU39 AV9 AW3 AW7 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27 AW31 AW33 AW35 AW37 AW39 AW41 AY13 AY15 AY18 AY30 BA2 BA7 BA13 BA15 BA18 BA21 BA25 BA31 BA35 BA39 A15 AL31 AM29 D C VSS_184 VSS_185 VSS_186 FT3 REV 0.53 @ PAD-OPEN 4x4m FT3 REV 0.53 @ FT3-REV-0P53_BGA769 Beema FT3-REV-0P53_BGA769 Beema Need Short +0.95VS_GFX_APU +0.95VS_APU 0.6A RC145 @ TB RS FT3 REV 0.53 Beema UC4 GND 10K_0402_5% CC82 1U_0402_6.3V6K CC81 10U_0603_6.3V6M FT3-REV-0P53_BGA769 CC110 0.22U_0402_10V6K RC1461 1U_0402_6.3V6K A8 A13 A23 A31 A35 A39 B8 B13 B23 B31 B39 C1 C2 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 D9 D11 D13 E3 E4 E9 E11 E13 E27 E31 E35 E38 E39 G3 G7 G11 G13 G15 G17 G21 G25 G29 G35 G37 G39 G41 H11 H13 H23 H31 VDD_095_GFX_3 AA10 VDDBT_RTC_G @ 0_0402_5% 4.7U_0603_6.3V6K CC90 VDD_095_GFX_2 W10 AN4 TB @ RS CC89 A2 A3 B3 C3 AG23 AG27 AJ21 AJ27 VDD_095_5 AL21 VDD_095_6 AL23 VDD_095_7 AL27 VDD_095_8 AM23 VDD_095_9 AM25 VDD_095_USB3_DUAL_1 +1.5VS CC125 VDD_095_GFX_1 U10 +0.95VALW_APU TB RS VDD_18_2 VDD_18_4 +RTCBATT_APU B VDD_18_ALW_2 VDD_18_3 @ +0.95VALW VDD_18_1 180P_0402_50V8-J Wake-on-Ring supported: Connect to +1.5V S5 rail Wake-on-Ring not supported: Connect to +1.5V S0 rail +1.8VS_APU VDD_18_ALW_1 1U_0402_6.3V6K +APU_CORE_NB VDDIO_AZ_ALW_2 +3VALW_APU @ RC1421 B1 B2 VDDIO_AZ_ALW_1 1U_0402_6.3V6K +VDDIO_AZ_APU VDDCR_NB_4 N13 VDDCR_NB_5 N17 VDDCR_NB_6 R11 VDDCR_NB_7 R13 VDDCR_NB_8 R17 VDDCR_NB_9 U13 VDDCR_NB_10 U17 VDDCR_NB_11 W13 VDDCR_NB_12 W17 VDDCR_NB_13 AA13 VDDCR_NB_14 AA17 VDDCR_NB_15 AC13 VDDCR_NB_16 AC17 VDDCR_NB_17 AE15 VDDCR_NB_18 AE17 VDDCR_NB_19 AE19 VDDCR_NB_20 AG17 VDDCR_NB_21 AG21 +VDDIO_AZ_APU 1U_0402_6.3V6K CC70 VDDCR_NB_1 L13 0.1A RC144 CC73 CC77 VDDCR_CPU_16 W23 VDDCR_CPU_17 W27 VDDCR_CPU_18 AA21 VDDCR_CPU_19 AA23 VDDCR_CPU_20 AA27 VDDCR_CPU_21 AC21 VDDCR_CPU_22 AC23 VDDCR_CPU_23 AC27 VDDCR_CPU_24 AE21 VDDCR_CPU_25 AE23 VDDCR_CPU_26 AE27 @ CC67 CC76 VDDCR_NB_3 N11 CC96 RC143 10U_0603_6.3V6M VDDCR_CPU_9 R21 VDDIO_MEM_S_9 VDDCR_NB_2 L17 CC95 S0 DOMAIN RC139 CC94 S5 DOMAIN CC66 VDDCR_CPU_7 N23 VDDIO_MEM_S_7 TB RS CC93 180P_0402_50V8-J A23 For STAMP APU_TEMPRETURN 20/25A VDDCR_CPU_6 N21 VDDIO_MEM_S_6 @ RC1401 2 1U_0402_6.3V6K 0_0603_5% 0_0603_5% TB RS 2.9A CC102 UC1H GND TB @ RS RC1321 RC1331 1U_0402_6.3V6K UC1G +1.8VS @ 1U_0402_6.3V6K @J8 @ J8 CC72 D +1.8VS_APU All RLC follow CRB, need dobulc check with DG 200mA @ B +VCCRTC Vout Vin RC148 10K_0402_5% 1 AP2138N-1.5TRG1_SOT23-3 JCOMS1 @ SHORT PADS SA000063Q00 BCD: AP2138N-1.5TRG1 SA000063O00 ANPEC: APL510215AITRG CC114 1U_0402_6.3V6K A CC26 2 CC27 CC28 @ CC139 CC130 CC131 CC132 CC133 1U_0402_6.3V6K CC25 1U_0402_6.3V6K 1U_0402_6.3V6K CC24 1U_0402_6.3V6K 22U_0805_6.3V6M CC23 180P_0402_50V8-J 180P_0402_50V8-J +VSYSMEM_APU CC64 180P_0402_50V8-J CC63 10U_0603_6.3V6M CC62 10U_0603_6.3V6M CC61 10U_0603_6.3V6M CC60 1U_0402_6.3V6K CC59 1U_0402_6.3V6K CC58 1U_0402_6.3V6K CC57 1U_0402_6.3V6K CC65 1U_0402_6.3V6K CC56 1U_0402_6.3V6K CC120 1U_0402_6.3V6K 1U_0402_6.3V6K CC55 1U_0402_6.3V6K 180P_0402_50V8-J CC54 10U_0603_6.3V6M 10U_0603_6.3V6M CC53 10U_0603_6.3V6M 10U_0603_6.3V6M +APU_CORE_NB A +VSYSMEM +APU_CORE CC45 CC46 CC47 CC48 CC49 CC50 CC51 2 CC52 1U_0402_6.3V6K 1U_0402_6.3V6K CC44 1U_0402_6.3V6K 1U_0402_6.3V6K CC43 1U_0402_6.3V6K 1U_0402_6.3V6K CC42 1U_0402_6.3V6K 1U_0402_6.3V6K CC41 1U_0402_6.3V6K 1U_0402_6.3V6K CC40 1U_0402_6.3V6K 180P_0402_50V8-J CC39 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M CC38 1 2 CC145 22U_0805_6.3V6M @ CC146 22U_0805_6.3V6M @ Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (POWER & DECOUPLING) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet of 60 Beema (STRAPS & OTHERS) RC176 10K_0402_5% D RC181 10K_0402_5% @ RC154 10K_0402_5% @ +3VALW_APU +3VALW_APU RC153 10K_0402_5% @ RC152 10K_0402_5% @ +3VALW_APU 1 RC151 10K_0402_5% +3VALW_APU RC150 10K_0402_5% +3VALW_APU S0 PWR, PH +3VS??? Or need isloate~~ EC D +3VALW_APU 1 +3VALW_APU RC154,RC176,RC181 change to @ due to internal PH LPC_FRAME# GEVENT2# SYS_RESET# I BLINK RC155 2K_0402_5% @ I SPI ROM Internal CLK Gen Default Default LPC ROM Exteranl CLK Gen PULL HIGH C PULL LOW Boot Fail Timer Enabled 1.8V SPI Boot Fail Timer Disabled 3.3V SPI Default Default Normal Power Up Coin Battery &Reset Timing LDT_RST#/ LDT_PWRGD output to APU Default Default Default Reserved Direct DC Reserved RC156 2K_0402_5% @ RC157 2K_0402_5% RC158 2K_0402_5% RC159 2K_0402_5% @ RTCCLK RC177 2K_0402_5% @ RC180 2K_0402_5% @ I SYS_RESET_L II GEVENT2_L II LPCCLK0 II LPCCLK1 II LFRAME_L BLINK Type SUSCLK Signal CLK_PCI_EC STRAP PINS LPC_CLK1 C Type I straps become valid immediately after capture with the rising edge of RSMRST_L Type II straps become valid after PWR_GOOD is asserted All Strap pins must be configured with either external pull-up or pull-down resistors B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (STRAPS & OTHERS) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet of 60 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 10 of 60 Power Sequence Block need to be update! 2 SPOK V PU5 D D VGA_PWRGD A1 V A5 B7 PBTN_OUT# PM_SLP_S3# PM_SLP_S5# V V V 51_ON# EC B4 11 FCH_PWRGD PLT_RST# V APU_PWRGD 14 APU_RST# CPU C PU7 +VSYSMEM 8a +3VGS QV2 V V SYSON 12 V KBRST# V V 13 PXS_PWREN ON/OFF PQ1 15 B6 V V A4 FCH EC_ON C VGA_PWRGD V V VS EC_RSMRST# V PU401 B1 V B3 B7 +3VALW V PU401 V B+ B2 A5 V BATT +1.1VVALW B5 V PU301 BATT MODE A3 VV A2 V VIN V V AC MODE V VR_ON V V V U15 +1.1VS PU8 +1.2VS VDDCI PU11 +VGA_CORE PU13 B VGA V +0.95VGS PU12 8b V +1.8VGS PU6 V V V V PU7 +0.75VS V V V V PU10 +1.5VS V +1.5VGS U14 U13 +3VS VGATE B U12 +5VS V 10 V SUSP#,SUSP VGA_PWRGD PU14 +CPU_CORE A A V PU14 +APU_CORE_NB Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Power sequence Block THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 47 of 60 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date Virtual symbol 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 48 of 60 pad_sht7p0x6p65b10p66x9p9d2p8 Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 H7 HOLEA H8 HOLEA H9 HOLEA H10 HOLEA 1 H11 HOLEA H12 HOLEA PAD_SHAPET8P8X8P0B9P0D2P8 PAD_SHAPET8P0X8P75B9P0D2P8 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 H6 HOLEA H5 HOLEA 1 1 H2 HOLEA H4 HOLEA H3 HOLEA D pad_c2p3d2p3n H1 HOLEA pad_o2p3x2p8d2p3x2p8n pad_o2p3x2p8d2p3x2p8n 1 pad_c2p3d2p3n NH5 HOLEA D NH4 HOLEA NH3 HOLEA NH1 HOLEA pad_ct6p0d4p3 Pad_ct6p0b8p0d4p6 PAD_SHAPET5P0X6P0B7P0D2P3 H23 HOLEA H24 HOLEA H21 HOLEA H22 HOLEA H20 HOLEA H17 HOLEA H16 HOLEA 1 H15 HOLEA H14 HOLEA H13 HOLEA C C CHASSIS1_GND pad_ct6p0shapeb8p0x6p75d2p3 pad_cb8p0d7p0 PAD_CT6P0shapeb10p04x10p0d2p8 pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 FD6 GP9 PAD_RT2P21X2P99 @ +3VS GP12 PAD_RT2P45X2P5 @ B 1 GP8 PAD_RT2P65X2P2 @ GP7 PAD_RT2P65X2P2 @ 1 1 GP11 PAD_RT2P45X2P5 @ FFC CONN GROUND PAD 1 C168 1U_0402_10V6-K @ GP6 PAD_RT2P65X2P2 @ 1 GP5 PAD_RT2P65X2P2 @ 1 GP4 PAD_RT2P65X2P2 @ 1 For EMC GP10 PAD_RT2P21X2P99 @ +VGA_CORE GP3 PAD_RT2P65X2P2 @ 1 PAD_SHAPET5P0X6P0-U GP2 PAD_RT2P65X2P2 @ 1 1 1 PAD_SHAPET5P0X6P0-D GP1 PAD_RT2P65X2P2 @ FD5 FD4 FD3 B FD2 H18 HOLEA FD1 H19 HOLEA PCB Fedical Mark PAD PAD_CT5P5B8P0D2P5 C169 1U_0402_10V6-K @ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date Hole 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 49 of 60 EN Silergy SY8208CQNC Converter FOR SYSTEM EN Silergy SY8206BQNC Converter FOR SYSTEM B+ D Adaptor EC_ON EC_ON +5VLP/ 100mA D +5VALW/5A PGOOD ALW_PWRGD +3VLP/ 100mA Silergy SY8868ABC Converter +3VALW/4A PGOOD ALW_PWRGD +1.8VALW/2.3A FOR APU VDDIO EC_APU_ALWEN C TI BQ24737RGRR Battery Charger Switch Mode SYSON S5 SUSP# S3 C +0.675VS/1.3A FOR DDR Intersil ISL62771HRTZ Switch Mode FOR APU/NB Core EC_VR_ON EN PGOOD PGOOD_NB Silergy SYX198DQNC Converter Battery Li-ion 4S1P/41WH EC_APU_ALWEN ANPEC APL5930KAI-TRG LDO +1.5VSP/150mA FOR APU VDDIO SUSP# EN PGOOD APU Core/20A/25A APU Core NB/13A/17A VR_APU_PWRGD +0.95VS/7.68A FOR APU VDD EN PGOOD +1.35V/11A PGOOD SMBus B Richtek RT8231AGQW Switch Mode EN PGOOD Interisl ISL62771HRTZ Switch Mode B APUALW_PWRGD +VGA_CORE/20A VIDs PXS_PWREN EN FOR GPU VDDC PGOOD VR_VGA_PWRGD A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Power Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 50 of 60 RTC_VCC 1 JRTC1 PC429 1000P_0402_50V7K @ PL102 HCB2012KF-121T50_0805 PC428 470P_0402_50V7K ACES_50299-00501-003 ME@ PC427 470P_0402_50V7K ADAPTER_ID ADAPTER_ID PL101 HCB2012KF-121T50_0805 APDIN1 PF1 7A_24VDC_429007.WRML APDIN 2 PC426 1000P_0402_50V7K D +3VL +VCCRTC VIN JDCIN1 PD1 RB751V-40_SOD323-2 + D PR417 1 2 BAT_D PD2 1K_0603_5% @ FDK_ML1220-TT28 @ RB751V-40_SOD323-2 PR4448 0_0402_5% RTC Battery @ +3VALW C PH1 under CPU botten side : CPU thermal protection at 92+-3 degree C Recovery at 56 +-3 degree C VIN C PR419 750_0603_1% PR420 1M_0402_5% PR423 40.2K_0402_1% 2 PD6 AZ5425-01F_DFN1006P2E2 PU403 @ MAINPWON PR426 0_0402_5% 2 OTP_N_003 VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 OTP_N_002 PR425 499K_0402_1% ADAPTER_ID_ON# PQ28B 2N7002KDWH_SOT363-6 B PH1 100K_0402_1%_NCP15WF104F03RC @ 5 G S 2 PR422 13.7K_0402_1% @ D PR424 1M_0402_5% PC432 0.1U_0402_25V6 1 ADAPTER_ID B PR29 47K_0402_1% @ @ PQ28A 2N7002KDWH_SOT363-6 +3VL 1 S +3VALW PC430 0.1U_0402_25V6-K ADAPTER_ID_ON#_G G PR421 @ 0_0402_5% 2 +5VLP D G718TM1U_SOT23-8 @ NTC_V A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/15 2013/08/15 Deciphered Date DCIN / RTC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 51 of 60 EC_SMB_CK1 EC_SMB_DA1 PL404 HCB2012KF-121T50_0805 PC434 0.01U_0402_25V7K D SUYIN_200082GR007G232ZR ME@ +3VALW PD7 @ AZC199-02S.R7G_SOT23-3 For 15 For 14 BATT_TEMP_IN BATT_TEMP PD8 @ AZ5215-01F_DFN1006P2E2 SUYIN_200082GR007G232ZR ME@ PC433 1000P_0402_50V7K PR429 100K_0402_1% EC_SMCA EC_SMDA BATT_TEMP_IN 2 100_0402_1% 100_0402_1% 1 PR427 PR428 EC_SMCA EC_SMDA GND1 GND2 BATT+ D JBATT2 PL403 HCB2012KF-121T50_0805 2 GND1 GND2 VMB2 VMB PF2 8A_24V_F1206HI8000V024T JBATT1 VMB2 PR430 10K_0402_5% C C PR1 10M_0402_5% DC_UVP_2 PU404A AS393MTR-G1_SO8 PR440 PJ409 JUMP_43X39 2 +VSB S B +3VL +3VALW PR4449 100K_0402_1% D PR443 10K_0402_1% BATT_LEN# S 2N7002KW_SOT323-3 G PQ3B 2N7002KDWH_SOT363-6 100K_0402_1% +VSBP 1 PC439 1U_0402_6.3V6K @ PR441 1K_0402_1% PCH_PWR_EN BATT_OUT G D O1 -_1 PR442 100K_0402_1% PQ4 VSBP_1 ALW_PWRGD PR439 @ 0_0402_5% B PR438 49.9K_0402_1% @ TP0610K-T1-E3_SOT23-3 0.1U_0402_25V6 PC438 22K_0402_1% +_1 P PQ2 G PR436 10K_0402_1% PR434 280K_0402_1% PC437 0.1U_0603_25V7-M +3VALW 1 VSBP_3 PC435 0.01U_0402_25V7K +VSBP 0.22U_0603_25V7K PC436 PR435 100K_0402_1% PR437 VSBP_2 1 VMB2 B+ +3VALW 100K_0402_1% PR433 +5VALW PR432 100K_0402_1% PR431 @ 0_0603_5% D G S PQ3A 2N7002KDWH_SOT363-6 A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/15 2013/08/15 Deciphered Date BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 52 of 60 B+ Charge Option() bit[8]=1 P3 Reserve for EMC request DISCHG_G PR56 47K_0402_1% DISCHG_G-1 P2-1 1 737_VCC PC33 0.1U_0402_25V6-K 737_SCL PR67 0_0402_5% @ @ EC_SMB_DA1 PR69 0_0402_5% PQ11 GND ACP ACDET AO4466L_SO8 BTST ACOK REGN 17 PR66 2.2_0603_5% BST_CHG PC36 0.047U_0603_25V7-K 16 PU4 SCL HIDRV 18 DH_CHG 19 LX_CHG 15 DL_CHG PL3 4.7UH_PCMB063T-4R7MS_5.5A_20% CHG BQ24737RGRR_VQFN20_3P5X3P5 737_SDA SDA PHASE BATT+ PC40 1500P_0402_50V7K 1 SRP SRN SRP_1 13 PR71 2.2_0805_5% AO4466L_SO8 2 PR76 6.8_0603_5% PR75 316K_0402_1% PC42 0.1U_0402_25V6-K 1 PC41 0.1U_0402_25V6-K 737_SRP B +3VL PR77 10_0603_5% 737_ILIM PR78 90.9K_0402_1% B PQ12 21 PR74 40.2K_0402_1% SRN_1 12 CMPIN ILIM BM# 11 PAD PR70 0.01_1206_1% 1 737_ILIM LODRV PR72 0_0402_5% BM# PQ27B 2N7002KDWH_SOT363-6 S @ 10 D G BATT_OUT BATT_TEMP IOUT PC37 100P_0402_50V8J ADP_I ADP_I PACIN PQ26A 2N7002KDWH_SOT363-6 CMPOUT ACPRN ACN VCC 737_ACDET G S C EC_SMB_CK1 PQ29A 2N7002KDWH_SOT363-6 D 14 PR64 390K_0603_1% PR65 59K_0402_1% PC35 0.1U_0402_25V6-K PACIN_P PR62 1M_0402_5% PC34 1U_0603_25V6M PD5 RB751V-40_SOD323-2 20 PQ29B 2N7002KDWH_SOT363-6 PD4 1SS355_SOD323-2 PC39 10U_0805_25V6K 1 D PACIN_N S S VIN S D D PC38 10U_0805_25V6K PR68 10K_0402_5% ACOFF-1 G ACOFF BQ24737_VDD G PACIN_G PC31 1U_0603_25V6M PR58 200K_0402_1% G PR63 47K_0402_1% PACIN C PQ30A 2N7002KDWH_SOT363-6 P2-2 G S PQ30B 2N7002KDWH_SOT363-6 S BATT_OUT PC32 0.1U_0402_25V6-K 2 PD3 1SS355_SOD323-2 D PR60 68K_0402_1% PQ26B 2N7002KDWH_SOT363-6 PR61 10_1206_5% G PC30 0.1U_0402_25V6-K P2 D PC29 0.1U_0402_25V6-K 1 PR59 20K_0402_1% P2_G1 PQ10 LTC015EUBFS8TL_UMT3F-3 PR57 10K_0402_1% VIN PC24 0.1U_0402_25V6-K D 2 PC44 10U_0805_25V6K @ PC45 10U_0805_25V6K @ 2ACOFF-1 737_ACN PC28 2200P_0402_50V7K 737_ACP PQ8 AO4407AL_SO8 PC27 4.7U_0805_25V6-K PC26 4.7U_0805_25V6-K 1P2_G2 PL905 HCB2012KF-121T50_0805 PC23 10U_0805_25V6K @ PR55 200K_0402_1% PC25 4.7U_0805_25V6-K 2 2 PQ9 LTA044EUBFS8TL_UMT3F-3 PR54 200K_0402_5% PC21 10U_0805_25V6K @ PC22 2200P_0402_50V7K 4 D PR53 0.01_1206_1% 2 PC20 0.1U_0402_25V6-K 2 1 PJ2 @ JUMP_43X118 2 PQ7 SI4483_SO8 P2 PQ6 AO4407AL_SO8 VIN 737_SRN +3VALW PR4447 10K_0402_5% PC43 0.1U_0402_25V6-K ACIN# BQ24737_VDD 1 G PQ906 2N7002KW_SOT323-3 D 10K_0402_1% PR83 10K_0402_1% PR84 47K_0402_1% PR4446 S PACIN D 2 G PQ27A 2N7002KDWH_SOT363-6 S ACPRN PR88 12K_0402_1% A A Modified for B+ voltage step ACPRN PR334 0_0402_5% @ ACIN# Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 53 of 60 B+ +3VALW @ PJ401 PC409 4.7U_0603_6.3V6K 2 PC410 680P_0402_50V7K @ PC411 0.01U_0402_25V7K +3VALW_P SY8206BQNC_QFN10_3X3 PR404 4.7_0603_5% PJ402 1 2 JUMP_43X79 PC441 2200P_0402_25V7-K +3VLP @ +3VALW_P D @ PC440 0.1U_0402_25V6 LDO +3VLX +3VALW PL401 2.2UH_PCMB063T-2R2MS_8A_20% PC407 22U_0805_6.3V6M OUT FB 10 PR444 PC403 2.2_0603_5% 0.1U_0603_25V7-M 2 PC406 22U_0805_6.3V6M EN1 +3VBS PC405 22U_0805_6.3V6M LX PC408 @ 0.1U_0402_25V6 RB751V-40_SOD323-2 @ GND PR405 1M_0402_5% MAINPWON BS 1 PD15 +3VALW_FB PG IN PC404 22U_0805_6.3V6M +3VALW_EN EN2 +3V_PWRGD 1 PR411 1M_0402_5% @ PR403 2.2K_0402_5% EC_ON TDC :4A OCP :8A PU401 D 1 PC402 0.1U_0402_25V6 2 JUMP_43X79 PC421 10U_0805_25V6K 1 PC401 10U_0805_25V6K +3VLP +3VL PJ403 @ JUMP_43X39 2 PR407 1K_0402_1% C C B+ @ +5VALW PJ405 PC413 10U_0805_25V6K +5VALW_P B PC425 6800P_0402_25V7-K PC424 680P_0402_50V7K @ PC443 2200P_0402_25V7-K SY8208CQNC_QFN10_3X3 PC442 0.1U_0402_25V6 1 PC420 22U_0805_6.3V6M +5VLP @ PR406 4.7_0603_5% PJ406 +5VALW_P PC419 22U_0805_6.3V6M LDO +5VALW PL402 3.3UH_PCMB063T-3R3MS_6.5A_20% PC418 22U_0805_6.3V6M FB +5VLX PC417 22U_0805_6.3V6M OUT 10 PR4445 PC415 2.2_0603_5% 0.1U_0603_25V7-M 2 LX EN +5VBS RB751V-40_SOD323-2 @ VCC BS 1 +5VFB PG GND +5V_PWRGD MAINPWON 1 MAINPWON 1U_0603_25V6M +5VALW_EN PR413 1M_0402_5% PD16 PC422 0.1U_0402_25V6 @ IN 2 PR412 2.2K_0402_5% EC_ON EC_ON PC416 2+5VVCC TDC :5A OCP :11A PU402 +5V_VIN PC423 4.7U_0603_6.3V6K 2 PC412 10U_0805_25V6K 2 1 PC414 0.1U_0402_25V6 JUMP_43X79 @ 1 JUMP_43X118 B PR416 1K_0402_1% +3VALW +3V_PWRGD PR408 100K_0402_5% PR409 0_0402_5% ALW_PWRGD @ +5V_PWRGD PR410 0_0402_5% @ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date PWR_3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 54 of 60 A B C D TDC :11A OCP :14A 18 PC508 0.1U_0402_10V6-K 21 1 PAD VTTGND PC507 10U_0603_6.3V6M +0.675VSP 20 BOOT +0.675VSP VTT +1.35VP 19 13 11 CS PR507 2.2_0603_5% 1 0.22U_0603_25V7K 17 VTTREF 15 DL_1.35V LGATE PGOOD 10 S3 S5 S3_1.35V B+_1.35V FB_1.35V S5_1.35V PR995 10K_0402_1% @ PC512 680P_0402_50V7K PR504 887K_0402_1% TON_1.35V FB VDDQ TON VDD @ +0.675VSP 12 VTTREF_0.675V VTTREF_0.675V PR510 5.1_0603_5% +5VALW PQ502 AON6414AL_DFN GND RT8231AGQW PHASE PR994 7.68K_0402_1% PC511 0.033U_0402_16V7K PR503 100K_0402_1% 2 16 LX_1.35V PR508 @ 4.7_0603_5% VTTSNS PU501 2 PC516 470P_0402_50V7K + PC509 330U_2.5V_M PC515 0.1U_0402_25V6 PC514 2200P_0402_25V7-K 1 UGATE DH_1.35V PL501 0.68UH_PCMB063T-R68MS_16A_+-20% +1.35VP PC506 +0.675VSP TDC :1.3A PR506 237K_0402_1% VLDOIN PQ501 AON6414AL_DFN PGND +1.35V 14 +3VALW PR511 @ 100K_0402_1% PR512 100K_0402_1% VID PC513 10U_0805_25V6-K PC505 10U_0805_25V6-K 2 @ JUMP_43X79 PC504 2200P_0402_25V7-K B+_1.35V PC503 0.1U_0402_25V6 1 PJ501 PC501 10U_0603_6.3V6M +1.35VP B+ PC510 1U_0402_10VA-K +3VALW VDDQ_PGOOD PJ502 2 1 @ JUMP_43X118 PR501 0_0402_5% SUSP# PJ504 +1.35VP @ 1 +1.35V @ JUMP_43X118 3 S3_1.35V PJ503 SYSON 1 +0.675VS @ JUMP_43X39 PC502 0.1U_0402_10V6-K PR505 0_0402_5% S5_1.35V +0.675VSP PR513 @ 0_0402_5% @ PC517 0.1U_0402_10V6-K 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 1.35VS/+0.675VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet 55 of 60 A B C D +3VALW PR601 10K_0402_5% OUT PR602 4.7_0603_5% @ 10 GND FB PC606 680P_0402_50V7K @ SS PC607 1U_0402_10V6-K @ PJ602 2 1 +1.8VALW JUMP_43X79 PC629 0.1U_0402_25V6 EN PR605 1M_0402_5% PR604 0_0402_5% 2 EC_APU_ALWEN EN_1.8VSP ALW_PWRGD LX3 +1.8VSP PC604 22U_0805_6.3V6M PR623 0_0402_5% @ 1_8VS_LX PC628 22U_0805_6.3V6M 1 LX2 LX1 PC631 22U_0805_6.3V6M VIN PU601 TDC :2.3A OCP :3.8A PL601 1UH_PH041H-1R0MS_3.8A_20% 2 JUMP_43X79 @ +1.8VALW 1_8VS_PVIN PG PC602 22U_0805_6.3V6M PC601 22U_0805_6.3V6M 2 PC630 0.1U_0402_10V6-K 2 1_8VS_PG PJ601 +3VALW SY8868QMC_QFN10_2X2 PC663 1U_0402_10V6-K @ PR625 200K_0402_1% 1_8VS_FB PR655 100K_0402_1% 2 PC603 22P_0402_50V8-J +5VALW +1.5VS TDC :150mA EC_APU_ALWEN ALW_PWRGD EC_APU_ALWEN PR622 0_0402_5% @ PR612 0_0402_5% +1.5VS FB PR608 21.5K_0402_1% 5332_FB PC610 10U_0603_6.3V6M PR610 24K_0402_1% +3VS 0.95VS_EN ALW_PWRGD 1 PC611 0.1U_0402_10V6-K @ PR611 100K_0402_5% @ PR609 0_0402_5% 2EN_1_5VSP SUSP# EN POK PC609 4.7U_0603_6.3V6K JUMP_43X39 +1.5VSP VOUT1 VOUT2 JUMP_43X79 VCNTL VIN TP 5332_VIN PJ603 @ @ 1 1 PJ606 +3VALW PU602 APL5930KAI-TRG_SO8 GND PC608 1U_0402_6.3V6K 2 @ PC612 1U_0402_10V6-K @ +0.95VALW PU603 SYX198DQNC B+ TDC :7.68A OCP :12A PJ604 PC624 4.7U_0603_6.3V6K PR618 20K_0402_1% PC623 2200P_0402_25V7-K PC622 0.1U_0402_25V6 1 PC627 330P_0402_50V8J PC626 680P_0402_50V7K @ PC621 22U_0805_6.3V6M PC625 4.7U_0603_6.3V6K +3VALW 0.95VS_LDO 2 +0.95VALWP PR617 1K_0402_1% APUALW_PWRGD +0.95VALW PJ605 2 1 JUMP_43X118 PC620 22U_0805_6.3V6M LDO PC618 22U_0805_6.3V6M PG +0.95VALWP PR615 4.7_0603_5% @ PR616 1M_0402_5% @ 0.95VS_LX PC617 22U_0805_6.3V6M BYP 20.95VS_ILNT PR614 @ 100K_0402_5% 10 LX FB ILMT GND PL602 0.68UH_PCMB063T-R68MS_16A_+-20% PR624 PC613 0_0603_5% 0.1U_0603_25V7-M 2 0.95VS_BS1 BS EN PC615 10U_0805_25V6K PC614 10U_0805_25V6K IN +3VALW 2 JUMP_43X79 @ B+_0.95VS 1 1 PC616 0.1U_0402_25V6 PR620 10K_0402_5% @ 1 0.95VS_FB +3VALW PR621 34K_0402_1% 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 +1.35VS_VGA/+1.5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet 56 of 60 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 57 of 60 +VGA_B+ PX@ PL804 HCB2012KF-121T50_0805 PC816 0.1U_0402_25V6 PR837 @ 32.4K_0402_1% @ PX@ PC1185 22U_0805_6.3V6M PC1184 22U_0805_6.3V6M 2 @ +VGA_CORE PR842 PX@ PC825 30K_0402_1% 150P_0402_50V8-JPX@ 2VGA_FB_1 1 2 PX@ B PX@ PC1255 330P_0402_50V8J PX@ PC815 330U_D2_2V_Y 2 PX@ VSUM- PX@ PR844 PX@ PC827 PX@ 2K_0402_1% 680P_0402_50V7K 1VGA_FB_3 PR293 10_0402_1% PX@ PC1182 22U_0805_6.3V6M PC824 0.22U_0402_10V6K @ PR841 PX@ 619_0402_1% PC822 PX@ 100P_0402_50V8J PR831 PX@ 3.65K_0402_1% PC1183 22U_0805_6.3V6M PC806 330U_D2_2V_Y ISEN2 PC826 0.033U_0402_16V7K 2 PC828 0.033U_0402_16V7K VSUM+ PX@ PR840 10K_0402_5% 1 @ PC821 PX@ PR836 PX@ 100P_0402_50V8J 499_0402_1% VGA_FB_2 PC823 PX@ 330P_0402_50V8J 1 2 PH802 10K_0402_NTC PX@ PR843 11K_0402_1% PX@ 2 PR838 2.61K_0402_1% PX@ 1 PR835 PX@ 1.02K_0402_1% VSUM- PR830 PX@ 10K_0402_1% PC817 680P_0402_50V7K @ ISEN1 PC819 0.22U_0402_10V6K PX@ PC812 10U_0805_25V6K + PR828 10_0402_1% PR827 4.7_0603_5% @ VGA_LGATE2 PC810 10U_0805_25V6K 1 PC814 PX@ 0.22U_0603_25V7K PX@ 2BOOT2_R 1 PX@ PR826 VGA_BOOT2 PX@ PL802 0.36UH_PCMB063T-R36MS_20A_20% PX@ VGA_PHASE2 ISEN2 PC818 0.22U_0402_10V6K PX@ PC805 330U_D2_2V_Y PX@ B PX@ VSUM+ VR_VGA_PWRGD 2.2_0603_5% VSUM- PC803 10U_0805_25V6K VGA_UGATE2 +3VGS PR829 @ 10K_0402_5% PR834 10K_0402_5% @ PX@ C PC813 PX@ 0.1U_0402_25V6-K PC820 PX@ 0.1U_0402_25V6 PR810 PX@ 10_0402_1% + +VGA_B+ PQ804 AON6554_DFN PX@ PC802 10U_0805_25V6K PC801 0.1U_0402_25V6 PR824 100K_0402_1% PX@ PC809 1U_0603_25V6M PX@ PQ803 AON6414AL_DFN PX@ TP VGA_COMP VGA_FB VGA_ISUMN PC808 1U_0603_25V6M PX@ VGA_NTC +5VS +5VS 2 PR825 10.7K_0402_1% PX@ PR823 130K_0402_1% PX@ 2 PH801 470K_0402_3%_NCP15WM474E03RC PX@ PR804 PX@ 3.65K_0402_1% @ 1 VGA_NTC_1 VGA_BOOT1 PR806 10K_0402_1% PX@ VSUM+ 21 VGA_UGATE1 PC807 680P_0402_50V7K @ 22 + ISEN1 VGA_PHASE1 +VGA_CORE 23 VGA_LGATE1 PR814 0_0402_5% TDC :20A OCP :35A PX@ PR809 4.7_0603_5% @ 24 PR816 1_0603_5% PX@ VGA_NTC PQ802 AON6554_DFN PX@ VGA_VDD +3VGS PR821 PX@ 27.4K_0402_1% 2 VGA_VDDP 25 +VGA_CORE PL801 0.36UH_PCMB063T-R36MS_20A_20% PX@ VGA_LGATE2 26 D 27 VGA_PHASE2 VGA_UGATE2 41 COMP PGOOD 20 19 18 PR822 1.91K_0402_1% PX@ FB BOOT1 VGA_BOOT2 28 PX@ PC811 0.1U_0402_25V6 UGATE1 IMON PQ801 AON6414AL_DFN PX@ PWROK 30 29 2 32 PR802 PX@ 10K_0402_5% BOOT_NB 33 PHASE_NB UGATE_NB 31 PR801 PX@ 10K_0402_5% 35 34 LGATE_NB COMP_NB PGOOD_NB PR848 10K_0402_5% 38 37 36 39 PHASE1 RTN @ ENABLE PC831 1U_0402_10V6-K PX@ LGATE1 NTC PR820 0_0402_5% @ ISL62771HRTZ_TQFN40_5X5 VSEN 10 SUSP# VDD SVT ISUMN VDDIO 17 VGA_PWROK VDDP 16 VGA_ENABLE PR819 0_0402_5% LGATE2 SVD ISUMP VR_HOT_L 15 +VDDIO_GPU +3VGS PR803 PX@ 2.2_0603_5% BOOT1_R PC804 PX@ 0.22U_0603_25V7K VGA_LGATE1 BOOT2 PX@ VGA_PHASE1 VGA_BOOT1 PHASE2 11 PXS_PWREN VGA_VRHOT_L PR849 0_0402_5% PX@ SVC PR818 20K_0402_1% PX@ 20_0402_5% @ GPU_SVD C PR812 10K_0402_1% PX@ VGA_UGATE1 UGATE2 14 PR811 GPU_VR_HOT# IMON_NB ISEN1 GPU_SVC NTC_NB ISEN2 13 12 PX@ 100K_0402_1% PR807 PX@ 100K_0402_1% VSEN_NB PR805 ISUMN_NB PU801 ISUMP_NB 40 @ FB_NB PR847 0_0402_5% @ B+ PX@ PL805 HCB2012KF-121T50_0805 D PX@ PR294 10_0402_1% PX@ PC830 1000P_0402_50V7K PX@ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 58 of 60 PC906 + + +APU_CORE_NB D +APU_CORE_NB 2 + PR914 10_0402_1% + @ PC1013 22U_0805_6.3V6M VSUMN_NB + PC916 680P_0402_50V7K @ PC1012 22U_0805_6.3V6M VSUMP_NB PC1011 22U_0805_6.3V6M 1 LGATE_NB PR915 422_0402_1% 2VSUMN_NB_11 PC1017 330U_D2_2V_Y PC913 0.22U_0603_25V7K LGATE_NB PR911 3.65K_0402_1% PR910 4.7_0603_5% @ COMP_NB PQ902 AON6554_DFN PGOOD_NB VSUMN_NB FB_NB PC915 0.1U_0402_25V6 @ PR909 2.2_0603_5% BOOT_NB_R1 PR912 11K_0402_1% VSEN_NB PC914 0.01U_0402_25V7K 2 PH901 10K_0402_NTC 2NB_NTCS PR908 2.61K_0402_1% BOOT_NB TDC :13A OCP :22A PL904 0.36UH 20% PCMB063T-R36MS 20A PHASE_NB VSUMP_NB B+ PL807 HCB2012KF-121T50_0805 68U_25V_M 68U_25V_M PC910 UGATE_NB 0.01U_0402_25V7K PC905 PC908 47P_0402_50V8J PQ901 AON6414AL_DFN PL806 HCB2012KF-121T50_0805 2200P_0402_50V7K PC909 2FB_NB_1 PR907 PC907 499_0402_1% @ PC911 100P_0402_50V8J 330P_0402_50V8J PR904 @ 32.4K_0402_1% PR903 82K_0402_1% PR902 1.58K_0402_1% 10U_0805_25V6K PC904 PR906 0_0402_5% CPU_B+ PC902 150P_0402_50V8-J 2FB_NB_2 1 2 +APU_CORE_NB D 2 APU_VDDNB_SEN_H PR901 2K_0402_1% 10U_0805_25V6K PC903 1FB_NB_3 2 PC901 680P_0402_50V7K PR905 100_0402_1% PC1016 330U_D2_2V_Y PC1015 330U_D2_2V_Y PHASE_NB UGATE_NB 2 VSUM+_APU PR936 3.65K_0402_1% PC935 680P_0402_50V7K VSUM-_APU @ ISEN1_APU PC931 47P_0402_50V8J 1 + + PC1026 22U_0805_6.3V6M PC1025 22U_0805_6.3V6M PC1020 22U_0805_6.3V6M PC1019 22U_0805_6.3V6M PC1021 22U_0805_6.3V6M B PR944 @ 32.4K_0402_1% 2APU_FB_1 PR949 PC934 267K_0402_1% 150P_0402_50V8-J PC1027 22U_0805_6.3V6M PC1024 22U_0805_6.3V6M PC1023 22U_0805_6.3V6M PC1022 22U_0805_6.3V6M 62771_SVC_A PC1010 22U_0805_6.3V6M PR269 @ 1K_0402_1% PC1009 22U_0805_6.3V6M APU_VDD_SEN_L 2 @ 62771_SVD_A 62771_SVT_A 1 A PR272 @ 220_0402_5% PR271 220_0402_5% @ PR273 220_0402_5% @ 2 PR955 10_0402_1% APU_VDD_SEN_H PC939 0.1U_0402_25V6 A PR953 0_0402_5% PC940 PR954 330P_0402_50V8J 0_0402_5% @ PR268 PC1008 22U_0805_6.3V6M PR267 @ 1K_0402_1% PC1007 22U_0805_6.3V6M PC936 680P_0402_50V7K +APU_CORE PR951 2K_0402_1% PR952 10_0402_1% +1.35V 2 1APU_FB_3 1 2 PR948 2.37K_0402_1% @ 1 APU_FB_2 PC930 PR942 100P_0402_50V8J 499_0402_1% PR947 @ 10K_0402_5% 1 @ PC932 0.22U_0402_10V6K PC937 0.047U_0402_25V7K 1 1APU_R_B 1K_0402_1% VSUM+_APU PR950 11K_0402_1% PC938 0.1U_0402_25V6 1 PC933 330P_0402_50V8J PR943 499_0402_1% PR945 2.61K_0402_1% PH904 10K_0402_NTC + PC929 0.1U_0402_25V6 2 VSUM-_APU 1.1V 1.0V 0.9V 0.8V(Default) 1 1 PR939 10_0402_1% PR941 10K_0402_5% Boot Voltage 2APU_NTCS 0 1 +APU_CORE PC1003 22U_0805_6.3V6M LGATE1_APU PQ905 AON6554_DFN PC1002 22U_0805_6.3V6M 4 PC1001 22U_0805_6.3V6M 2 PC927 0.22U_0603_25V7K PR935 4.7_0603_5% @ PC1006 330U_D2_2V_Y PR934 2.2_0603_5% 2BOOT1_R_A BOOT1_APU PQ904 AON6554_DFN SVD PC1018 22U_0805_6.3V6M 2 0.01U_0402_25V7K PC925 PHASE1_APU PC1005 330U_D2_2V_Y VR_APU_PWRGD PC1004 330U_D2_2V_Y PR957 0_0402_5% @ LGATE1_APU SVC TDC :20A OCP :30A PL903 0.36UH_PCMC104T-R36MN1R105_30A_20% PR956 0_0402_5% @ 1 PGOOD_APU ISEN2_APU PRE-PWROK METAL VID CODES +APU_CORE UGATE1_APU PR931 1.91K_0402_1% PGOOD_NB B PC1014 22U_0805_6.3V6M 1 PQ903 AON6414AL_DFN 2 41 20 18 62771_FB_APU 19 17 +3VS PR933 10.7K_0402_1% 62771_RTN_APU PH903 470K_0402_3%_NCP15WM474E03RC 16 62771_VSEN_APU 62771NTC_APU CPU_B+ 2200P_0402_50V7K PC922 BOOT1_APU UGATE1_APU PR927 1_0603_5% 22 21 10U_0805_25V6K PC924 PHASE1_APU LGATE1_APU 23 C +5VS TP PGOOD COMP FB RTN VSEN ISUMN BOOT1 APU_VDD 24 +5VALW 10U_0805_25V6K PC923 UGATE1 IMON 25 PR923 @ 0_0402_5% PWROK PHASE1 PR920 0_0402_5% @ APU_VDDP PC921 1U_0603_25V6M LGATE1 ENABLE 28 27 26 32 VDD ISL62771HRTZ_TQFN40_5X5 SVT 29 VDDIO 30 PC920 1U_0603_25V6M BOOT_NB 31 33 PHASE_NB UGATE_NB 34 LGATE_NB PGOOD_NB 35 36 VDDP 11 APU_NTC_1 COMP_NB 39 38 37 FB_NB SVD PR991 27.4K_0402_1% PR940 0_0402_5% VSEN_NB 40 LGATE2 PC926 0.1U_0402_25V6 +5VS ISUMP_NB VR_HOT_L 15 PHASE2 62771_ISUMN_APU APU_PWROK UGATE2 SVC ISUMP 62771A_IMON BOOT2 IMON_NB ISEN1 APU_SVT EC_VR_ON NTC_NB 14 PR961 0_0402_5% VR_IMVP_IMON APU_SVD +1.8VS IMON_NB PR919 0_0402_5% 62771_SVC_A PR921 0_0402_5% @ 262771_VRHOT_A PR922 0_0402_5% @ 262771_SVD_A PR926 0_0402_5% @ 262771_VDDIO_A PR928 0_0402_5% @ 62771_SVT_A PR929 0_0402_5% @ 62771_EN_A PR930 0_0402_5% @ 262771_PWROK_A @ 62771A_IMON 10 PR932 133K_0402_1% VR_HOT# 62771NTC_NB APU_SVC ISUMN_NB PH902 470K_0402_3%_NCP15WM474E03RC ISEN2 1000P_0402_50V7K PC919 PR924 133K_0402_1% PR916 @ 10K_0402_5% PU901 C BOOT_NB PC917 @ 0.22U_0402_10V6K NTC 1 13 PR918 10.7K_0402_1% 62771NTC_NB_R 2NB_R_B 12 PC918 0.1U_0402_25V6 PR917 27.4K_0402_1% 2 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 PWR_CPU Core THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Sheet 59 of 60 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 PROCESSOR DECOUPLING THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Date: Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 60 of 60 www.s-manuals.com ... PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM- A281 A B C D E Sheet of 60 A B Voltage Rails ( O > Means ON C E , X > Means OFF ) Board ID... PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Thursday, February 20, 2014 Date: Rev 0.4 NM- A281 A B C D E Sheet of 60 Beema (MEM & PCIE I/F) D D UC1A OK MEMORY DDRA_MA[15 0] DDRA_MA0... SA000067P00 MEM_MA_EVENT# Layout: Place within 1000 SA000067Q00 mils of the APU socket A ZZZ A PCB NM- A281 DA60000U810 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15