A B C D E 1 KSWAA/KTWAA Liverpool 10M/10MG Sunderland 10M/10MG 2 LA-4982P REV 1.0 Schematic Intel Penryn/ Cantiga/ ICH9M 2009-07-27 Rev 1.0 3 4 Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet E of 45 A B C D E Compal Confidential Fan Control Model Name : KSWAA/KTWAA File Name : LA-4981P APL5607 uPGA-478 Package (Socket P) page page CRT page 17 VGA MXM/B ATI M92XT,64bit with 128M/256MB ATI M96,128bit with 256M/512MB EC SMBUS HDMI CEC Controller R5F211A4SP PCIE-Express 16X GM45/PM45/GL40 GM47/GM49 uFCBGA-1329 page 18 HDMI Conn Level Shifter page 20 page 20 Intel Cantiga page 20 H_D#(0 63) Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel 1.5V DDR3 800/1066 USB/B FP/B USB port 0,1 USB port page 25 PCIeMini Card WLAN C-Link USB Express Card Int Camera USB port USB port 11 1.5V 2.5GHz(250MB/s) SATA port Intel ICH9-M 5V 1.5GHz(150MB/s) page 25 1.5V 2.5GHz(250MB/s) SATA port 5V 1.5GHz(150MB/s) PCIe 1x page 28 5V 1.5GHz(150MB/s) page 32 page 21,22,23,24 Power/B page 26 page 25 eSATA USB page 25 USB port page 25 page 31 HD Audio 3.3V/1.5V 24.576MHz/48Mhz HDA Codec MDC 1.5 Conn Debug Port page 21 3V 33MHz ENE KB926 D2 page 34 page 26 page 33 AMP ALC272 TPA6017 page 29 page 30 DC/DC Interface CKT page 35 Touch Pad ODD/B for 17" page 25 5V 480MHz RTC CKT page 25 SATA ODD USB port PCI LPC BUS USB/B page 25 SATA port 5V 480MHz PCMCIA OZ601 SATA HDD0 BGA-676 USB RTS5159E 3IN1 USB port 10 1.5V 2.5GHz(250MB/s) 3.3V 33 MHz PCIe port page 18 PCIe 1x RTL8103EL 10/100M page 28 page 26 5V 480MHz PCIe 1x [2,4,5] 5V 480MHz Express Card BT conn USB USB USB port page 26 DMI x 5V 480MHz PCIe port page 27 RJ45 page 14,15 BANK 0, 1, 2, page 7,8,9,10,11,12,13 USB port page 27 PCIe port page 16 4,5,6 PCIeMini Card WiMax SLG8SP556VTR page 667/800/1066MHz LCD Conn Clock Generator EMC1402-1 FSB H_A#(3 35) page 19 Thermal Sensor Intel Penryn Processor page 26 Int.KBD SPI ROM page 34 Int MIC CONN page 30 page 33 Power Circuit DC/DC MIC CONN page 30 HP CONN page 30 SPK CONN page 30 page 36,37,38,39 40,41,42 FP/B for 17" page 25 Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet E of 45 A B C D Voltage Rails SIGNAL STATE Power Plane Description S1 S3 S5 G3 VIN Adapter power supply (19V) ON ON ON OFF B+ AC or battery power rail for power circuit ON ON ON ON E SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON HIGH HIGH HIGH HIGH S1(Power On Suspend) LOW HIGH HIGH HIGH S3 (Suspend to RAM) LOW LOW HIGH HIGH S4 (Suspend to Disk) LOW LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW LOW G3 LOW LOW LOW LOW +CPU_CORE Core voltage for CPU ON OFF OFF OFF +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF OFF +1.8VS 1.8V power rail for VRAM ON ON OFF OFF +3VALW 3.3V always on power rail ON ON ON OFF +3VL 3.3V always on power rail ON ON ON ON +3V_SB 3.3V power rail for LAN ON ON OFF OFF +3V_LAN 3.3V power rail for LAN ON ON OFF OFF +3VS 3.3V switched power rail ON OFF OFF OFF +3VS_HDP 3.3V power rail for G-sensor ON OFF OFF OFF +5VALW 5V always on power rail ON ON ON OFF +5VL 5V always on power rail ON ON ON ON +5V_SB 5V power rail for SB ON ON OFF OFF +5VS 5V switched power rail ON OFF OFF OFF +VSB VSB always on power rail ON ON ON OFF +RTCVCC RTC power ON ON ON ON BTO Option Table Function description DEVICE PCI DEVICE ID IDSEL# CARD BUS D4 AD20 REQ/GNT# A/B EC SM Bus1 address RJ11 Camera (B) (R) (X) MDC Camera Express Card PCMCIA Bluetooth BTO NEW@ PCM@ BT@ explain MDC@ 3D Sensor (S) 3D Sensor CAM@ GSENSOR@ HDMI (Y) description PIRQ Bluetooth (A) explain BTO Power Device (E) Function External PCI Devices Express Card/ PCMCIA Intel(UMA) IHDMI@ ATI VGA/B NIHDMI@ HDMI@ COMMON H@ EC SM Bus2 address Address +5VL EC KB926 D2 +5VL Smart Battery 0001 011X b +5VL HDMI-CEC 0011 010x b Power Device +3VS +3VS +3VS Address EC KB926 D2 CPU THM Sen SMSC SMC1402 VGA THM Sen ADM1032ARMZ VGA on die thermal sensor 1001 101Xb 1001 100Xb 1001 111Xb (No used) ICH9M SM Bus address Power Device Address +3V_SB ICH9M 1101 001Xb +3VS Clock Generator (SLG8SP556V) DDR DIMM0 +3VS DDR DIMM1 1001 010Xb +3VS Express Card +3VS 1001 000Xb Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet E of 45 H_A20M# H_FERR# H_IGNNE# 22 22 22 22 H_STPCLK# H_INTR H_NMI H_SMI# H_A20M# H_FERR# H_IGNNE# A6 A5 C4 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] Reserve for debug close to South Bridge D20 B3 LOCK# H4 RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 HIT# HITM# G6 E4 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 H_BR0# H_IERR# H_INIT# R1 56_0402_5% H_INIT# 22 +1.05VS H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# C2 if use XDP,these resistor are 51ohm +1.05VS XDP_TDO XDP_TMS XDP_TDI XDP_TCK XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# XDP_TRST# PAD T13 U1 H_THERMDA H_LOCK# H_RESET# C1 H_THERMDC 2200P_0402_50V7K CPU_THERM# R3 10K_0402_5% +3VS +1.05VS XDP_DBRESET# 23 THERMTRIP# H_PROCHOT# H_THERMDA H_THERMDC C7 54.9_0402_1% 54.9_0402_1% 54.9_0402_1% R6 R7 54.9_0402_1% 54.9_0402_1% DN THERM# ALERT# GND EC_SMB_CK2 17,33 D EC_SMB_DA2 17,33 R2 10K_0402_5% @ Reserve +3VS for source control R8 R9 @ 56_0402_5% 56_0402_5% FAN Control Circuit 1A 1SS355_SOD323-2 OCP# Q6 @ MMBT3904_SOT23 23 +FAN1 EN_DFAN1 10mil H CLK H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil JFAN +FAN1 U2 PROCHOT# PU: 68Ohm near CPU and MVP6 56Ohm near CPU if no used CLK_CPU_BCLK 16 CLK_CPU_BCLK# 16 D1 @ C3 10U_0805_10V4Z H_THERMTRIP# 8,22 A22 A21 SMCLK SMDATA EMC1402-1-ACZL-TR_MSOP8 +5VS 33 BCLK[0] BCLK[1] DP Address:0100_1100 EMC1402-1 Address:0100_1101 EMC1402-2 R14 R4 R5 H_PROCHOT# D21 A24 B25 VDD THERMAL PROCHOT# THERMDA THERMDC 1 IERR# INIT# F1 0.1U_0402_16V4Z CONTROL H_DEFER# H_DRDY# H_DBSY# C 22 22 22 H5 F21 E1 7 E H_ADSTB#1 A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# ICH REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# H_ADS# H_BNR# H_BPRI# B C BR0# ADDR GROUP_1 H_A#17 Y2 H_A#18 U5 H_A#19 R3 H_A#20 W6 H_A#21 U4 H_A#22 Y5 H_A#23 U1 H_A#24 R4 H_A#25 T5 H_A#26 T3 H_A#27 W2 H_A#28 W5 H_A#29 Y4 H_A#30 U2 H_A#31 V4 H_A#32 W3 H_A#33 AA4 H_A#34 AB2 H_A#35 AA3 V1 DEFER# DRDY# DBSY# H1 E2 G5 EN VIN VOUT VSET GND GND GND GND D2 @ C4 @ 1000P_0402_25V8J 1 3 GND GND C H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17 35] ADS# BNR# BPRI# K3 H2 K2 J3 L1 +3VS A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# XDP/ITP SIGNALS H_ADSTB#0 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP_0 D 7 7 7 @ JCPUA H_A#[3 16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 ACES_85204-0300N @ BAS16_SOT23-3 APL5607KI-TRG_SO8 C5 10U_0805_10V4Z R10 10K_0402_5% +3VS FAN_SPEED1 33 C6 0.01U_0402_16V7K @ RESERVED Penryn B H_FERR# C596 H_SMI# H_INIT# H_NMI H_A20M# H_INTR H_IGNNE# H_STPCLK# C597 C598 C599 C600 C601 C602 C603 @ 180P_0402_50V8J B @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J Reserve for debug close to CPU A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet of 45 @ JCPUD @ JCPUB D 7 7 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16 31] C +1.05VS Close 7 H_DSTBN#1 H_DSTBP#1 H_DINV#1 +CPU_GTLREF +CPU_GTLREF R11 1K_0402_1% to CPU pin AD26 within 500mils R17 2K_0402_1% 8,16 CPU_BSEL0 8,16 CPU_BSEL1 8,16 CPU_BSEL2 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] DATA GRP H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#[32 47] E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 MISC D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# DATA GRP H_D#[0 15] DATA GRP A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[48 63] Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal COMP[0,2] trace width is 18 mils COMP[1,3] trace width is mils H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_PWRGOOD H_CPUSLP# COMP0 R12 R13 COMP2 R15 COMP3 R18 COMP1 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% H_DPRSTP# 8,22,43 H_DPSLP# 22 H_DPWR# H_PWRGOOD 22 H_CPUSLP# H_PSI# 43 layout note: Please use "Daisy Chain" to layout and the signal (H_DPRSTP#) is routed from ICH9 to power IC, then to NB and CPU Penryn layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs B CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 H_CPUSLP# 166 1 200 266 0 C650 H_PWRGOOD C651 H_DPRSTP# C652 H_DPSLP# C653 Reserve for debug close to CPU @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J @ 180P_0402_50V8J VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] D C B Penryn A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet of 45 330U_X_2VM_R6M 1 D +CPU_CORE Near CPU CORE regulator ESR 1980uF + C7 @ 330U_X_2VM_R6M +CPU_CORE + C8 @ + C9 @ +CPU_CORE 330U_X_2VM_R6M 1 + C10 @ 330U_X_2VM_R6M Place these capacitors on L8 (North side,Secondary Layer) 2 C11 10U_0805_6.3V6M C12 10U_0805_6.3V6M C13 10U_0805_6.3V6M C14 10U_0805_6.3V6M C15 10U_0805_6.3V6M C16 10U_0805_6.3V6M C17 10U_0805_6.3V6M C18 10U_0805_6.3V6M D +CPU_CORE +CPU_CORE @ JCPUC C B A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] 330U_6.3V_M_R15 330U_6.3V_M_R15 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCCSENSE VCCSENSE 43 VSSSENSE AE7 VSSSENSE VSSSENSE 43 1 1 + + + + C79 C80 C81 Place these capacitors on L8 (North side,Secondary Layer) C19 10U_0805_6.3V6M C20 10U_0805_6.3V6M C21 10U_0805_6.3V6M C22 10U_0805_6.3V6M C23 10U_0805_6.3V6M C24 10U_0805_6.3V6M C25 10U_0805_6.3V6M C26 10U_0805_6.3V6M C82 2 need to change P/N +CPU_CORE 330U_6.3V_M_R15 330U_6.3V_M_R15 reserve for test please co-layout with C7~C10 Place these capacitors on L8 (Sorth side,Secondary Layer) C27 10U_0805_6.3V6M C28 10U_0805_6.3V6M C29 10U_0805_6.3V6M C30 10U_0805_6.3V6M C31 10U_0805_6.3V6M C32 10U_0805_6.3V6M C33 10U_0805_6.3V6M C34 10U_0805_6.3V6M +CPU_CORE Place these capacitors on L8 (Sorth side,Secondary Layer) C35 10U_0805_6.3V6M C36 10U_0805_6.3V6M C37 10U_0805_6.3V6M C38 10U_0805_6.3V6M C39 10U_0805_6.3V6M C40 10U_0805_6.3V6M C41 10U_0805_6.3V6M C42 10U_0805_6.3V6M C Mid Frequence Decoupling +1.05VS 4.5A 330U_6.3V_M_R15 1 + + C43 @ Place these inside socket cavity on L8 +1.05VS (North side Secondary) C146 330U_X_2VM_R6M reserve for test C44 0.1U_0402_10V6K C45 0.1U_0402_10V6K C46 0.1U_0402_10V6K C47 0.1U_0402_10V6K C48 0.1U_0402_10V6K C49 0.1U_0402_10V6K Near pin B26 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 43 43 43 43 43 43 43 +1.5VS 1 C50 0.01U_0402_16V7K 10U_0805_6.3V6M C51 B Penryn +CPU_CORE VCCSENSE 100_0402_1% R19 VSSSENSE 100_0402_1% R20 Close to CPU pin within 500mils A A Length match within 25 mils The trace width/space/other is 14/7/25 Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet of 45 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 C Layout Note: H_RCOMP / +H_VREF / H_SWNG trace width and spacing is 10/20 within 100 mils from NB B 1 +1.05VS R22 221_0402_1% R23 2K_0402_1% H_SWNG H_SWING H_RCOMP R24 24.9_0402_1% 2 C52 0.1U_0402_16V4Z @ H_SWING=0.3125*VCCP C5 E3 H_RCOMP +H_VREF H_SWNG H_RCOMP H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 R25 100_0402_1% C53 0.1U_0402_16V4Z H_RESET# H_CPUSLP# C12 E11 H_CPURST# H_CPUSLP# +H_VREF Near B3 pin A11 B11 H_AVREF H_DVREF H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK 16 CLK_MCH_BCLK# 16 H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 J8 L3 Y13 Y1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 L10 M7 AA5 AE6 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 5 5 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 5 5 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 4 4 H_RS#_0 H_RS#_1 H_RS#_2 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 4 2 R21 1K_0402_1% F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 H_A#[3 35] U3A H_D#[0 63] D +1.05VS HOST D C 5 5 B CANTIGA ES_FCBGA1329 GM45R3@ A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet of 45 AY21 Internal pull-up 01 00 10 11 Internal pull-up = Dynamic ODT Disabled = Dynamic ODT Enabled *(Default) CFG[13:12] = All Z Mode Enabled = Reserved = XOR Mode Enabled = Normal Operation*(Default) BG23 BF23 BH18 BF18 CFG19 Internal pull-down = Normal Operation = DMI Lane Reversal Enable CFG20 = Only PCIE or [SDVO/DP/HDMI] is operational Internal pull-down (PCIE/SDVO select) RSVD20 RSVD22 RSVD23 RSVD24 RSVD25 *(Default) * (Default) 5,16 CPU_BSEL0 5,16 CPU_BSEL1 5,16 CPU_BSEL2 R46 R47 1 2@ 2.21K_0402_1% 2@ 2.21K_0402_1% MCH_CFG_12 MCH_CFG_13 +3VS R48 2@ 2.21K_0402_1% MCH_CFG_16 1 T16 PAD MCH_CFG_19 4.02K_0402_1% MCH_CFG_20 2@ 4.02K_0402_1% R49 R50 B +3VS PM_EXTTS#_R 10K_0402_5% PM_SYNC# 14,15 PM_EXTTS# 0_0402_5% 5,22,43 H_DPRSTP# R53 R54 R55 R56 1 0_0402_5% PM_SYNC#_R PM_EXTTS#_R GMCH_PWROK 100_0402_5% MCH_RSTIN# NB_THERMTRIP# 0_0402_5% DPRSLPVR 0_0402_5% R29 B7 N33 P32 AT40 AT11 T20 R32 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 SMRCOMP SMRCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BF28 BH28 +SM_RCOMP_VOH +SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# AV42 AR36 BF17 BC36 +SM_VREF SM_PWROK SM_REXT DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# B38 A38 E41 F41 CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC# PEG_CLK PEG_CLK# F43 E43 CLK_MCH_3GPLL 16 CLK_MCH_3GPLL# 16 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AE41 AE37 AE47 AH39 DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 21 21 21 21 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AE40 AE38 AE48 AH40 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 21 21 21 21 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AE35 AE43 AE46 AH42 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 21 21 21 21 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AD35 AE44 AF46 AH43 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 21 21 21 21 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 B33 B32 G33 F33 E33 GFX_VR_EN C34 R29 R30 1 1 2 C56 0.01U_0402_16V7K 14 14 15 15 +1.5V 0_0402_5% 499_0402_1% SM_DRAMRST# 14,15 R31 1K_0402_1% @ C58 0.1U_0402_16V4Z @ CLK_DREF_96M 16 CLK_DREF_96M# 16 CLK_DREF_SSC 16 CLK_DREF_SSC# 16 2.2U_0603_6.3V6K C57 R28 1K_0402_1% +1.5V 80.6_0402_1% 80.6_0402_1% 20mil R32 R33 D SM_PWROK R101 0_0402_5% DDR3_SM_PWROK 42 R34 1K_0402_1% CLK_DREF_96M R575 CLK_DREF_96M# R576 CLK_DREF_SSC R577 CLK_DREF_SSC# R578 PM@ 0_0402_5% PM@ 0_0402_5% PM@ 0_0402_5% PM@ 0_0402_5% C Please place these resistors close to related balls +1.05VS +3VS R38 1K_0402_5% Lane reversal R41 54.9_0402_1% R42 1K_0402_5% MCH_TSATN# Q7 MMBT3904_SOT23-3 MCH_TSATN_EC# 33 Strap Pin Table SDVO_CTRLDATA (Internal pull-down) = SDVO interface disabled *(Default) = SDVO interface enabled DDPC_CTRLDATA (Internal pull-down) = Digital display (iHDMI/DP) interface disabled = Digital display (iHDMI/DP) interface enabled *(Default) B +1.05VS 17,21,27,28,33,34 PLT_RST# 4,22 H_THERMTRIP# 23,43 PM_DPRSLPVR R51 PM R52 23 BG22 BH21 80 Ohm C MCH_CFG_9 MCH_CFG_10 SM_RCOMP SM_RCOMP# 2.2U_0603_6.3V6K C55 R27 3.01K_0402_1% +SM_RCOMP_VOL For Cantiga E 1 2@ 2.21K_0402_1% 2@ 2.21K_0402_1% CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 14 14 15 15 B R44 R45 R39 R40 R43 T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 CFG 1 1 1K_0402_5% MCH_CLKSEL0 1K_0402_5% MCH_CLKSEL1 1K_0402_5% MCH_CLKSEL2 T14 PAD T15 PAD MCH_CFG_5 2@ 2.21K_0402_1% MCH_CFG_6 2@ 2.21K_0402_1% MCH_CFG_7 2@ 2.21K_0402_1% BD17 AY17 BF15 AY13 GRAPHICS VID C 2 SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1 DMI CLK = PCIE/[SDVO/DP/HDMI] are operating simu R35 R36 R37 DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1# = PCIe Loopback Enable = Disable*(Default) SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SM_DRAMRST# would be needed for DDR3 only Internal pull-up RSVD15 RSVD16 RSVD17 BA17 AY16 AV16 AR13 C54 0.01U_0402_16V7K 14 14 15 15 CFG10 B31 B2 M1 DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 = Lane Reversal Enable = Normal Operation *(Default) BC28 AY28 AY36 BB36 +SM_RCOMP_VOH Internal pull-up RSVD CFG9 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 14 14 15 15 = Intel Management Engine Crypto TLS cipher suite with confidentiality *(Default) DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1# Internal pull-up AR24 AR21 AU24 AV20 = Intel Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 R26 1K_0402_1% *(Default) 14 14 15 15 can support disble by SW = iTPM Host Interface is Disabled DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1 = iTPM Host Interface is enabled AP24 AT21 AV24 AU20 Internal pull-up = DMI x = DMI x *(Default) SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 CFG6 CFG16 +1.5V RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 COMPENSATION Internal pull-up M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 DDR CLK/ CONTROL/ CFG5 CFG7 U3B 011 = FSB667 010 = FSB800 000 = FSB1067 CFG[2:0] D Strap Pin Table R57 1K_0402_1% CL_CLK0 23 CL_DATA0 23 ICH_PWROK Width:Spacing 12mil:12mil CL_RST#0 23 +CL_VREF +CL_VREF=0.355V C59 0.1U_0402_16V4Z DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# N28 M28 G36 E36 K36 H36 SDVO_SCLK SDVO_SDATA TSATN# B12 MCH_TSATN# AH37 AH36 AN36 AJ35 AH34 SDVO_SCLK 20 SDVO_SDATA 20 CLKREQ_3GPLL# 16 MCH_ICH_SYNC# 23 CL_VREF should be 0.35 V R60 499_0402_1% +3VS SDVO_SCLK R61 GM@ SDVO_SDATA R62 IHDMI@ HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 AZ_SDIN2_MCH_R AZ_BITCLK_MCH 22 AZ_RST_MCH# 22 R63 AZ_SDOUT_MCH 22 AZ_SYNC_MCH 22 33_0402_5% IHDMI@ 2.2K_0402_5% GM@ R579 0_0402_5% PM@ R580 0_0402_5% 2009/07/22 Compal Electronics, Inc 2012/07/22 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A AZ_SDIN2_MCH 22 Compal Secret Data Classification Issued Date 2.2K_0402_5% the strap pin will impact no IHDMI SKU if mount R62 CANTIGA ES_FCBGA1329 GM45R3@ Security R61 PM@ 0_0402_5% R62 PM@ 0_0402_5% NC A CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF ME GMCH_PWROK @ 0_0402_5% 0_0402_5% MISC 23,33,43 VGATE 23,33 ICH_PWROK R58 R59 HDA Use VGATE for GMCH_PWROK SCHEMATIC MB A4982 Document Number Rev B 401791 Sheet Wednesday, December 30, 2009 of 45 D D 15 DDR_B_D[0 63] DDR_A_BS0 14 DDR_A_BS1 14 DDR_A_BS2 14 SA_RAS# SA_CAS# SA_WE# BB20 BD20 AY20 DDR_A_RAS# 14 DDR_A_CAS# 14 DDR_A_WE# 14 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SYSTEM MEMORY A DDR_A_DM[0 7] SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AJ43 DDR_A_DQS#0 AT43 DDR_A_DQS#1 BA44 DDR_A_DQS#2 BD37 DDR_A_DQS#3 AY12 DDR_A_DQS#4 BD8 DDR_A_DQS#5 AU9 DDR_A_DQS#6 AM8 DDR_A_DQS#7 DDR_A_DQS#[0 7] DDR_A_MA[0 14] SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 14 DDR_A_DQS[0 7] U3E DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 14 14 14 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 CANTIGA ES_FCBGA1329 GM45R3@ SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 B SA_BS_0 SA_BS_1 SA_BS_2 BD21 BG18 AT25 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 DDR_B_BS0 15 DDR_B_BS1 15 DDR_B_BS2 15 SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 DDR_B_RAS# 15 DDR_B_CAS# 15 DDR_B_WE# 15 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 MEMORY B SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 DDR C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SYSTEM U3D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 DDR 14 DDR_A_D[0 63] SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 DDR_B_DM[0 7] DDR_B_DQS[0 7] 15 C DDR_B_DQS#[0 7] AL46 DDR_B_DQS#0 AV47 DDR_B_DQS#1 BH41 DDR_B_DQS#2 BH37 DDR_B_DQS#3 BG9 DDR_B_DQS#4 BC2 DDR_B_DQS#5 AT2 DDR_B_DQS#6 AN5 DDR_B_DQS#7 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 15 DDR_B_MA[0 14] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 15 15 B CANTIGA ES_FCBGA1329 GM45R3@ A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet of 45 +3VS U3C within 500 mils D L_DDC_DATA LCTLA_CLK L32 10K_0402_5% G32 33 UMA_ENBKL LCTLB_DATA LCTLA_CLK GM@ M32 10K_0402_5% LCTLB_DATA M33 GM@ UMA_LCD_EDID_CLK UMA_LCD_EDID_CLK K33 18 UMA_LCD_EDID_CLK 2.2K_0402_5% UMA_LCD_EDID_DATAJ33 18 UMA_LCD_EDID_DATA GM@ UMA_LCD_EDID_DATA UMA_ENVDD M29 18 UMA_ENVDD 2.2K_0402_5% R69 GM@ LVDS_IBG C44 2.37K_0402_1% Spacing=20mil B43 R501 GM@ 0_0402_5% E37 R502 GM@ 0_0402_5% E38 GM@ = LFP Disable *(Default) = LFP Card Present; PCIE disable LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL C41 C40 B37 A37 LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK 18 UMA_LCD_TXOUT018 UMA_LCD_TXOUT118 UMA_LCD_TXOUT2- H47 E46 G40 A40 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 18 UMA_LCD_TXOUT0+ 18 UMA_LCD_TXOUT1+ 18 UMA_LCD_TXOUT2+ H48 D45 F40 B40 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 18 UMA_LCD_TZOUT018 UMA_LCD_TZOUT118 UMA_LCD_TZOUT2- A41 H38 G37 J37 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 18 UMA_LCD_TZOUT0+ 18 UMA_LCD_TZOUT1+ 18 UMA_LCD_TZOUT2+ B42 G38 F37 K37 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 18 18 18 18 UMA_LCD_TXCLKUMA_LCD_TXCLK+ UMA_LCD_TZCLKUMA_LCD_TZCLK+ LVDS R64 PM@ 0_0402_5% R66 PM@ 0_0402_5% R67 PM@ 0_0402_5% R68 PM@ 0_0402_5% L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN GRAPHICS R500PM@ 0_0402_5% R64 R66 R67 R68 C GM@ R70 GM@ R71 GM@ R72 TV_COMPS 75_0402_1% TV_LUMA 75_0402_1% TV_CRMA 75_0402_1% TV_COMPS TV_LUMA TV_CRMA F25 H25 K25 H24 C31 E32 R73 PM@ 0_0402_5% R74 PM@ 0_0402_5% R75 PM@ 0_0402_5% R73 GM@ R74 GM@ R75 GM@ UMA_CRT_B 150_0402_1% UMA_CRT_G 150_0402_1% UMA_CRT_R 150_0402_1% UMA_CRT_B 19 UMA_CRT_G 19 UMA_CRT_R B R78 PM@ 0_0402_5% R503 PM@ R504 PM@ UMA_CRT_CLK 4.7K_0402_5% UMA_CRT_DATA 4.7K_0402_5% E28 CRT_BLUE UMA_CRT_G G28 CRT_GREEN UMA_CRT_R UMA_CRT_HSYNC 0_0402_5% UMA_CRT_VSYNC 0_0402_5% 19 UMA_CRT_CLK 19 UMA_CRT_DATA 19 UMA_CRT_HSYNC R78 GM@ UMA_CRT_CLK UMA_CRT_DATA UMA_CRT_HSYNC 1UMA_CRT_IREF 1.02K_0402_1% J28 CRT_RED G29 CRT_IRTN H32 J32 J29 E29 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF UMA_CRT_VSYNC L29 19 UMA_CRT_VSYNC TV_DCONSEL_0 TV_DCONSEL_1 UMA_CRT_B +3VS R76 GM@ R77 GM@ TV_RTN PEG_COMP R65 49.9_0402_1% PEG_COMPI PEG_COMPO T37 T36 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 VGA 19 TVA_DAC TVB_DAC TVC_DAC TV R70 PM@ 0_0402_5% R71 PM@ 0_0402_5% R72 PM@ 0_0402_5% PCI-EXPRESS R499GM@ 0_0402_5% CRT_VSYNC +1.05VS 10mils D PCIE_GTX_C_MRX_N[0 15] PCIE_GTX_C_MRX_N[0 15] 17 PCIE_GTX_C_MRX_P[0 15] PCIE_GTX_C_MRX_P[0 15] 17 PCIE_MTX_C_GRX_N[0 15] PCIE_MTX_C_GRX_P[0 15] PCIE_MTX_C_GRX_N[0 15] 17 PCIE_MTX_C_GRX_P[0 15] 17 C C612 PM@ C614 PM@ C616 C618 C620 C622 C624 PM@ PM@ PM@ PM@ PM@ C626 PM@ C628 PM@ C630 PM@ C632 PM@ C634 PM@ C636 C638 PM@ PM@ C640 PM@ C642 PM@ C611 0.1U_0402_16V7K C613 0.1U_0402_16V7K C615 0.1U_0402_16V7K C617 0.1U_0402_16V7K C619 0.1U_0402_16V7K C621 0.1U_0402_16V7K C623 0.1U_0402_16V7K C625 0.1U_0402_16V7K PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ C627 0.1U_0402_16V7K C629 0.1U_0402_16V7K C631 0.1U_0402_16V7K C633 0.1U_0402_16V7K C635 0.1U_0402_16V7K C637 0.1U_0402_16V7K C639 0.1U_0402_16V7K C641 0.1U_0402_16V7K PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 B CANTIGA ES_FCBGA1329 GM45R3@ PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 C61 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 C65 PCIE_GTX_C_MRX_P3 C63 C67 C60 IHDMI@ 0.1U_0402_16V7K C62 IHDMI@ 0.1U_0402_16V7K IHDMI@ 0.1U_0402_16V7K C64 IHDMI@ 0.1U_0402_16V7K C66 IHDMI@ 0.1U_0402_16V7K IHDMI@ 0.1U_0402_16V7K IHDMI@ 0.1U_0402_16V7K IHDMI@ 0.1U_0402_16V7K R505 IHDMI@ 0_0402_5% PCIE_MTX_C_GRX_HDMI_N0 PCIE_MTX_C_GRX_HDMI_N1 PCIE_MTX_C_GRX_HDMI_N2 PCIE_MTX_C_GRX_HDMI_N3 20 20 20 20 PCIE_MTX_C_GRX_HDMI_P0 PCIE_MTX_C_GRX_HDMI_P1 PCIE_MTX_C_GRX_HDMI_P2 PCIE_MTX_C_GRX_HDMI_P3 20 20 20 20 PCIE_GTX_C_MRX_HDMI_P3 20 A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet 10 of 45 A B 21 PCI_AD[0 31] PCI_AD[0 31] 21 PCI_CBE#[0 3] PCI_CBE#[0 3] C D +3VS 0.1U_0402_16V4Z +5VS IDSEL SELECT POWER-ON-STRAPPING (SEE NOTE & TABLE FOR OPTIONS) 10U_0805_10V4Z CB1 PCM@ 0.1U_0402_16V4Z +3VS +3VS CB8 PCM@ 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS CB9 PCM@ CB10 PCM@ CB13 PCM@ 2 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_AD20 IDSEL PCM@ RB19 100_0402_5% PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 64 77 97 115 10 13 14 15 16 17 18 19 21 22 28 29 30 31 34 35 36 37 38 39 40 41 42 43 44 46 127 11 12 49 50 CORE_VCC CORE_VCC CORE_VCC CORE_VCC PCI_VCC PCI_VCC PCI_VCC AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VPP_VCC/VPPD1/IDSEL C/BE3# C/BE2# C/BE1# C/BE0# 16 CLK_PCI_PCM 21 PCI_DEVSEL# 21 PCI_FRAME# 21 PCI_IRDY# 21 PCI_TRDY# 21 PCI_STOP# 21 PCI_PAR 26 27 23 24 25 47 48 PCI_CLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR#/SPKR_OUT 29 PCM_SPK# 51 21 21 PCI_REQ#1 PCI_GNT#1 21 PCI_RST# 126 120 RB20 @ 23 PM_CLKRUN# 0_0402_5% CLK_PCI_PCM RST# PME#/RI_OUT# MF6 MF4 MF3 MF0 32 45 65 96 128 for EMI request RB21 10_0402_5% @ 55 54 53 52 REQ# GNT# GND GND GND GND GND 23,33,34 SERIRQ 21 PCI_PIRQA# CB3 PCM@ VCC5#/VCCD0#/SDATA VCC3#/VCCD1#/SCLK VPP_PGM/VPPD0/SLATCH 124 125 123 VCC5# VCC3# D10/CAD31 D9/CAD30 D1/CAD29 D8/CAD28 D0/CAD27 A0/CAD26 A1/CAD25 A2/CAD24 A3/CAD23 A4/CAD22 A5/CAD21 A6/CAD20 A25/CAD19 A7/CAD18 A24/CAD17 A17/CAD16 IOW#/CAD15 A9/CAD14 IORD#/CAD13 A11/CAD12 OE#/CAD11 CE2#/CAD10 A10/CAD9 D15/CAD8 D7/CAD7 D13/CAD6 D6/CAD5 D12/CAD4 D5/CAD3 D11/CAD2 D4/CAD1 D3/CAD0 103 102 101 100 99 110 109 108 106 105 104 118 95 94 93 75 73 74 71 72 70 69 68 85 84 82 83 80 81 78 79 76 S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3 A16/CCLK A23/CFRAME# A15/CIRDY# A22/CTRDY# A21/CDEVSEL# A20/CSTOP# A13/CPAR A14/CPERR# WAIT#/CSERR# INPACK#/CREQ# WE#/CGNT# RDY/IREQ#/CINT# A19/CBLOCK# WP/CCLKRUN# RESET/CRST# D2/RFU D14/RFU A18/RFU VS1/CVS1 VS2/CVS2 CD1#/CCD1# CD2#/CCD2# BVD2/LED/CAUDIO BVD1/STSCHG#/RI#/CSTSCHG 107 114 117 116 113 61 58 60 91 89 62 88 59 87 119 98 86 63 57 121 56 122 92 90 S1_A16_R S1_A23 S1_A15 S1_A22 S1_A21 S1_A20 S1_A13 S1_A14 S1_WAIT# S1_INPACK# S1_WE# S1_RDY# S1_A19 S1_WP S1_RST S1_D2 S1_D14 S1_A18 S1_VS1 S1_VS2 S1_CD1# S1_CD2# S1_BVD2 S1_BVD1 REG#CCBE3# A12/CCBE2# A8/CCBE1# CE1/CCBE0# 111 112 66 67 S1_REG# S1_A12 S1_A8 S1_CE1# CB4 PCM@ 2 +S1_VCC RB17 33K_0402_5% PCM@ VCC5# VCC3# 4.7U_0805_10V4Z UB2 40mil VCC/VPP +3.3V VCC/VPP +3.3V VCC5# +5V VCC3# GND PCMCIA Socket OZ2210GN-B1_SO8 PCM@ JPCM PVT RB22 33K_0402_5% PCM@ SA000026P10 (S IC OZ2210GN-B1 SO 8P) VCC5# (124) VCC5# (124) VPP_PGM IDSEL SELECT (123) VPP_PGM (125) IDSEL SELECT 0 AD18 * AD20 AD25 1 PIN F4 NOTE: IDSEL SELECTION! THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE PCI AD LINES OR EXTERNAL IDSEL SIGNAL RB18 33_0402_5% S1_A16 PCM@ 22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO SELECT ONE OF THE POSSIBLE IDSEL CONNECTIONS THE TABLE BELOW SHOWS THE POSSIBLE COMBINATIONS 35 36 37 38 39 40 41 42 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 S1_D3 S1_CD1# S1_D4 S1_D11 S1_D5 S1_D12 S1_D6 S1_D13 S1_D7 S1_D14 S1_CE1# S1_D15 S1_A10 S1_CE2# S1_OE# S1_VS1 S1_A11 S1_IORD# S1_A9 S1_IOWR# S1_A8 S1_A17 S1_A13 S1_A18 S1_A14 S1_A19 S1_WE# S1_A20 S1_RDY# S1_A21 +S1_VCC CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS FOR A FULL PARALLEL POWER MODE IF AN EXTERNALLY CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC +S1_VCC 0.1U_0402_16V4Z CB11 PCM@ CB12 PCM@ 4.7U_0805_10V4Z S1_A16 S1_A22 S1_A15 S1_A23 S1_A12 S1_A24 S1_A7 S1_A25 S1_A6 S1_VS2 S1_A5 S1_RST S1_A4 S1_WAIT# S1_A3 S1_INPACK# S1_A2 S1_REG# S1_A1 S1_BVD2 S1_A0 S1_BVD1 S1_D0 S1_D8 S1_D1 S1_D9 S1_D2 S1_D10 S1_WP S1_CD2# OZ601TN_TQFP128~D PCM@ 22K TO 47K PULL-UPS MUST BE PLACED ON INTA#, PME#, SERIRQ# & CLKRUN# GND GND DATA3 CD1# DATA4 DATA11 DATA5 DATA12 DATA6 DATA13 DATA7 DATA14 CE1# DATA15 ADD10 CE2# OE# VS1# ADD11 IORD# ADD9 IOWR# ADD8 ADD17 ADD13 ADD18 ADD14 ADD19 WE# ADD20 READY ADD21 VCC VCC VPP VPP ADD16 ADD22 ADD15 ADD23 ADD12 ADD24 ADD7 ADD25 ADD6 VS2# ADD5 RESET ADD4 WAIT# ADD3 INPACK# ADD2 REG# ADD1 BVD2 ADD0 BVD1 DATA0 DATA8 DATA1 DATA9 GND DATA2 GND DATA10 GND WP GND CD2# GND GND 69 70 71 72 SANTA_130675-4_68P @ this is temp footprint 4 RB16 33K_0402_5% @ UB1 20 33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1 1 CB7 PCM@ 2 CB6 PCM@ 1 CB5 PCM@ CB2 PCM@ CB14 10P_0402_50V8J @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Deciphered Date 2012/07/22 Title SCHEMATIC MB A4982 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev B 401791 Wednesday, December 30, 2009 D Sheet 31 of 45 +3VS_CR RC2 +3VS +3VALW D 0_0603_5% 3IN1@ RC4 0_0603_5% @ confirm that whether can be removed CC1 0.1U_0402_16V4Z 3IN1@ RC7 CC6 0.1U_0402_16V4Z 3IN1@ UC2 +3VS_CR CC4 RC8 100K_0402_5% 3IN1@ 0.1U_0402_16V4Z 3IN1@ 11 33 AV_PLL NC NC CARD_3V3 D3V3 D3V3 RST#_R MODE SEL XTLO XTLI 44 45 47 48 3V3_IN RST# MODE_SEL XTLO XTLI CR_LED# 14 DM DP GPIO0 +VCC_3IN1 VREG MS_D4 NC +3VS_CR RC10 0_0402_5% RST#_R 3IN1@ RST# CC5 1U_0402_6.3V4Z 3IN1@ CC8 1U_0402_6.3V4Z 3IN1@ +3VS_CR 21 21 USB20_N10 USB20_P10 +3VS MODE SEL RC13 120_0402_5% 3IN1@ 1 22 RC16 0_0402_5% 3IN1@ Vf=2.0V(typ),2.4V(max) DC1 HT-110UYG-CT_YEL/GRN 3IN1@ RREF 12 32 DGND DGND 46 AGND AGND XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI 43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18 XTAL_CTR MS_D5 13 24 EEDO EECS EESK SD_CMD 15 16 17 36 2 2 CR_LED# CC7 1U_0402_6.3V4Z 3IN1@ SD_DATA2 SD_DATA3 SD_MS_CLK MS_DATA3_SD_DATA6 MSCD# MS_DATA2_SD_DATA7 SD_MS_DATA0 MS_DATA1 MSBS SD_DATA1 SDCD# SDWP# RC11 3IN1@ 22_0402_5% SDCLK RC12 3IN1@ 22_0402_5% MSCLK C XTAL_CTR in Card Reader SDCMD RTS5159-GR_LQFP48_7X7 3IN1@ RC15 0_0402_5% 3IN1@ confirm all pin define with connector spec 1 RC14 6.19K_0402_1% 3IN1@ 10 22 30 C CC13 0.1U_0402_16V4Z @ D 0_0402_5% 3IN1@ JREAD SDWP# SD_DATA1 SD_MS_DATA0 B 10 11 12 13 14 15 16 17 18 19 20 21 MSBS SDCLK MS_DATA1 SD_MS_DATA0 +VCC_3IN1 48Mhz RC19 0_0402_5% 16 CLK_48M_CR CC10 1U_0402_6.3V4Z 3IN1@ XTLI MS_DATA2_SD_DATA7 1 2 CC11 0.1U_0402_16V4Z 3IN1@ 3IN1@ +3VS_CR SD_DATA3 XTAL_CTR RC20 0_0402_5% 3IN1@ 12Mhz USB AUTO DE-LINK MS FORMATTER R C NC YES NC 47P YES NC NC 6P_0402_50V8D NC 680P A YC1 12MHZ_16P_6X12000012 @ 10K 680P 6P_0402_50V8D TAITW_R009-125-LR_RV @ LED ON 10_0402_5% MSCLK @ RC17 LED ON SDCLK YES Compal Secret Data 2009/07/22 Issued Date 2012/07/22 Deciphered Date Title A 10P_0402_50V8J @ CC15 Compal Electronics, Inc SCHEMATIC MB A4982 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: 10P_0402_50V8J @ CC14 10_0402_5% @ RC18 22 23 Compatible with RTS5158E YES Security Classification B YES 10K 180P XTLO CC12 @ SD_DATA2 SDCD# Description Recommended XTLI CC9 @ MSCD# MS_DATA3_SD_DATA6 SDCMD MSCLK SD-WP SD-DAT1 SD-DAT0 SD-GND MS-GND MS-BS SD-CLK MS-DAT1 MS-DAT0 SD-VCC MS-DAT2 SD-GND MS-INS MS-DAT3 SD-CMD MS-SCLK MS-VCC SD-DAT3 MS-GND SD-DAT2 GND1 SD-CD GND2 Rev B 401791 Sheet Wednesday, December 30, 2009 32 of 45 +3VL +3VL 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z C773 2 0.1U_0402_16V4Z C769 C774 C775 1000P_0402_50V7K1000P_0402_50V7K U43 VCC VCC VCC VCC VCC VCC for EMI request 0.1U_0402_16V4Z 67 C772 CLK_PCI_EC AVCC 0.1U_0402_16V4Z C771 C770 22 33 96 111 125 D R738 @ 10_0402_5% 2 CLK_PCI_EC 12 13 ECRST# 37 20 38 16 CLK_PCI_EC 8,17,21,27,28,34 PLT_RST# R739 47K_0402_5% 2 C780 23 EC_SCI# 35 WL_BT_LED# ECRST# 0.1U_0402_16V4Z R595 R596 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 KSO2 C to avoid EC entry ENE test mode 26 KSI[0 7] 26 KSO[0 17] KSI[0 7] KSO[0 17] RP23 +3VL +3VS EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 38 38 4,17 4,17 2.2K_8P4R_5% R751 +3VL EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 14 15 16 17 18 19 25 28 29 30 31 32 34 36 SLP_S5# EC_SMI# CEC_INT# +3VALW C781 0.1U_0402_16V4Z @ 23 PM_SLP_S5# MCH_TSATN_EC# PM_SLP_S4#_R P FAN_SPEED1 B A U44 @ NC7SZ08P5X_NL_SC70-5 SLP_S5# G Y DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 83 84 85 86 87 88 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 97 98 99 109 SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 INVT_PWM 18 EC_BEEP# 29 ACOFF BATT_TEMPA GPIO SM Bus BATT_TEMPA 38 ADP_I ADP_V BATT_TEMPA C776 ACIN_D C779 39 39 27 E51_TXD 27 E51_RXD 26,35 ON/OFFBTN# 35 PWR_SUSP_LED# 26 NUM_LED# PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A GPI maybe can remove R750 PM_SLP_S4#_R 0_0402_5% XCLK1 XCLK0 R749 CRY1 2CRY2 AGND PM_SLP_S4# 122 123 SLP_S5# GND GND GND GND GND 0_0402_5% 11 24 35 94 113 R748 69 CRY1 CRY2 PM_SLP_S5# USB_CHG_EN# 25 USB_EN# 25 ENCODER_DIR 30 ENCODER_PULSE 30 TP_CLK 26 TP_DATA 26 TP_CLK TP_DATA VGATE +5VS TP_CLK 4.7K_0402_5% TP_DATA 4.7K_0402_5% R740 R741 +3VALW VGATE 8,23,43 WOL_EN# 36 SBPWR_EN# 24,36 LID_SW# 34 LID_SW# 47K_0402_5% ACIN_D FSTCHG 39 BATT_FULL_LED# 35 CAPS_LED# 26 BATT_CHG_LOW_LED# 35 PWR_ON_LED# 35 SYSON 27,42 VR_ON 43 100K_0402_5% R742 D64 ACIN_D PM_PWROK EC_RSMRST# 23 EC_LID_OUT# 23 EC_ON 35 EC_SWI# PM_PWROK BKOFF# 18 XMIT_OFF# 27 ACIN 23,35,37 B R745GM@ 0_0402_5% R746PM@ 0_0402_5% R747 100K_0402_5% ENBKL USB_OC#0_R USB_OC#3 21,25 EC_THERM# 23 SUSP# 17,27,29,36,39,41 PBTN_OUT# 23 ICH_PWROK R231 R264 PM_PWROK +3VS +EC_V18R C782 4.7U_0805_10V4Z KB926QFD3_LQFP128_14X14 C777 VGATE B PM_PWROK A Y VGA_ENBKL 17 R752@ 10K_0402_5% 10K_0402_5% 0.1U_0402_16V4Z ICH_PWROK 8,23 U5 NC7SZ08P5X_NL_SC70-5 0_0402_5% A To reduce CMOS dischage fail rate Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: UMA_ENBKL 10 ENBKL 32.768KHZ_12.5P_1TJS125BJ4A421P R766 +3VALW C785 Y5 15P_0402_50V8J IN 1 OUT USB_OC#0 21,25 C784 NC The circuit is reserve for new design for pre-MP LAN_WAKE# 28 NC EC_SWI# 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% USB_OC#0_R R753@ R754 R756@ R757 SB_WAKE# 15P_0402_50V8J 23,27 C EC_SI_SPI_SO 34 EC_SO_SPI_SI 34 SPI_CLK 34 SPI_CS# 34 @ 20M_0603_5% A 100P_0402_50V8J 100P_0402_50V8J DAC_BRIG 18 EN_DFAN1 IREF 39 CHGVADJ 39 SPI Device Interface SPI Flash ROM 39 CH751H-40PT_SOD323-2 23 23 PM_SLP_S4# PS2 Interface CEC_INT# 100K_0402_5% 23 PM_SLP_S3# B BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 63 64 65 66 75 76 DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 KSO1 47K_0402_5% 47K_0402_5% PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 21 23 26 27 PWM Output AD Input KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 +3VL INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 +3VL GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC P C778 @ 22P_0402_50V8J 10 22 GATEA20 22 KB_RST# 23,31,34 SERIRQ 22,34 LPC_FRAME# 22,34 LPC_AD3 22,34 LPC_AD2 22,34 LPC_AD1 22,34 LPC_AD0 G D SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet 33 of 45 LPC Debug Port Lid SW SPI Flash (16Mb*1) Please place the PAD under DDR DIMM +3VALW It's for 16" using 20mils U46 VCC W HOLD C D 33 EC_SO_SPI_SI C822 0.1U_0402_16V4Z 16@ S +3VALW Q H1 +3VS LID_SW# 33 PLT_RST# 8,17,21,27,28,33 LPC_AD3 LPC_AD2 22,33 LPC_AD1 LPC_AD0 22,33 10 CLK_PCI_DDR 23,31,33 SERIRQ C823 10P_0402_50V8J 16@ 22,33 22,33 33 SPI_CS# 33 SPI_CLK VSS VOUT It's for 17" using R761 0_0402_5% 22,33 LPC_FRAME# U50 17@ APX9132ATI-TRL_SOT23-3 EC_SI_SPI_SO 33 @ DEBUG_PAD GND SST25LF080A_SO8-200mil VDD VOUT R764 22_0402_5% LID_SW# 16 0.1U_0402_16V4Z VDD C786 GND U48 16@ APX9132ATI-TRL_SOT23-3 +3VL R953 33_0402_5% 1 C852 reserve for EMI, close to U46 33P_0402_50V8J C838 10P_0402_50V8J 17@ 1 SPI_CLK C836 0.1U_0402_16V4Z 17@ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/07/22 Deciphered Date C820 22P_0402_50V8J 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet 34 of 45 ISPD Power Button U3 ZZZ U3 +3VL NB_PM_R1 NB_PM_R3 PCB R765 D PCB ZKU LA-4982P REV1 CANTIGA PM PMR3@ PJP1 U3 CANTIGA PM PMR1@ D 100K_0402_5% ON/OFFBTN# ON/OFFBTN# 26,33 TOP side SMT1-05-A_4P SW6 NB_GL40_R1 NB_GL40_R3 PJP1 KSWAA45@ Q28A 2N7002DW-T/R7_SOT363-6 CANTIGA GL40 GL40R3@ CANTIGA GL40 GL40R1@ U3 U9 another at page36 EC_ON U3 PJP1 R767 10K_0402_5% For EMI request SMT1-05-A_4P DC-IN 17 @ DC-IN 16 BTM side 33 37 @ 51_ON# C646 0.1U_0402_16V4Z @ SW5 NB_GM45_R1 PJP1 KTWAA45@ debug phase using SB_R1 CANTIGA GM45 GM45R1@ ICH9-M ES ICH9R1@ Screw Hole 2N7002DW-T/R7_SOT363-6 H13 H14 H21 H22 H15 H23 H16 H17 H24 H18 H26 H19 H27 H20 H28 H_3P0 @ H_3P0 @ H_3P0 @ H_3P0 @ H_3P0 @ H_3P0 @ H_3P0 @ H_3P0N @ H_3P0N @ Q30A C H29 H_3P0 @ H40 BATT CHARGE/FULL LED +3VALW Vf=1.9V(typ),2.4V(max) for amber Vf=2.0V(typ),2.4V(max) for green If=30mA(max) R770 120_0402_5% H_3P0 @ H_3P0 @ H_3P0 @ H_3P0 @ H_3P1N @ H_3P0 @ PWR_ON_LED# 33 H_3P0 @ H_3P0 @ PWR_SUSP_LED# 33 D68 another at page36 H12 POWER/SUSPEND LED D67 2 120_0402_5% HT-110UYG-CT_YEL/GRN R768 H11 23,33,37 +3VALW ACIN Vf=2.0V(typ),2.4V(max) If=30mA(max) DC-IN LED C H_4P1X3P1N @ HT-210UD/UYG_AMB/GRN H38 H39 D70 BATT_FULL_LED# 33 H32 H33 H34 H35 H_3P7 @ H_3P7 @ H_3P7 @ 1 WL&BT LED H_3P7 @ B D74 2 120_0402_5% HT-110UD_1204_AMBER WLAN@ WLAN@ R777 H30 WL_BT_LED# 33 H31 MDC +3VS H_3P7 @ CPU HT-210UD/UYG_AMB/GRN B H_3P7 @ 120_0402_5% H_3P2 @ H36 MINI CARD 1 R773 H_3P2 @ H37 H_3P7 @ +3VALW BATT_CHG_LOW_LED# 33 VGA H_3P7 @ PCB Fedical Mark PAD +3VS R780 D76 2 120_0402_5% HT-110UYG-CT_YEL/GRN FD3 @ FD4 @ A R779 10K_0402_5% +3VS HDD LED FD2 @ @ FD1 SATA_LED# 22 A Q31A 2N7002DW-T/R7_SOT363-6 Compal Electronics, Inc Compal Secret Data Security Classification Q31B 2N7002DW-T/R7_SOT363-6 2009/07/22 Issued Date Deciphered Date 2012/07/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC MB A4982 Document Number Rev B 401791 Wednesday, December 30, 2009 Sheet 35 of 45 B C +3VALW TO +3VS +5VALW TO +5VS +3VALW +5VALW +1.5V Q36B FDS6676AS C834 2 2 R783 1U_0402_6.3V4Z R789 820K_0402_5% R786 +VSB 220K_0402_5% 470_0805_5% C829 SI4856ADY_SO8 Q36A SUSP 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R788 200K_0402_5% @ S S S G C833 1 +VSB D D D D C832 1 R785 47K_0402_5% 470_0805_5% 1U_0402_6.3V4Z C828 Q34 Q37A Q37B SUSP 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 Q35B R782 1 SI4800BDY_SO8 Q35A SUSP 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 Vgs=10V,Id=14.5A,Rds=6mohm 4.7U_0805_10V4Z 2 S S S G R787 330K_0402_5% +VSB D D D D C831 1 2 0.022U_0402_25V7K 4.7U_0805_10V4Z C830 R784 47K_0402_5% C827 1U_0402_6.3V4Z SI4800BDY_SO8 R781 2 C826 0.01U_0402_25V7K 4.7U_0805_10V4Z +1.5VS 4.7U_0805_10V4Z Q33 S S S G 4.7U_0805_10V4Z 1 D D D D C825 C824 470_0805_5% Q32 Inrush current = 0A Vgs=10V,Id=9A,Rds=18.5mohm +1.5V to +1.5VS +5VS 4.7U_0805_10V4Z Inrush current = 0A E 0.1U_0402_25V6 +3VS D C835 A +3VALW TO +3V_LAN +3VALW TO +3V_SB +3VALW +3VALW D G 1U_0402_6.3V4Z STAR@ SBPWR_EN# 2N7002DW-T/R7_SOT363-6 R805 200K_0402_5% STAR@ Q46B STAR@ C845 0.1U_0402_25V6 STAR@ Q46A STAR@ C841 2 R804 20K_0402_5% STAR@ R803 470_0805_5% STAR@ 2 C840 4.7U_0805_10V4Z @ C844 STAR@ +VSB 1U_0402_6.3V4Z 1 C843 4.7U_0805_10V4Z STAR@ STAR@ SI3456BDV-T1-E3_TSOP6 2 Inrush current = 0A current = 0A @ JUMP_43X79 1 1 C842 10U_0805_10V4Z STAR@ S 2 WOL_EN# Q44 Vgs=10V,Id=6A,Rds=35mohm PJ35 JUMP_43X79 @ +3V_LAN G 33 C839 Q41 0.1U_0402_16V7K AO3413_SOT23 STAR@ STAR@ 1 2 R795 47K_0402_5% STAR@ C837 0.01U_0402_25V7K STAR@ Inrush D S +3V_SB PJ36 Vgs=-4.5V,Id=3A,Rds