5520 LA 8241p

A C D MODEL NAME : QCL00_QCL20 PCB NO : LA-8241P BOM P/N : 4619GP31L21 Inspiron DIS 4619GQ31L21 Inspiron UMA 4619GP31L01 Vostro DIS 4619GQ31L01 Vostro UMA E c n B om Dell / Compal Confidential Inspron A5 & Vostro 3560 (Intel Chief River) Ivy Bridge(rPGA) + Panther Point(mainstream) ix c Schematic Document af Discrete AMD Thames-XT in c h 2012-02-01 46@ : for 46 level @ : Nopop Component Rev: 1.0 CONN@ : Connector Component KB930@ : ENE KB930 Implemented MB Type KB9012@ : ENE KB9012 Implemented EXP@ : Express Card Implemented FFS@ : Only for Free Fall Sensor VOS@ : Only for Vostro INS@ : Only for Inspiron UMA@ : Only for UMA GCLK@ : Green CLK implemented AMP@ : External Amplifier implemented KBBL@ : Keyboard Back Light implemented A ww BOM P/N Config Compal Electronics, Inc Compal Secret Data 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B C Security Classification Issued Date X76@ : VRAM Group CH@ : Chelsea M2 SE@ : Seymour M2 TH@ : Thames-XT DIS@ : Only for Discrete D Cover Page Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet E of 56 B C D Compal Confidential P.25 64M*16 Intel Ivy Bridge Processor 35W QC rPGA 988 35W DC rPGA 988 64bit 64M*16 VRAM * P.41 DDR3 64bit AMD Thames-XT / Chelsea Pro 24-26 W P.34~39 PEG 3.0 x16 Memory Bus (DDR3) Dual Channel 1.5V DDR3 1333 MHz page 11,12 8GB Max DMI x4 100MHz 5GB/s c FDI x8 Port SATA3.0 CRT CRT Conn LVDS Conn HDMI HDMI Conn P.23 USB2.0 P.28 Port Ethernet RTL8105E (10/100) RTL8111F (10/100/1000) P.32 Daughter board P.25 4MB P.13 2MB P.13 P.27 ww Int.KBD A page 25 Daughter board P.29 USB 3.0 Conn USB 3.0 Conn P.32 Digital Camera P.22 Daughter board ( Half ) P.32 Card Reader RTS5139 P.32 Finger Print Daughter board in Socket Daughter board P.32 P13~20 Digital Mic LPC Bus ENE KBC KB9012 / KB930 page DC/DC Interface CKT P.32 USB 3.0 Conn P.33 USB 3.0 Conn -( USB Charger ) HD Audio Headphone Jack Audio Codec CX20672 33MHz SPI SPI ROM P.29 Mini Card-1 (WLAN) Port 10 SPI c h Power On/Off CKT Port Port Daughter board SPI ROM P.13 Port 12 RJ45 34mm Slot Daughter board Port 0,1 Port 3,4 Port 2,3 af Express Card Port 1,2 BGA 989 Balls in Mini Card-1 WLAN / BT4.0 Half P.32 USB 3.0 USB2.0 PCI-E x1 Port SATA ODD Conn ix P.22 Port ( Full ) Port Intel Panther Point PCH HM77 FFS P.29 Mini Card-2 (mSATA) Port LVDS Port 11 SATA HDD Conn Port P.22 BANK 0, 1, 2, 3, ,5 ,6 ,7 P.5~10 100MHz 2.7GT/s DDRIII-DIMM X2 om VRAM * P.40 DDR3 CPU XDP Conn P.6 Fan Control Project Code : QCL00 / QCL20 File Name : LA-8241P RTC CKT E c n A P.30 Mic Jack SPI Amplifier TPA3113D2 24 P.31 Int Speaker R/L only for Vostro 3560 PS/2 Touch Pad page 25 Dashboard Button page x3 32 SPI ROM 128K page 26 reserved for KB930 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Block Diagram Size B C D Document Number Rev 1.0 LA-8241P Date: Wednesday, February 01, 2012 E Sheet of 56 A B C D c n Compal Confidential Project Code : QCL00 / QCL20 File Name : LA-8241P pin-Hot Bar LS-8241P (Ins) LED/B LS-8251P (Vos) Led2 pin-Hot Bar LS-8245P (Ins) LS-8255P (Vos) SW1 Led1 SW1 LED/B FFC pin pin pin LA-8241P M/B Lid (Inspiron) SW2 SW3 Lid (Vostro) JFC pin JLVDS 40 pin JPWR Led3 c FFC Led2 LS-8242P (Ins) LS-8252P (Vos) FFC pin IO/B ix 80 pin JBTB1 L JCR2 pin af pin TP Led (Ins) JCR1 pin in JLED JEXP 26 pin 10 pin (Vostro) FFC Camera LCD Panel FFC 40 pin pin Wire pin-Hot Bar Card Reader/B 26 LS-8243P (Ins) LS-8253P (Vos) (Inspiron) c h 10 pin R (Vostro) TP Led (Vos) Touch Pad JFP pin JTP om Led1 E LS-8244P (Ins) LS-8254P (Vos) LED/B Express Card 10 pin-Hot Bar A Led2 Led3 ww Led1 pin-Hot Bar Led4 Finger Print/B LS-8256P (Vos) Top Side Bottom Side Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B C D Block Diagram Document Number Rev 1.0 Wednesday, February 01, 2012 Sheet E of 56 A Board ID 3.3V +/100K +/Rb 8.2K +/18K +/33K +/56K +/100K +/200K +/NC 5% 5% 5% 5% 5% 5% 5% 5% USB PORT# BOARD ID Table V AD_BID V 0.168 V 0.375 V 0.634 V 0.958 V 1.372 V 1.851 V 2.433 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0.155 V 0.362 V 0.621 V 0.945 V 1.359 V 1.838 V 2.420 V 3.300 V EC AD3 0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF Board ID PCB Revision 0.1 0.1 0.2 0.2 0.3 0.2 0.3 0.3 1.0 1.0 1.0 QCL00 QCL20 SMBUS Control Table KB9012 EC_SMB_CK2 EC_SMB_DA2 KB9012 PCH_SML0CLK PCH_SML0DATA PCH PCH_SML1CLK PCH_SML1DATA PCH MEM_SMBCLK MEM_SMBDATA PCH CLKOUT MINI2 BATT SODIMM Express Card Thermal Sensor FFS VGA Thermal VGA Sensor XDP V V V V Link V V V V V V DESTINATION EC LPC PCI2 None PCI3 None PCI4 None DIFFERENTIAL CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4 CLKOUT_PCIE5 10/100/1G LAN USB conn.1 USB conn.2 - Power Share USB conn.3 USB conn.4 MINI CARD-1 (WLAN) NC NC NC Finger Print NC 10 Card Reader 11 Express Card 12 Camera 13 NC SATA DESTINATION PCI EXPRESS DESTINATION SATA0 HDD Lane 10/100/1G LAN SATA1 SSD Lane MINI CARD-1 (WLAN) SATA2 ODD Lane Express Card SATA3 None Lane None SATA4 None Lane None SATA5 None Lane None Lane None Lane None DESTINATION None MINI CARD-1 WLAN CLKOUTFLEX1 None Express Card CLKOUTFLEX2 None None CLKOUTFLEX3 None Symbol Note : : means Digital Ground None None CLKOUT_PCIE6 None CLKOUT_PCIE7 None CLKOUT_PEG_B FLEX CLOCKS CLKOUTFLEX0 ww CLK DESTINATION in PCI1 af PCH_LOOPBACK c h PCI0 Charger ix EC_SMB_CK1 EC_SMB_DA1 MINI1 c SOURCE PCH QCL01 DESTINATION om Vcc Ra c n Board ID Table for AD channel None : means Analog Ground Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A Notes List Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet of 56 +VCCP JCPU1A DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI_FSYNC0 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC FDI_INT H20 FDI_LSYNC0 FDI_LSYNC1 J19 H17 FDI_INT FDI0_LSYNC FDI1_LSYNC +VCCP +EDP_COM 24.9_0402_1% 10K_0402_5% @ B A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD C15 D15 eDP_AUX eDP_AUX# C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] eDP RC36 RC158 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 CC9 CC10 CC11 CC12 CC13 CC14 CC15 CC16 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K 220nF_0402_16V7K PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 1 1 1 1 2 2 2 2 CC25 CC26 CC27 CC28 CC29 CC30 CC31 CC32 1 1 1 1 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 A ww c h Sandy Bridge_rPGA_Rev1p0 CONN@ PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 om DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] c B28 B26 A24 B23 JCPU1I ix DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 J22 J21 H22 af PEG_COMP PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO in DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS* - GRAPHICS B27 B25 A25 B24 Intel(R) FDI C DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI D PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils - typical impedance = 14.5 mohms RC2 24.9_0402_1% c n VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 D C B Sandy Bridge_rPGA_Rev1p0 CONN@ A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 PROCESSOR(1/6) DMI,FDI,PEG Document Number Rev 1.0 LA-8241P Sheet Wednesday, February 01, 2012 of 56 @ @ RC22 H_CPUPWRGD_XDP RC23 CFD_PWRBTN#_XDP 1K_0402_5% 0_0402_1% 1 @ @ RC24 XDP_HOOK2 RC26 SYS_PWROK_XDP PCH_SMBDATA PCH_SMBCLK PCH_JTAG_TCK 0_0402_5% @ CLK_CPU_ITP CLK_CPU_ITP# XDP_RST#_R XDP_DBRESET# @ RC25 XDP_TDO RC28 XDP_TRST#_R XDP_TDI RC31 XDP_TMS_R RC29 PLT_RST# 1K_0402_5% @ @ @ PCH_JTAG_TDO 0_0402_5% 0_0402_5% PCH_JTAG_TDI PCH_JTAG_TMS +VCCP 2 CC36 0.1U_0402_16V7K CC35 0.1U_0402_16V7K @ RC27 1K_0402_5% SYS_PWROK_XDP AL33 CATERR# H_PECI AN33 PECI H_PROCHOT# B H_THERMTRIP# H_THERMTRIP# PROCHOT# AN32 @ H_PM_SYNC_R RC49 0_0402_1% AM34 H_CPUPWRGD @ RC53 H_CPUPWRGD_R 0_0402_1% AP33 RC57 VDDPWRGOOD VDDPWRGOOD_R 130_0402_1%~D BUF_CPU_RST# V8 AR33 ix CLOCKS SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# PRDY# PREQ# TCK TMS TRST# TDI TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] H_CPUPWRGD_R ww @ Sandy Bridge_rPGA_Rev1p0 CONN@ 10P_0402_50V8J Issued Date UC2 NC VCC A GND Y RC32 75_0402_5% C RC33 BUF_CPU_RST# 43_0402_1% BUFO_CPU_RST# SN74LVC1G07DCKR_SC70-5~D RC37 RC38 A16 A15 CLK_CPU_DPLL_R CLK_CPU_DPLL#_R RC39 RC40 @ @ 0_0402_1% 0_0402_1% 1K_0402_1% 1K_0402_1% PU/PD for JTAG signals +VCCP +VCCP Remove DPLL Ref clock (for eDP only) R8 AK1 A5 A4 H_DRAMRST# H_DRAMRST# SM_RCOMP0 140_0402_1%1 SM_RCOMP1 25.5_0402_1%1 SM_RCOMP2 200_0402_1%1 RC55 RC58 RC60 XDP_PRDY# RC1211 XDP_PREQ# RC1221 @ @ 0_0402_5% 0_0402_5% XDP_PRDY#_R XDP_PREQ#_R AR26 AR27 AP30 XDP_TCK RC1231 XDP_TMS RC1241 XDP_TRST# RC1251 @ @ @ 0_0402_1% 0_0402_1% 0_0402_1% XDP_TCK_R XDP_TMS_R XDP_TRST#_R AR28 AP26 XDP_TDI_R XDP_TDO_R AL35 XDP_DBRESET#_R AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 @ @ 51_0402_5% XDP_TDI_R 51_0402_5% XDP_PREQ# 51_0402_5% XDP_TDO 51_0402_5% RC48 RC45 RC46 @ RC47 51_0402_5% RC52 XDP_TRST#_R 51_0402_5% RC54 XDP_DBRESET# 1K_0402_5% RC42 H_CPUPWRGD_R 10K_0402_5%1 RC44 0_0402_1% XDP_TDI 0_0402_1% XDP_TDO XDP_DBRESET# @ 0_0402_1% RC56 XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R RC59 RC61 RC62 RC63 RC64 RC65 RC66 RC67 1 1 1 1 @ @ @ @ @ @ @ @ 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 RC68 RC69 RC70 RC71 1 1 @ @ @ @ 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% B +3VS XDP_DBRESET# XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 CFG12 CFG13 CFG14 CFG15 A Compal Electronics, Inc Compal Secret Data 2012/01/17 XDP_TMS_R XDP_TCK_R AP29 AP27 RC50 RC51 @ RC34 0_0402_5% CLK_CPU_DMI CLK_CPU_DMI# 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: +VCCP CLK_CPU_DMI_R CLK_CPU_DMI#_R Security Classification 2 DDR3 Compensation Signals CC64 A +3VALW A28 A27 THERMTRIP# c h H_PM_SYNC AL32 in RC41 H_PROCHOT#_R 56_0402_1% PWR MANAGEMENT RC43 62_0402_5% af H_CATERR# DPLL_REF_CLK DPLL_REF_CLK# JTAG & BPM @ T1 BCLK BCLK# DDR3 MISC SKTOCC# +VCCP MISC AN34 PROC_SELECT# THERMAL C26 H_SNB_IVB# @ QC1 SSM3K7002F_SC59-3 CC63 0.1U_0402_16V7K JCPU1B S PLT_RST# Place near JXDP1 D RUN_ON_CPU1.5VS3# G RUN_ON_CPU1.5VS3# 0_0402_5% +3VALW PAD~D 2 @ CLK_CPU_ITP CLK_CPU_ITP# SAMTE_BSH-030-01-L-D-A CONN@ C RC8 CRB 1.1K CHECK LIST 0.7 > 4.75K RC19 INTEL recommand 1.1K 39_0402_1% PDG 0.71 rev >200 CC34 0.1U_0402_16V7K The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net RC30 XDP_TCK1 XDP_TCK_R 200_0402_1% D VDDPWRGOOD 74AHC1G09GW TSSOP 5P 1 CFG0 VGATE 1K_0402_5% 0_0402_5% B VCC A GND Y RC8 200_0402_1% H_CPUPWRGD PBTN_OUT# +3V_PCH UC1 +1.5V_CPU_VDDQ XDP_BPM#6 XDP_BPM#7 RC4 XDP_BPM#4 XDP_BPM#5 @ 2D_PWG 0_0402_1% RC11 PM_DRAM_PWRGD @ RC6 10K_0402_5% 1 RC13 CFG10_R RC15 CFG11_R @ @ @ 2 RC127 0_0402_1% @ 0_0402_5% 0_0402_5% CFG10 CFG11 RC128 SYS_PWROK om +3V_PCH +3VS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 c XDP_BPM#2 XDP_BPM#3 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 CC33 0.1U_0402_16V7K XDP_BPM#0 XDP_BPM#1 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 c n PCH_PWROK JXDP1 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP_PREQ#_R XDP_PRDY#_R D +VCCP 0_0402_5% +VCCP PROCESSOR(2/6) PM,XDP,CLK Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet of 56 JCPU1C JCPU1D B DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AE8 AD9 AF9 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# RSVD_TP[1] RSVD_TP[2] RSVD_TP[3] AA5 AB5 V10 M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA AB3 AA3 W10 SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8] AK3 AL3 AG1 AH1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10] AH3 AG3 AG2 AH2 M_ODT0 M_ODT1 C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_CAS# SA_RAS# SA_WE# M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA AB4 AA4 W9 RSVD_TP[4] RSVD_TP[5] RSVD_TP[6] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] DDR_B_D[0 63] DDR_CS0_DIMMA# DDR_CS1_DIMMA# M_ODT0 M_ODT1 DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] c h Sandy Bridge_rPGA_Rev1p0 CONN@ DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CLK[0] SB_CLK#[0] SB_CKE[0] SB_CLK[1] SB_CLK#[1] SB_CKE[1] om SA_BS[0] SA_BS[1] SA_BS[2] SA_CLK[1] SA_CLK#[1] SA_CKE[1] M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA c AE10 AF10 V6 SA_CLK[0] SA_CLK#[0] SA_CKE[0] ix SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] af C C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA in DDR_A_D[0 63] D AB6 AA6 V9 c n AA9 AA7 R6 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AA10 AB8 AB9 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# RSVD_TP[11] RSVD_TP[12] RSVD_TP[13] RSVD_TP[14] RSVD_TP[15] RSVD_TP[16] SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18] DDR SYSTEM MEMORY B SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] AE2 AD2 R9 M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB AE1 AD1 R10 M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB D M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB AB2 AA2 T9 AA1 AB1 T10 AD3 AE3 AD6 AE6 DDR_CS2_DIMMB# DDR_CS3_DIMMB# AE4 AD4 AD5 AE5 M_ODT2 M_ODT3 D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT2 M_ODT3 C DDR_B_DQS#[0 7] DDR_B_DQS[0 7] DDR_B_MA[0 15] B Sandy Bridge_rPGA_Rev1p0 CONN@ +1.5V @ RC74 0_0402_5% QC2 D S H_DRAMRST# H_DRAMRST# RC75 1K_0402_5% BSS138_SOT23 DDR3_DRAMRST#_R RC76 1K_0402_5% DDR3_DRAMRST# G RC77 4.99K_0402_1% RC72 DRAMRST_CNTRL ww A @ 0_0402_1% DRAMRST_CNTRL_PCH A DRAMRST_CNTRL CC37 047U_0402_16V7K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PROCESSOR(3/6) DDRIII Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet of 56 c n CFG Straps for Processor D D CFG2 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 T89 @ T90 @ PAD~D PAD~D PAD~D RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 @ T10 @ T11 @ T12 @ T13 PAD~D PAD~D PAD~D PAD~D RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 AR35 AT34 AT33 AP35 AR34 @ T14 @ T15 @ T16 @ T17 @ T18 PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D +SA_DIMM_VREFDQ T19 @ AJ26 VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE RSVD5 +SB_DIMM_VREFDQ @ PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D RC85 1K_0402_1% RSVD6 RSVD7 RC159 +3VS 10K_0402_5% B T25 T26 T27 T28 T30 T32 T33 T34 T35 T37 T38 T39 T40 T41 T42 T43 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 PAD~D T44 @ PAD~D T45 @ H_VCCP_SEL J20 B18 A19 PAD~D J15 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 VCCIO_SEL T49 @ CFG4 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 VCC_DIE_SENSE B34 A33 A34 B35 C35 AJ32 AK32 @ T20 @ T21 @ T22 @ T23 @ T24 PAD~D PAD~D PAD~D PAD~D PAD~D @ T29 @ T31 PAD~D PAD~D @ T36 AH27 RSVD54 RSVD55 AN35 AM35 RSVD56 RSVD57 RSVD58 AT2 AT1 AR1 CFG4 INTEL 12/28 recommand to add RC120, RC121, RC122, RC123 Please place as close as JCPU1 attached to Embedded Display Port CFG5 PAD~D @ T46 @ T47 @ T48 PAD~D PAD~D PAD~D @ T50 PAD~D RC87 1K_0402_1% CLK_RES_ITP CLK_RES_ITP# @ RC86 1K_0402_1% PCIE Port Bifurcation Straps B 11: (Default) x16 - Device functions and disabled B1 CFG[6:5] *10: x8, x8 - Device function enabled ; function disabled 01: Reserved - (Device function disabled ; function enabled) 00: x8,x4,x4 - Device functions and enabled c h @ RC91 50_0402_1% ww A @ RC90 50_0402_1% * : Disabled; No Physical Display Port CFG6 Sandy Bridge_rPGA_Rev1p0 CONN@ VSS_VAL_SENSE C : Enabled; An external Display Port device is connected to the Embedded Display Port RSVD27 KEY VSS_AXG_VAL_SENSE @ RC81 1K_0402_1% Display Port Presence Strap in @ RC84 1K_0402_1% B4 D1 1 +SA_DIMM_VREFDQ +SB_DIMM_VREFDQ 1:(Default) Normal Operation; Lane # definition matches socket pin map definition *0:Lane Reversed ix VSS_VAL_SENSE C AJ31 AH31 AJ33 AH33 af VSS_AXG_VAL_SENSE VCC_VAL_SENSE PEG Static Lane Reversal - CFG2 is for the 16x CFG2 RESERVED VCC_AXG_VAL_SENSE om PAD~D PAD~D @ T7 @ T8 @ T9 @ @ AT26 AM33 AJ27 T87 T88 RSVD33 RSVD34 RSVD35 PAD~D PAD~D RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 @ CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] @ RC80 50_0402_1% T86 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 2 @ RC79 50_0402_1% PAD~D CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 PAD~D PAD~D PAD~D PAD~D PAD~D 2 +VCC_CORE CFG0 T85 @ @ T2 @ T3 @ T4 @ T5 @ T6 c +VCC_GFXCORE_AXG PAD~D RC78 1K_0402_1% L7 AG7 AE7 AK2 W8 JCPU1E CFG7 @ RC89 1K_0402_1% PEG DEFER TRAINING CFG7 *1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A PROCESSOR(4/6) RSVD,CFG Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet of 56 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 SVID VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 om 1 +VCCP RC95 RC93 75_0402_5% RC95 close to CPU 130_0402_1%~D H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT ww A RC94 RC92 RC96 @ @ 43_0402_1% 0_0402_1% 0_0402_1% VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT +VCC_CORE AJ35 VCCSENSE_R AJ34 VSSSENSE_R RC98 RC99 @ @ 0_0402_1% 0_0402_1% VCCSENSE VSSSENSE VCC_SENSE VSS_SENSE RC97 100_0402_1% VCCIO_SENSE VSSIO_SENSE +VCCP B10 A10 RC100 100_0402_1% RC108 10_0402_1% RC111 10_0402_1% VCCIO_SENSE A Sandy Bridge_rPGA_Rev1p0 CONN@ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Place the PU resistors close to CPU B SENSE LINES c h B C J23 VCCIO40 D c VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 ix PEG AND DDR 8.5A VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 in C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 +VCCP af AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 D POWER QC=94A DC=53A +VCC_CORE JCPU1F c n CORE SUPPLY PROCESSOR(5/6) PWR,BYPASS Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet of 56 RC105 330K_0402_1% QC5B RUN_ON_CPU1.5VS3# D 2N7002DW-7-F_SOT363-6 QC5A 2N7002DW-7-F_SOT363-6 @ RC104 0_0402_5% RC107 0_0402_5% 2 JCPU1H +VCC_GFXCORE_AXG RC113 @ CC40 0.1U_0402_10V7K~D 10_0402_1% VCC_AXG_SENSE +V_SM_VREF @ QC4 NTR4503NT1G_SOT23-3~D ix RUN_ON_CPU1.5VS3 5A 1K_0402_5% RC116 @ +1.5V_CPU_VDDQ AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 @ JP10 1 2 2 2 +1.5V PAD-OPEN 4x4m J8 OPEN + CC47 330U_D2_2VM_R6M~D af VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 +VCCSA M27 M26 L26 J26 J25 J24 H26 H25 6A 2 2 @ + VCCSA_SENSE C22 C24 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS VCCSA_SENSE +1.5V_CPU_VDDQ VCCSA_VID0 VCCSA_VID1 C @ RC110 0_0402_5% +1.5V CC53 0.1U_0402_10V7K~D CC58 0.1U_0402_10V7K~D CC59 0.1U_0402_10V7K~D CC60 0.1U_0402_10V7K~D add CC181 , CC182, caps are all pop follow checklist 1.0 5/24 A ww D B Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 Title PROCESSOR(6/6) PWR,VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D Document Number DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-8241P Date: AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 Sandy Bridge_rPGA_Rev1p0 CONN@ H23 c h FC_C22 VCCSA_VID1 CC48 330U_D2_2VM_R6M~D in MISC 1.8V RAIL Sandy Bridge_rPGA_Rev1p0 CONN@ VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 c 1K_0402_5% RC112 +V_SM_VREF_CNT SENSE LINES VREF AL1 CC46 10U_0805_4VAM~D SM_VREF CC52 10U_0603_6.3V6M + @ 0_0402_5% CC45 10U_0805_4VAM~D VCCPLL1 VCCPLL2 VCCPLL3 @ RC106 +V_SM_VREF should have 10 mil trace width CC51 10U_0805_4VAM~D B6 A6 A2 @ 1K_0402_5% CC44 10U_0805_4VAM~D CC57 330U_D2_2.5VM_R6M~D @ CC62 10U_0805_4VAM~D CC61 10U_0805_4VAM~D CC56 1U_0402_6.3V6K A CC55 1U_0402_6.3V6K CC54 10U_0805_4VAM~D +1.5V RC129 CC50 10U_0805_4VAM~D +1.8VS_VCCPLL 0_0805_1% +1.5V_CPU_VDDQ 10_0402_1% CC43 10U_0805_4VAM~D @ CC49 10U_0805_4VAM~D VSS_AXG_SENSE RC114 AK35 AK34 CC42 10U_0805_4VAM~D 1.2A RC109 VSS_AXG_SENSE VAXG_SENSE VSSAXG_SENSE 1K_0402_5% B +1.8VS @ RC126 DDR3 -1.5V RAILS C VCC_AXG_SENSE 100_0402_1% CC41 10U_0805_4VAM~D AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 POWER SA RAIL 33A AT24 GRAPHICS +VCC_GFXCORE_AXG JCPU1G RC157 2 AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 om RUN_ON_CPU1.5VS3# 1 CPU1.5V_S3_GATE 1 SUSP# CC39 0.1U_0603_50V_X7R RUN_ON_CPU1.5VS3 2 RC101 100K_0402_5% RC102 100K_0402_5% +1.5V_CPU_VDDQ CC38 10U_0805_10V6K 1 RC103 20K_0402_5% QC3 AO4728L_SO8~D B+_BIAS c n +1.5V_CPU_VDDQ Source +1.5V +3VALW Wednesday, February 01, 2012 Sheet 10 of 56 Version Change List ( P I R List ) Item Page# Title Date Request Owner Page Issue Description Solution Description 08,11,12 DIMM 11/07/28 COMPAL The M3 traces are routed to the Sandy Bridge Processor reserved pins for DDR3 VREF 18,19 PCH 11/07/28 COMPAL VCCDMI, V_PROC_IO change to +VCCP from +1.05VS Intel CHKLST Rev1.5 required 09,10 CPU 11/07/28 COMPAL remove decoupling cap for +VCC_CORE, +VCCP, +VCC_GFXCORE_AXG, owner change to PWR Intel CHKLST Rev1.5 required 10 CPU 11/07/28 COMPAL VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent (SA) VR controller Intel CHKLST Rev1.5 required Intel CHKLST Rev1.5 required Rev 0.1 D D 0.1 0.1 0.1 om c 10 11 12 13 C c n 14 C ix 15 16 17 in af 18 B c h B A ww A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HW-PIR Size Date: Document Number Rev 1.0 Wednesday, February 01, 2012 Sheet 42 of 56 B VIN 1 PR902 2.2K_0402_5% 2 c n PD901 BAV99W-7-F_SOT-323-3~D D S PD900 DA204U_SOT323~D PR905 10K_0402_1% 1VSB_N_003 PC910 1U_0402_16V7K PR912 0_0402_5% 2VSB_N_002 G PR908 22K_0402_1% af POK EC_SMB_DA1 in +3VALW EC_SMB_CK1 PR913 100_0402_5% 0_0402_5% PR919 B+_BIAS 1 PQ902 TP0610K-T1-E3_SOT23-3 VSB_N_001 PQ903 2N7002KW _SOT323-3 SMART Battery: 01.BATT1+ 02.BATT2+ 03.CLK_SMB 04.DAT_SMB 05.BATT_PRS 06.SYS_PRES 07.BAT_ALERT 08.GND1 09.GND2 PBATT1 battery connector (Follow E3) PR909 100K_0402_1% PR914 100_0402_5% ALLTO_C144FE-109A7-L 2 PR927 13K_0402_1% 130W /90W # PR916 @ 13K_0402_1% VCIN0_PH 1 G 1 D S +3VLP PR917 65W/90W# 499K_0402_1% 65W 90W High Low 130W PC915 @ PH900 100K_0402_1%_TSM0B104F4251RZ 1U_0402_16V7K 130W/90W# Low 2 2 S 65W /90W # +3VALW VCIN1_PH VS_N_002 @930 PR923 22K_0402_1% 51_ON# PC912 @930 0.1U_0402_25V6 G 1 PC911 @930 0.22U_0603_25V7K 2 @930 PR922 100K_0402_1% @ D PR926 @ 6.81K_0402_1% 1 VS 2N7002KW_SOT323-3 PQ906 PR915 332K_0402_1% 2N7002KW_SOT323-3 PQ904 PR921 @930 68_1206_5% N1 PR918 90.9K_0402_1% @930 PR920 68_1206_5% c h @930 PQ905 TP0610K-T1-E3_SOT23-3 LL4148_LL34-2 VS_N_001 @930 PD907 BATT+ PH901 under CPU botten side : CPU thermal protection at 90 degree C ADP_I PD906 @930 LL4148_LL34-2 PR911 10K_0402_1% PR910 100_0402_5% S om +3VLP BATT_TEMP CLK_SMB DAT_SMB BATT_PRS SYS_PRES B+ @ PD905 RB751V-40_SOD323-2 PSID-5 10K_0402_1% +RTCBATT +5VALW PBATT9 @ 1 2 3 4 5 6 7 8 9 GND 10 GND 11 PR906 SUYIN_060003FA002G202NL PESD24VS2UT_SOT23-3 @ PD903 @ PD902 SM24_SOT23 + E PC908 0.22U_0603_25V7K - @ PD904 @ PESD24VS2UT_SOT23-3 PQ900 MMST3904-7-F_SOT323~D B PR907 100K_0402_1% 1 JRTC9 @ PSID-1 32 1M_0402_1% PSID-2 c PC907 100P_0402_50V8J PC900 1000P_0402_50V7K 1 BATT++ PR930 High PU900 G920AT24U_SOT89-3 @930 A 4.7U_0603_6.3V6K~D @930 PR924 0_0603_5% PC913 OUT IN @930 GND PR925 PC914 +CHGRTC 1U_0603_25V6K ww @930 +3VLP +5VALW C ix PL900 SMB3025500YA_2P PC906 0.01U_0402_25V7K 2 PC905 100P_0402_50V8J BATT+ PC916 0.1U_0402_25V6 BATT++ PQ907A SSM6N7002FU-2N_SOT363-6 200K_0402_1% BATT+ PQ907B 1 PR928 PR904 100K_0402_1% PR929 1M_0402_1% PS_ID +5VALW PR900 15K_0402_1% ACIN PSID PL902 BLM18BD102SN1D_0603~D 1 ACES_50299-00501-003 +3VALW G PR903 33_0402_5% PSID-3 PQ901 FDV301N_NL_SOT23-3~D D Erp lot6 Circuit VIN SSM6N7002FU-2N_SOT363-6 PR901 @ 0_0402_5% PC904 100P_0402_50V8J PC903 1000P_0402_50V7K PC902 100P_0402_50V8J GND GND 2 2 D +5VALW PR931 1.2K_1206_5%~D 1 @ PJPDC9 PC901 1000P_0402_50V7K ADPIN C VIN PL901 SMB3025500YA_2P PC909 0.1U_0402_25V6 A 200_0805_5% Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC @930 Date: B C PWR-DCIN / BATT CONN / OTP Document Number Rev 1.0 LA-8241P W ednesday, February 01, 2012 D Sheet 43 of 56 A B c n Iada=0~4.62A(90W) P3 CC = 3.52A (Normal) ADP_I = 19.9*Iadapter*Rsense CV = 13.3V B+ PR102 0.01_1206_1% PQ102 AO4407AL_SO8 PR136 1.2K_1206_5%~D 747@ PC131 309K/0402 747@ 0.1U/0402 A PQ106A SSM6N7002FU-2N_SOT363-6 BATT_TEMP PR127 0/0402 PR107 PC112 747@ 20 VREF PGND CSOP 19 18 CE CSON 17 VFB GND 29 NC 16 om PQ113B SSM6N7002FU-2N_SOT363-6 PR121 PL100 0.01_1206_1% 10UH_PCMB063T-100MS_4A_20% CHG DL_CHG PR130 PQ113A SSM6N7002FU-2N_SOT363-6 @ @ 15 VFB PQ108 BATT+ 100_0402_5% BATT+ PC120 10U_0805_25V5K~D LGATE 1U_0603_10V6K ACOFF PC119 10U_0805_25V5K~D EAO PC118 10U_0805_25V5K~D LX_CHG PC115 PC122 10U_0805_25V5K~D 23 PR128 0_0402_5% PHASE 10K_0402_5% DH_CHG EAI PC105 2200P_0402_25V7K~D 1 24 PR132 VDDP_LDO AO4466L_SO8~D UGATE PC106 0.1U_0603_25V7K PC104 4.7U_0805_25V6-K PC103 4.7U_0805_25V6-K 2 VDDP_LDO in PC128 0.1U_0402_10V7K 747@ PC125 747@ 21 747@ V1 PR127 731@ 10_0402_5% FBO VIN PR115 PR124 4.7_1206_5% VDDP af VICM 25 BST ix NC PD101 747@ BAT54HT1G_SOD323-2~D @ 731@ PC126 TP 747@ PC129 0.1U_0603_25V7K ISL88731CHRTZ-T_QFN28_5X5~D @ 0.1U/0603 0.22U_0603_25V7K @ PC130 0.1U_0603_25V7K ISL88731C BQ24747 ISL88731C BQ24747 ISL88731C BQ24747 ISL88731C BQ24747 PU100 ISL88731C BQ24747 PR122 @ 200k PC134 0.01u @ PC108 0.1u @ PR133 @ 100k PR123 @ 7.5k PC129 @ 0.1u PR106 10 PR112 100k @ PR129 @ 10k PC126 0.22u 0.1u PR107 10 PR117 158k @ PC117 @ 2200p PR127 10 PC112 0.047u 0.1u PR113 210k 309k PC124 @ 56p PR111 4.7 @ PC131 0.1u 220p PC123 @ 120p PC110 1u @ 747@ 731@ for ISL88731C 747@ PC132 0/0402 731@ PC108 0.1U_0603_25V7K PR107 731@ 27 BOOT 26 0.1U_0603_25V7K 2BST_CHGA SDA ICOUT PC135 PQ110 SCL 100K_0402_1% PR110 47K_0402_1% c VDDSMB 10 PR111 731@ 4.7_0603_5% PR114 0_0603_5% CSSN ACOK 11 28 13 CSSP ACIN 12 PC126 10_0402_5% 10_0402_5% PR106 PC107 731@ 0.1U_0603_25V7K 2 PR113 210K_0402_1% 731@ 10K_0402_5% 1U_0603_10V6K 56P_0402_50V8~D 747@ PR129 V1 DCIN PR108 200K_0402_1% PC121 680P_0402_50V7K PC102 5600P_0402_25V7K~D 0.1U_0402_10V7K PC109 PC124 731@ PC134 0.01U_0402_25V7K @ ww PQ112B BQ24747 SSM6N7002FU-2N_SOT363-6 @ 747@ PR113 VIN PQ106B SSM6N7002FU-2N_SOT363-6 PU100 22 PC110 731@ 1U_0603_10V6K 7.5K_0402_5% c h S For DT Mode MAX8731_REF @ PC133 0.01U_0402_25V7K PQ111 @ SSM3K7002FU_SC70-3 PR123 MAX8731_REF 0_0402_5% 0_0402_5% PR135 PR134 2 D G 731@ PC132 0.01U_0402_25V7K PC131 1U_0402_16V7K 1 731@ DCIN ACSETIN 14 2200P_0402_50V7K 120P_0402_50VNPO~D H_PROCHOT# ACOFF 747@ PC117 747@ ADP_I 747@ PR122 200K_0402_5% 747@ PC123 BATT_TEMP EC_SMB_DA1 ICREF PR101 200K_0402_1% 747@ PR133 100K_0402_1% 1MAX8731_REF PR125 100_0402_1% @ PC127 1U_0603_25V6K 731@ PU100 PR120 0_0402_5% 1 BATT_TEMP 731@ PC112 0.047U_0603_25V7M 2 PR119 0_0402_5% 2 VIN EC_SMB_CK1 1 PQ112A SSM6N7002FU-2N_SOT363-6 10K_0402_5% PC116 0.1U_0402_10V7K 2 PC111 1U_0603_25V6K PR116 49.9K_0402_1% PR126 4.7K_0402_5% PR131 @ +5VALW 731@ PR117 158K_0402_1% ACIN @ PR109 10_1206_1% CHG_B+ PL101 1UH_NRS4018T1R0NDGJ_3.2A_30% PC113 1000P_0402_50V7K PQ109 DDTC115EUA-7-F_SOT323 2 PR118 47K_0402_5% CSIP ACIN ACOFF PC101 0.1U_0603_25V7K PQ105B SSM6N7002FU-2N_SOT363-6 ACIN BATT_TEMP CSIN VIN PR105 150K_0402_1% 731@ PR112 100K_0402_1% 1VDDP_LDO PQ105A SSM6N7002FU-2N_SOT363-6 PQ104 DDTC115EUA-7-F_SOT323 V1 2 PC100 2.2U_0805_25V6K PR104 2 3.3_1210_5% PR103 200K_0402_1% 1 3.3_1210_5% PR100 PQ103 PDTA144EU PNP_SOT323 PQ107 DDTC115EUA-7-F_SOT323 4 D P2 C PQ100 AO4407AL_SO8 PQ101 AO4409L_SO8 AO4712L_SO8~D VIN 0.01u @ PC125 @ 1u PD101 @ 747@ for BQ24747 BAT54HT1G 0.1U/0603 PR106 747@ @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0/0402 Date: B C PWR-Charger Document Number Rev 1.0 LA-8241P W ednesday, February 01, 2012 D Sheet 44 of 56 D E c n C 2VREF_6182 N_3_5V_001 2.2K_0402_5% PR215 0_0402_5% PR214 100K_0402_5% A LG_5V PC207 0.1U_0402_25V6 NC 19 PL201 3.3UH_PCMC063T-3R3MS_6A_20% 18 VREG5 17 16 VIN ix EN LX_5V SNUB_5V LGATE1 1 2 + PC213 330U_6.3V_M af 2 PC216 4.7U_0805_10V6K @ B++ @ PQ205 AON7702A_DFN8-5 VL +5VALWP @ PC215 680P_0603_50V7K LGATE2 20 BST1_5V PR210 4.7_1206_5% PHASE1 BST_5V 2.2_0603_5% UG_5V PHASE2 13 om ENTRIP1 ENTRIP1 FB1 REF TONSEL 21 PC218 0.1U_0402_25V6 2VREF_6182 VL c h ENTRIP2 22 PJP202 +5VALWP +5VALW +3VALWP 1 PAD-OPEN 4x4m PJP200 PAD-OPEN 4x4m +3VALW 5VALWP TDC 5.6A Peak Current 8A OCP current 9.6A TYP H/S Rds(on) :27mohm , L/S Rds(on) :11mohm , MAX 34mohm 14mohm PAD-OPEN 4x4m PC219 4.7U_0603_10V6K PJP203 PAD-OPEN 4x4m PJP204 3/5V_EN-2 ww @930 BOOT1 UGATE1 PC211 0.22U_0603_10V7K PR208POK SSM6N7002FU-2N_SOT363-6 PR213 PR217 40.2K_0402_1% @930 23 UGATE2 BOOT2 PQ201 DTC115EUA_SC70-3 VS 24 PQ200B 2 PR216 150K_0402_1% PGOOD PQ203 AON7408L_DFN8-5 RT8205LZQW(2) WQFN 24P PWM in ENTRIP2 @ PQ200A VCOUT0_PH PR212 200K_0402_1% AON7702A_DFN8-5 PR206 110K_0402_1% VO1 VREG3 PC217 1U_0603_10V6K VCOUT0_PH PQ204 SSM6N7002FU-2N_SOT363-6 EC_ON_35V PR200 499K_0402_1% BZV55-B5V1_SOD80C2 PR211 @ 0_0402_5% ENTRIP1 MAX 34mohm 14mohm VO2 GND @ B++ 12 @ PD200 SNUB_3V PC212 330U_6.3V_M + 11 LG_3V @ UG_3V 10 LX_3V BST_3V @ PC214 680P_0603_50V7K +3VALWP PR209 4.7_1206_5% PL200 3.3UH_PCMC063T-3R3MS_6A_20% 15 PC210 0.22U_0603_10V7K BST1_3V PR207 2 2.2_0603_5% B++ c 3.3VALWP TDC 5.4A Peak Current 7.7A OCP current 9.2A TYP H/S Rds(on) :27mohm , L/S Rds(on) :11mohm , P PAD 25 PR204 20K_0402_1% PU200 PC206 10U_0805_6.3V6M FB2 PQ202 AON7408L_DFN8-5 PR205 110K_0402_1% PC205 4.7U_0805_25V6-K PC204 2200P_0402_50V7K PC203 0.1U_0402_25V6 +3VLP FB_5V SKIPSEL 1UH_PCMB061H-1R0MS_7A_20% FB_3V 14 B++ PR203 20K_0402_1% PL202 PR202 30.9K_0402_1% PC208 2200P_0402_50V7K 1 PR201 13.7K_0402_1% B+ @ PC200 ENTRIP2 1 2 0.1U_0402_25V6 0.1U_0402_25V6 @ PC202 PC201 1 1U_0603_16V6K B PC209 4.7U_0805_25V6-K A 2012/01/17 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B C D PWR-3VALWP/5VALWP Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet E 45 of 56 B C D c n A 1 VFB=0.6V Vo=VFB*(1+PR401/PR404)=0.6*(1+20K/10K)=1.8V c +1.8VSP TDC 2.6A Peak Current 3.8A OCP current 4.5A PC404 22U_0805_6.3V6M om 22P_0402_50V8J PC402 1 PR400 10K_0402_1% PC400 22U_0805_6.3V6M SY8033BDBC_DFN10_3X3 2 @ PR401 47K_0402_5% PR403 20K_0402_1% 1.8VSP_FB +1.8VSP NC TP 11 EN_1.8VSP 2 PR402 100K_0402_5% PC405 0.22U_0402_16V7K SUSP# FB EN SVIN LX PL400 1UH_NRS4018T1R0NDGJ_3.2A_30% 1.8VSP_LX PR404 4.7_1206_5% PVIN 1SNUB_1.8VSP LX PC401 680P_0603_50V7K PC403 22U_0805_6.3VAM PVIN PAD-OPEN 3x3m 10 NC 1.8VSP_VIN @ PG PJP400 PU400 +3VALW +1.8VSP PJP401 @ +1.8VS PAD-OPEN 3x3m in af ix c h ww 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C PWR-1.8VSP Document Number Rev 1.0 LA-8241P W ednesday, February 01, 2012 D Sheet 46 of 56 +V1.05S_VCCPP_B+ c n @ PJP500 2 1 B+ FB_+V1.05S_VCCPP VFB V5IN +V1.05S_VCCPP_5V RF_+V1.05S_VCCPP TST DRVL LG_+V1.05S_VCCPP SUSP# TP PC506 0.22U_0402_16V7K +5VALW 11 PC500 1U_0603_10V6K TPS51212DSCR_SON10_3X3 PR504 470K_0402_1% 2 PC509 PR507 @ 1000P_0402_50V7K in B PC508 @ 1000P_0402_50V7K PC504 4.7U_0805_25V6-K C PR508 0_0402_5% VCCIO_SENSE @ PJP501 PAD-OPEN 4x4m B +1.05VS +V1.05S_VCCP TDC 11A Peak Current 16A OCP current 19A TYP H/S Rds(on) 10mohm , L/S Rds(on) :3mohm , c h +VCCP ww @ af PR509 10K_0402_1% PC503 4.7U_0805_25V6-K PC501 2200P_0402_50V7K PC502 0.1U_0402_25V6 PR505 @ 4.7_1206_5% +VCCP PR506 @ 1.2K_0402_1% 4.99K_0402_1% A +VCCP ix C PL500 1UH_PCMC063T-1R0MN_11A_20% PC507 SW _+V1.05S_VCCPP 0.1U_0402_10V7K UG_+V1.05S_VCCPP SW DRVH EN TRIP 2 TRIP_+V1.05S_VCCPP 47.5K_0402_1% EN_+V1.05S_VCCPP PR500 2.2_0603_5% c 10 VBST PQ501 PR503 150K_0402_5% BST_+V1.05S_VCCPP PGOOD PU500 PR502 PC505 1U_0603_25V7K om +V1.05S_VCCP_PWRGOOD D 1 PQ500 PR501 100K_0402_5% SIR818DP-T1-GE3_POWERPAK8-5~D D +3VS SIR472DP-T1-GE3_POWERPAK8-5~D JUMP_43X118 A Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Issued Date Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC MAX 14.5mohm 3.6mohm Title PWR-V1.05S_VCCPP Size Document Number Rev 1.0 LA-8241P Date: W ednesday, February 01, 2012 Sheet 47 of 56 0.75Volt +/- 5% TDC 0.7A Peak Current 1A OCP Current 1.2A +5VALW 20 19 18 1.5V_B+ GND VTTREF VTTREF_1.5V VDDQ +1.5V 1U_0402_6.3VX5R FB S3 S5 TON 1.5V_FB PR300 1M_0402_1% PR307 10K_0402_1% PC313 @ 1U_0402_16V7K S3_1.5V +1.5V in MAX 14.5mohm 3.6mohm C PR305 10K_0402_1% af PR308 0_0402_5% PC310 0.033U_0402_16V7~D PC314 220P_0402_50V8J~D S5_1.5V PC300 VTT BOOT VLDOIN VTTSNS D +0.75VSP PR306 200K_0402_5% VDD PC311 1U_0603_10V6K 11 VDDP PGOOD om PC309 12 1U_0603_10V6K VDD_1.5V RT8207MZQW _W QFN20_3X3 10 UGATE CS 17 16 PHASE 13 21 B PGND PR304 5.1_0603_5% +5VALW SUSP# 1.5VP TDC 14A Peak Current 20A OCP current 24A TYP H/S Rds(on) :10mohm , L/S Rds(on) :3mohm , 14 CS_1.5V PAD VTTGND PC306 10U_0805_6.3V6M SIR472DP-T1-GE3_POWERPAK8-5~D PQ300 PC305 2200P_0402_50V7K SYSON LGATE c @ PR302 7.15K_0402_1% 15 PU300 ix C DL_1.5V 2 SW _1.5V PC308 330U_2.5V_M SIR818DP-T1-GE3_POWERPAK8-5~D PQ302 + PC304 0.22U_0603_10V7K @ @ DH_1.5V 680P_0603_50V7K 4.7_1206_5% PC312 PR303 SNUB_1.5V PL300 0.68UH_PCMC063T-R68MN_15.5A_20% 2 PC303 0.1U_0402_25V6 PC302 4.7U_0805_25V6-K PC301 4.7U_0805_25V6-K JUMP_43X118 BOOT_1.5V PR301 2.2_0603_5% 1.5V_B+ D +1.5V +1.5V PAD-OPEN1x1m @ PJP302 2 1 SIR818DP-T1-GE3_POWERPAK8-5~D PQ301 B+ PC307 10U_0805_6.3V6M PJP301 VLDOIN_1.5V c n @ +0.75VSP PJP300 B +0.75VS A ww c h PAD-OPEN 3x3m A Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Issued Date Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-1.5V/0.75VSP Size Document Number Rev 1.0 LA-8241P Date: W ednesday, February 01, 2012 Sheet 48 of 56 VID [0] 0 1 D VID[1] 1 VCCSA Vout 0.9V 0.8V 0.725V 0.675V output voltage adjustable network PC600 680P_0402_50V7K c SNUB_+1.5VP VID1 EN VID0 +VCCSA_EN +3VS PR606 100_0402_5% PR602 0_0402_5% af 0_0402_5% PR601 +V1.05S_VCCP_PWRGOOD C +VCCSAP PC609 22U_0805_6.3VAM VOUT PR605 100K_0402_5% PC607 22U_0805_6.3VAM PG 1K_0402_5% PR603 LX FB PC606 22U_0805_6.3VAM SVIN SA_PGOOD ix PC604 22U_0805_6.3VAM 10 LX PL600 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% +VCCSA_PHASE @ PC601 0.1U_0402_10V7K PC610 68P_0402_50V8J +VCCSAP_FB PVIN 1K_0402_5% PR604 11 GND PC612 10U_0805_6.3V6M 2 PC611 10U_0805_6.3V6M +VCCSA_PWR_SRC 13 HCB1608KF-121T30_0603 2200P_0402_50V7K PC605 +3VALW 0.1U_0603_25V7K PC603 C D +VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A PR600 4.7_1206_5% PL601 PU600 SY8037BDCC_DFN12_3X3 12 PVIN LX c n om VCCSA_VID0 VCCSA_SENSE VCCSA_VID1 in The 1k PD on the VCCSA VIDs are empty These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability B @ PJP601 +VCCSAP +VCCSA PAD-OPEN 4x4m c h B A ww A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-VCC_SAP Size Document Number Rev 1.0 LA-8241P Date: Wednesday, February 01, 2012 Sheet 49 of 56 5.11K_0402_1% PC708 165K_0402_1% CSREFA 1500P_0402_50V7K PR711 SWN1A c n c ix PR728 0_0402_5% LG1 HG1 PR730 BST1_1 1 2.2_0603_5% PC721 0.22U_0603_10V7K SW1 CSP2A +5VS DROOP PC734 24.9K_0402_1% CSREF 1000P_0402_50V7K IMVP_IMON PUT COLSE TO VCORE Phase Inductor 6.98K_0402_1% SWN2 CSP3 B TSENSE CSREF CSSUM PC733 1500P_0402_50V7K @ PH702 100K_0402_1%_TSM0B104F4251RZ CSREF PC735 560P_0402_50V7K PR748 130K_0603_1% SWN1 PR750 130K_0603_1% SWN2 PUT COLSE TO VCORE HOT SPOT PR751 2NTC_PH201 PR752 75K_0402_1% 165K_0402_1% PH703 220K_0402_5%_ERTJ0EV224J A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SWN1 PR745 PR744 6.98K_0402_1% CSREF PC730 1000P_0402_50V7K 8.25K_0402_1% CSP1 PC736 PR766 13.3K_0402_1% PC726 0.047U_0402_16V7K TSENSE PC723 1U_0402_16V7K CSP1 CSP2 CSP3 PR749 @ PR736 0_0402_5% Option for phase CPU PR740 CSP2 Date: C Option for phase GFX +5VS PR733 43.2K_0402_1% 806_0402_1% ww A SW2 2.2U_0603_10V7K 2 1K_0402_1% 100K_0402_1%_TSM0B104F4251RZ PUT COLSE TO V_GT HOT SPOT PR767 13.3K_0402_1% c h PC732 PR754 PC719 PC731 0.047U_0402_16V7K PR747 0.033U_0603_16V7 PC729 2FB_CPU3 10_0402_1% 0.033U_0603_16V7 PR746 FB_CPU2 CSCOMP BST1 PH701 +5VS PC718 PR723 BST2_1 1 2.2_0603_5% 0.22U_0603_10V7K PR742 PC728 1COMP_CPU1 6.34K_0402_1% 1800P_0402_50V7K CSCOMP PR741 PC727 2FB_CPU1 49.9_0402_1% 560P_0402_50V7K 8.06K_0402_1% LG2 af PC725 10P_0402_50V8J TRBST# HG2 6132P_VCCP PR739 1K_0402_1% PR743 BST2 DRVEN 1 B ILIM_CPU DROOP PC722 1000P_0402_50V7K VSP PR738 12.7K_0402_1% PR737 0_0402_5% VSN 1U_0402_16V7K PR735 0_0402_5% VCCSENSE 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 TSENSEA 6132_PWMA in VGATE TRBST# FB_CPU COMP_CPU VSSSENSE CSP2A CSP1A TSENSEA PAD VSNA VSPA DIFFA TRBSTA# FBA COMPA IOUTA ILIMA DROOPA CSCOMPA CSSUMA CSREFA CSP2A CSP1A TSNSA VR_HOT# SWN1A CSREFA 1000P_0402_50V7K 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PR732 10K_0402_5% 6.98K_0402_1% PC705 DROOPA PR717 28K_0402_1% TRBST# FB COMP IOUT ILIM DROOP CSCOMP CSSUM CSREF CSP3 CSP2 CSP1 TSNS DRVEN PWM PC720 1 PR731 75_0402_1% 1U_0402_16V7K VCC PWMA VDDBP BSTA VRDYA HGA EN SWA SDIO LGA ALERT# BST2 SCLK HG2 VBOOT NCP6132BMNR2G_QFN60_7X7 SW2 ROSC LG2 VRMP PVCC VRHOT# PGND VRDY LG1 VSN SW1 VSP HG1 DIFF BST1 0.01U_0402_25V7K +VCCP PC713 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 1U_0402_16V7K PR722 54.9_0402_1% PR721 VR_SVID_DAT VR_SVID_ALRT# VR_SVID_CLK PR712 PC710 1000P_0402_50V7K PU700 2.2U_0603_10V7K 6132_VDDBP PR720 VR_RDYA VR_ON_CPU VR_ON PC717 0_0402_5% VR_SVID_DAT1 VR_SVID_ALRT# PR726 PR724 VR_SVID_CLK 95.3K_0402_1% 0_0402_5% VBOOT 10K_0402_1% ROSC_CPU PR725 2VR_SVID_DAT1 VRMP CPU_B+ 10 VR_HOT# 11 PR727 1K_0402_1% VGATE 12 13 14 +3VS DIFF_CPU 15 130_0402_1% 1U_0402_16V7K PC716 6132_VDDBP 2.2U_0603_10V7K PR718 2_0603_5% PC714 6132_VCC +5VS VR_RDYA +VCCP PC753 CSP1A PC709 0.047U_0402_16V7K CSREFA CSSUMA +5VS PR716 @ 10K_0402_1% C DIFFA TRBSTA# FBA COMPA IMONA ILIMA DROOPA +3VS PC711 1000P_0402_50V7K PR765 0_0402_5% VSS_AXG_SENSE 1PR713 15.8K_0402_1% CSCOMPA 69.8K_0603_1% PR753 0_0402_5% VCC_AXG_SENSE 1K_0402_1% COMPA1 CSCOMPA 1K_0402_1% PR706 PR709 PR705 220K_0402_5%_ERTJ0EV224J NTC_PH203 D 560P_0402_50V7K PR708 2 FBA2 10_0402_1% PC707 om PC706 PR714 10P_0402_50V8J PR707 8.25K_0402_1% 24.9K_0402_1% 806_0402_1% PUT COLSE TO GT Inductor PH700 8.06K_0402_1% 1 PR703 FBA1 PC704 0.033U_0603_16V7 1 PC702 PR702 TRBSTA# 1U_0402_16V7K PR701 2 PC701 D PR704 75K_0402_1% PC700 0.033U_0603_16V7 FBA3 2 PC703 PR700 10_0402_1% 680P_0402_50V7K 1200P_0402_50V7K CPU Core Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet 50 of 56 c n VCC_core TDC 32A Peak Current 53A OCP current 65 Load line -1.9mV/A FSW=300kHz DCR 1.1mohm +/-5% TYP H/S Rds(on) :10mohm , L/S Rds(on) :3mohm , CPU_B+ 1SNUB_CPU1 PR757 V1N_CPU 10_0402_1% SWN1 PC745 @ 680P_0402_50V7K VCC PR761 0_0402_5% DRVL NCP5911MNTBG_DFN8_2X2 GFX_LG PC751 2.2U_0603_10V7K PC749 4.7U_0805_25V6-K PC748 4.7U_0805_25V6-K PC747 4.7U_0805_25V6-K ww A SW GND PR758 10_0402_1% CSREF SWN2 PC746 @ 680P_0402_50V7K +VCC_GFXCORE_AXG TDC 21.5A Peak Current 33A OCP current 40A Load line -3.9mV/A FSW=300kHz DCR 1.1mohm +/-5% TYP H/S Rds(on) :10mohm , L/S Rds(on) :3mohm , B MAX 14.5mohm 3.6mohm +VCC_GFXCORE_AXG Issued Date PR764 CSREFA 10_0402_1% SWN1A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-VCC_SAP Size Document Number Rev 1.0 LA-8241P Date: C V2N_CPU 1 JUMP_43X118 EN 1VCC_GFX @ 4.7_1206_5% 2 PR756 @ 4.7_1206_5% PJP701 PL704 0.36UH_FDU1040J-H-R36M=P3_33A_20% GFX_SW @ B+ @ @ 680P_0402_50V7K +5VS PQ706 SIR818DP-T1-GE3_POWERPAK8-5~D PC752 PR762 SNUB_GFX1 DRVH DRVEN 3 1EN_GFX c h PR760 DRVEN 2K_0402_1% PWM FLAG BST PC750 0.22U_0603_10V7K PU701 6132_PWMA af GFX_HG PQ704 SIR472DP-T1-GE3_POWERPAK8-5~D GFX_BST_1 2.2_0603_5% PQ705 SIR818DP-T1-GE3_POWERPAK8-5~D 2 PR759 GFX_BST in B LG2 CSREF ix PQ707 SIR818DP-T1-GE3_POWERPAK8-5~D QC-SV 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=32A R_LL=1.9m ohm OCP~65A PQ702 SIR818DP-T1-GE3_POWERPAK8-5~D LG1 PR755 @ 4.7_1206_5% @ SW2 +VCC_CORE CPU_B+ SNUB_CPU2 D PL702 0.36UH_FDU1040J-H-R36M=P3_33A_20% 1 MAX 14.5mohm 3.6mohm 4 HG2 SW1 PC742 4.7U_0805_25V6-K om PC741 4.7U_0805_25V6-K PC740 4.7U_0805_25V6-K PC739 4.7U_0805_25V6-K PL701 0.36UH_FDU1040J-H-R36M=P3_33A_20% +VCC_CORE PQ708 SIR818DP-T1-GE3_POWERPAK8-5~D C c HG1 PQ700 SIR472DP-T1-GE3_POWERPAK8-5~D CPU_B+ + PQ701 SIR472DP-T1-GE3_POWERPAK8-5~D PQ703 SIR818DP-T1-GE3_POWERPAK8-5~D + PC724 PC712 JUMP_43X118 1 100U_25V_M~D PC744 4.7U_0805_25V6-K PJP700 100U_25V_M~D @ PC743 4.7U_0805_25V6-K B+ D Wednesday, February 01, 2012 Sheet 51 of 56 VCCSENSE_VGA @ PJP800 2 1 EN af 0 0.85V 1 0.825V 1 1 0.8V PC804 VGA@ 4.7U_0805_25V6-K PC803 VGA@ 4.7U_0805_25V6-K PC802 VGA@ 2200P_0402_50V7K PC801 VGA@ 0.1U_0402_25V6 1 PC812 VGA@ 10U_0805_6.3V6M PC811 VGA@ 10U_0805_6.3V6M PC810 VGA@ 10U_0805_6.3V6M 2 VGA@ PR827 10K_0402_1% PC825 22P_0402_50V8J PJP804 +VGA_PCIEP 2 @ +VGA_PCIEP Thames XT +1.0VGS VGA@ PC818 22U_0805_6.3VAM B VGA@ PC824 22U_0805_6.3VAM VGA@ PC820 22U_0805_6.3VAM LX PR825 VGA@ 5.9K_0402_1% VGA@ 2 PG PC822 VGA@ FB_PCIE VGA@ PC821 22U_0805_6.3VAM @ PR828 47K_0402_5% SY8036LDBC_DFN10_3x3 VGA@ PR829 4.7_1206_5% 2EN_PCIE 200K_0402_5% SS TP 2 FB SNUB_PCIE 0.875V EN 1 SVIN LX VGA@ PC826 680P_0603_50V7K VGA@ PR826 VGA@ PL801 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% +VGA_PCIEP 0.9V C LX_PCIE 0.925V 1000P_0603_50V7K 1 PVIN 0.1U_0402_10V7K 0 LX VGA@ PVIN 0.95V PXS_PWREN VGA@ PC819 22U_0805_6.3VAM 10 11 PU800 PCIE_B+ 1 1 Core Voltage Level 1K_0402_5% VGA@ PR837 GPU_VID2 GPU_VID0 c h GPU_VID1 VGA@ PR836 1K_0402_5% VGA@ ww A JUMP_43X79 1U_0402_16V7K Chelsea Pro PC806 + VGA@ EN_VGA_CORE GPU_VID0 GPU_VID1 B +VGA_PCIE TDC 3.6A Peak Current 5.2A OCP current 6A @ in PJP805 +3VALW PX_MODE PR800 0_0402_5% 2 MAX 14.5mohm 3.6mohm PC823 0.1U_0402_10V7K VGA@ PR804 2.2K_0402_5% 2 VGA@ 10K_0402_1% VGA_PW RGD PR801 VGA@ +3VS 2 +VGA_CORE TDC 22A Peak Current 30A OCP current 36A FSW=350kHz DCR 1.1mohm +/-5% TYP H/S Rds(on) :10mohm , L/S Rds(on) :3mohm , @ VGA@ PC830 0.1U_0402_10V7K 2 G PR803 VGA@ 10K_0402_1% GPU_VID2 @ PC805 VGA@ 0.1U_0603_25V7K + ix D 0_0402_5%~D PR839 S PR838 0_0402_5%~D PQ804 SI2301CDS-T1-GE3_SOT23-3 VGA@ PR802 VGA@ 2.2_0603_5% 10 VID1 PR834 VGA@ 2.49K_0402_1% 11 BST_VGA_CORE PC813 @ PC809 VGA@ 470U_D2_2VM_R4.5M BST PC800 VGA@ 470U_D2_2VM_R4.5M V0 om SW _VGA_CORE PR808 @ 4.7_1206_5% 12 +VGA_CORE SW VGA@ PQ802 SIR818DP-T1-GE3_POWERPAK8-5~D V1 4 UG_VGA_CORE TPS51518RUKR_QFN20_3X3 D VGA@ PL800 0.36UH_FDU1040J-H-R36M=P3_33A_20% c 13 V2 +5VALW LG_VGA_CORE VGA@ PQ801 SIR818DP-T1-GE3_POWERPAK8-5~D VGA_CORE_5V DRVL 14 15 DRVH 1U_0603_10V6K PC807 VGA@ V5IN VGA@ PQ800 SIR472DP-T1-GE3_POWERPAK8-5~D 2 16 GND MODE 17 18 TRIP VSNS SLEW 20 PC814 4700P_0402_25V7K 19 21 V3 VREF C PR807 43K_0402_1% GSNS VID0 PR833 VGA@ 105K_0402_1% 1 G PGOOD PU801 PR811 VGA@ 5.11K_0402_1% D S VGA@ PAD PQ803 2N7002KW _SOT323-3 VGA@ PR815 VGA@ 76.8K_0402_1% PR814 VGA@ 2.49K_0402_1% PR813 VGA@ 5.11K_0402_1% PR810 VGA@ 5.11K_0402_1% VGA@ D c n VGA@ B+ JUMP_43X118 0_0402_5% PR830 VGA@ PC829 10P_0402_50V8J 10P_0402_50V8J VGA@ PR835 0_0402_5% VSSSENSE_VGA PC828 VGA@ VGA_CORE_B+ Chelsea Pro VGA_PCIE 1.0V 0.95V PR825 6.81K 5.9K A JUMP_43X79 0.775V 2012/01/17 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2013/01/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: VGA_COREP Document Number Rev 1.0 LA-8241P W ednesday, February 01, 2012 Sheet 52 of 56 B C D c n A +VDDCI TDC 2.8A Peak Current 4A OCP current 6A 1 2 4.99K_0402_1% VGA@ PC1005 22U_0805_6.3V6M +VDDCIP om 1 VGA@ PR1003 VGA@ PC1003 22U_0805_6.3V6M FB=0.6Volt VGA@ PC1000 22P_0402_50V8J 1 PR1001 VGA@ 4.7_1206_5% SY8036LDBC_DFN10_3x3 PR1006 VGA@ 10_0402_5% PR1004 c VGA@ FB_VDDCIP 2 PR1005 1M_0402_5% @ VGA@ PR1002 10K_0402_5% LX_VDDCIP VGA@ PC1002 680P_0603_50V7K PC1004 0.1U_0402_10V7K 11 TP EN FB LX SVIN PG EN_VDDCIP LX SS PVIN LX VGA@ PC827 0.1U_0402_10V7K PVIN 10 PC1001 VGA@ 22U_0805_6.3V6M JUMP_43X79 PX_MODE PL1000 VGA@ 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% PU1000 VGA@ 2 PJ1000 @ 1 +3VALW VDDCI_SEN 0_0402_5% +3VGS VGA@ PR1008 VGA@ 10K_0402_5% D VDDCI_VID PR1010 @ 100K_0402_5% @ PC1006 4700P_0402_25V7K VDDCI_VID in High 1V Low 0.9V @ PJ1001 +VDDCIP +VDDCI PAD-OPEN 4x4m c h PQ1000 VGA@ 2N7002W -T/R7_SOT323-3 af S G PR1009 VGA@ 10K_0402_5% 1 ix VGA@ PR1000 10K_0402_1% VGA@ PR1007 29.4K_0402_1% ww 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Deciphered Date 2013/01/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C +VDDCIP Document Number Rev 1.0 LA-8241P W ednesday, February 01, 2012 D Sheet 53 of 56 +VCC_CORE +VCC_CORE PC1201 10U_0805_6.3VAM PC1202 10U_0805_6.3VAM PC1203 10U_0805_6.3VAM Below is 458544_CRV_PDDG_0.5 Table 5-8 +VCC_GFXCORE_AXG PC1204 10U_0805_6.3VAM PC1205 10U_0805_6.3VAM +VCC_GFXCORE_AXG D 2 2 + 2 PC1249 22U_0805_6.3V6M PC1250 22U_0805_6.3V6M PC1251 22U_0805_6.3V6M PC1252 22U_0805_6.3V6M PC1253 22U_0805_6.3V6M PC1256 22U_0805_6.3V6M +VCC_CORE + 330U_D2_2VM_R9M 1 + + PC1261 @ 330U_D2_2V_Y 2 A PC1258 330U_D2_2V_Y + PC1259 330U_D2_2VM_R9M PC1262 @ 330U_D2_2V_Y + C + + + PC1260 330U_D2_2V_Y in PC1257 2 B c h + ww 1 af PC1247 330U_D2_2V_Y ix 2 PC1255 330U_D2_2VM_R9M + 330U_D2_2V_Y C B c PC1246 PC1245 22U_0805_6.3V6M PC1242 22U_0805_6.3V6M PC1233 22U_0805_6.3V6M PC1254 330U_D2_2VM_R9M PC1241 22U_0805_6.3V6M PC1244 22U_0805_6.3V6M 2 PC1232 22U_0805_6.3V6M PC1240 22U_0805_6.3V6M PC1231 22U_0805_6.3V6M 2 PC1200 330U_D2_2VM_R9M PC1239 22U_0805_6.3V6M PC1243 22U_0805_6.3V6M 2 PC1230 22U_0805_6.3V6M PC1238 22U_0805_6.3V6M 2 PC1229 22U_0805_6.3V6M 2 1 D +VCCP +VCCP 1 PC1228 22U_0805_6.3V6M x 22 µF (0805) x (0805) no-stuff sites PC1227 22U_0805_6.3V6M Socket Top PC1226 22U_0805_6.3V6M x 22 µF (0805) x (0805) no-stuff sites PC1225 22U_0805_6.3V6M PC1223 22U_0805_6.3V6M PC1237 22U_0805_6.3V6M PC1222 22U_0805_6.3V6M PC1236 22U_0805_6.3V6M PC1221 22U_0805_6.3V6M PC1235 22U_0805_6.3V6M PC1220 22U_0805_6.3V6M PC1234 22U_0805_6.3V6M PC1219 22U_0805_6.3V6M PC1224 22U_0805_6.3V6M 1 Socket Bottom om PC1218 22U_0805_6.3V6M PC1217 22U_0805_6.3V6M +VCC_CORE PC1216 22U_0805_6.3V6M PC1210 10U_0805_6.3VAM PC1215 22U_0805_6.3V6M PC1209 10U_0805_6.3VAM PC1214 22U_0805_6.3V6M PC1208 10U_0805_6.3VAM PC1213 22U_0805_6.3V6M PC1207 10U_0805_6.3VAM PC1212 22U_0805_6.3V6M PC1206 10U_0805_6.3VAM PC1211 22U_0805_6.3V6M 1 c n A Compal Electronics, Inc Compal Secret Data Security Classification 2012/01/17 Issued Date Deciphered Date 2013/01/16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR DECOUPLING Size Document Number Rev 1.0 LA-8241P Date: W ednesday, February 01, 2012 Sheet 54 of 56 CPU OTP c n Power block Page 43 Turn Off D B+ +3VALWP: TDC:5.4A +5VALWP: TDC:5.6A RT8205LZQW(2) WQFN CHARGER CC:0A~3.52A CV:13.3V(6cell) ISL88731CHRTZ-T Page 44 C +VCCP: TDC:11A TPS51212DSCR ix Battery af SYSON Page 48 VR_ON ww +VCC_GFXCORE_AXG TDC: 21.5A NCP6132BMNR2G VR_ON A +V1.05S_VCCP_PWRGOOD Page 49 B c h +VCC_CORE TDC: 32A NCP6132BMNR2G Page 52 in B C SUSP# Page 47 +VCCSAP: TDC:4.2A SY8037DCC +VGA_CORE TDC:23.4A TPS51518RUKR SUSP# Page 46 +1.5V/+0.75VSP: TDC:14A/0.7A RT8207MZQW PX_MODE Always Page 45 c +1.8VSP: TDC:2.6A SY8033BDBC om Input Switch Page 44 DC IN D PXS_PWREN +VGA_PCIEP: TDC:3.5A SY8036LDBC Page 52 +VDDCIP: TDC:2.8A SY8036LDBC Page 53 PX_MODE Page 50/51 A Page 50/51 2012/1/17 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/1/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PROCESSOR DECOUPLING Document Number Rev 0.2 LA-8241P Wednesday, February 01, 2012 Sheet 55 of 56 Version Change List ( P I R List ) Item Page# Title Date Request Owner Page c n Issue Description 44 Charger 11/12/08 Frank Change PR113 for 45 3.3VALWP/5VALWP 11/12/08 Frank 53 +VDDCIP 11/12/08 Frank Solution Description temperature and voltage test Rev Change PR113 from 316k to 309k for Charger IC BQ24747RHDR Remove PR132 X00 Design change Change PC219 from 1uF to 4.7uF X00 Fine tune time sequence Change PR1002 from 100k to 0ohm Remove PR1005 and PC1004 X00 D c om D C in af ix C B A ww c h B A 2012/01/17 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/01/16 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR-PIR Document Number Rev 1.0 LA-8241P Wednesday, February 01, 2012 Sheet 56 of 56 ... DESTINATION SATA0 HDD Lane 10/100/1G LAN SATA1 SSD Lane MINI CARD-1 (WLAN) SATA2 ODD Lane Express Card SATA3 None Lane None SATA4 None Lane None SATA5 None Lane None Lane None Lane None DESTINATION... CH21 CH22 PCIE_PRX_LANTX_N1 PCIE_PRX_LANTX_P1 PCIE_PTX_LANRX_N1_C PCIE_PTX_LANRX_P1_C Controller PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2 0.1U_0402_10V7K~D... CLK_PCIE_WLAN# CLK_PCIE_WLAN +3VS WLAN_CLKREQ# RH67 RH68 RH69 BG36 BJ36 AV34 AU34 SMBALERT# H14 c WLAN (Mini Card 1) -> CLK_PCIE_LAN# CLK_PCIE_LAN +3V_PCH LAN_CLKREQ#