128 LA 4111p

A B C D E 1 Compal confidential 2 Schematics Document Mobile AMD S1G2 CPU with ATI RS780M(NB) & SB700(SB) core logic 3 2008-03-07 REV:0.4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Cover Sheet Rev 0.4 LA-4111P Friday, March 07, 2008 Sheet E of 54 A B C D E Compal Confidential Consumer AMD 14" UMA - Ripley (JBL20) Thermal Sensor ADM1032ARMZ Accelerometer ST LIS302DLTR AMD S1G2 CPU Page Page 30 Fan conn 72QFN DDR2-SO-DIMM X2 DDR2 800MHz 1.8V BANK 0, 1, 2, Dual Channel 638-PIN uFCPGA 638 Clock Generator SLG8SP626VTR Page 8, Page 15 Page Page 4, 5, 6, Side-Port DDR2 SDRAM 256Mbits(16Mbx16) Page 12 Hyper Transport Link 16X16 USB conn x2 LVDS Panel Interface Page ATI RS780M 17 CRT BT Conn Page 10, 11, 12, 13, 14 Page 16 DDR2 400MHz HDMI 4X PCI-E USB conn x1 PCI-E BUS*5 Azalia (HDA I/F) CardReader JMicron JMB385-LGEZ0A Realtek 8102E(10/100M) Page 27 Mini-Card*2 WLAN & WWAN Page 25 CardReader Socket 26 Page 31 Page 17 SATA Slave FingerPrinter AES1610 USBx1 page 35 SATA Slave Page 19, 20, 21, 22, 23 daughter board daughter board Page 26 MDC V1.5 daughter board SATA Master-2 Express Card Page 26 Page 31 USB WebCam SATA Master-1 ATI SB700 daughter board Mini-Card WWAN Page 14" Only USB2.0 X12 A-Link Express II Page 18 Page 31 LPC BUS RJ45/11 CONN daughter board Page 34 Audio CKT Page 25 Page 27 TPA6017A2 Page 28 KBC ENE KB926 AMP & Audio Jack Codec_IDT9271B7 Page 29 SATA HDD Connector Page 24 Page 33 Docking CONN *RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *S-VIDEO OUT *SPDIF *Headphone/Line Out L/R *Stereo Mic L/R *Volume Control *Consumer IR *USB x1 *DC JACK SATA ODD Connector LED Page 24 Touch Pad CONN P41 Int.KBD Page 34 Page 33 Page 19 SPI Consumer IR Page 34 SPI ROM SST25VF080B Page 32 Page 31 Power OK CKT P35 Power On/Off CKT P35 Compal Secret Data Security Classification 2007/08/02 Issued Date DC/DC Interface CKT Page 35 Multi-Bay HDD/ODD Option Connector Page 24 14" UMA PA Only e-SATA Connector RTC CKT 2008/08/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Page 36 Date: A Compal Electronics, Inc B C D Block Diagram Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 A B Voltage Rails O MEANS ON C X MEANS OFF D E Symbol Note : 1 : means Digital Ground +5VS +3VS : means Analog Ground +1.5VS power plane +5VALW Layout Notes +0.9V L +VCCP Please see VGA@ as no install No support RX780M +CPU_CORE +1.8V +B +3VALW +VGA_CORE +2.5VS : Question Area Mark.(Wait check) +1.8VS State +1.2VS "*" as default BOM setting *PA@ : means install when Ripley PA PR@ : means install when Ripley PR RM@ : means install when Rachman *RP@ : means install when Ripley SIDE@ : means install when SidePort support *CY@ : means install when Function Board-Cypress *ENE@ : means install when Function Board-ENE @ : means just reserve , no build 45@ : Install when 45 level Assy +0.9VGA S0 O O O O S1 O O O O S3 O O O X S5 S4/AC O O X X S5 S4/ Battery only O X X X S5 S4/AC & Battery don't exist X X X X SMBUS Control Table SOURCE SMB_EC_CK1 I2C / SMBUS ADDRESSING SMB_EC_DA1 SMB_EC_CK2 DEVICE HEX ADDRESS DDR SO-DIMM A0 10100000 I2C_CLK DDR SO-DIMM A4 10100100 I2C_DATA CLOCK GENERATOR (EXT.) D2 11010010 DDC_CLK0 SMB_EC_DA2 DDC_DATA0 DDC_CLK1 EC SM Bus1 address Device Smart Battery 24C16 HEX Address 16H 0001 011X b A0H 1010 000X b EC SM Bus2 address Device HEX Address CPU 98H 1001 100X b ADI1032-2 CPU 9AH 1001 101X b DDC_DATA1 SCL0 KB926 KB926 RS780M RS780M RS780M SB700 SDA0 SCL1 SB700 SDA1 SCL2 SB700 SDA2 SCL3 SB700 SDA3 X X X X X X X X X BATT V X X X X X X X X SERIAL EEPROM V X X X X X X X X THERMAL SENSOR CPU & ADM1032 SODIMM I / II VCPU V ADM1032 X X X X X X X X X X X X V X X X CLK CHIP X X X X X V X X X Compal Secret Data Security Classification 2007/08/02 Issued Date INVERTER 2008/08/02 Deciphered Date Title MINI CARD Slot X X X X X X V X X Date: B C D HDMI X X V X X X X X X X X X V X X X X X G-Sensor X X X X X X X V X Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A LCD Notes List Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 A B C D E 1 VLDT CAP +1.2V_HT 250 mil 10 H_CADIP[0 15] 10 H_CADIN[0 15] H_CADIP[0 15] H_CADOP[0 15] H_CADIN[0 15] H_CADON[0 15] H_CADOP[0 15] H_CADON[0 15] 10 C1 4.7U_0805_10V4Z 10 1 C2 4.7U_0805_10V4Z C3 0.22U_0603_16V4Z C4 0.22U_0603_16V4Z C5 180P_0402_50V8J C6 180P_0402_50V8J Near CPU Socket +1.2V_HT JCPUA E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 J3 J2 J5 K5 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 N1 P1 P3 P4 10 10 10 10 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 AE2 +VLDT_B C7 AE3 AE4 AE5 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 Y1 W1 Y4 Y3 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 R2 R3 T5 R5 4.7U_0805_10V4Z If VLDT is connected only on one side, one 4.7uF cap should be added to the island side H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 +5VS H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 PWM Fan Control circuit 10 10 10 10 JP2 VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 10 10 10 10 HT LINK D1 D2 D3 D4 D1 CH751H-40PT_SOD323-2 10 10 10 10 C8 4.7U_0805_10V4Z C9 0.1U_0402_16V4Z 2 VLDT=500mA GND GND 1 Athlon 64 S1 Processor Socket ACES_88231-02001 CONN@ +VCC_FAN FOX_PZ6382A-284S-41F_GRIFFIN CONN@ D Q1 @ D2 G FAN_PWM RLZ5.1B_LL34 S SI3456BDV-T1-E3_TSOP6 33 9/20 SP07000DM00/SP07000EQ00 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc AMD CPU S1G2 HT I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 A B C D E Processor DDR2 Memory Interface PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH 1 DDR_A_CLK#0 C10 1.5P_0402_50V9C DDR_A_CLK1 DDR_A_CLK#1 C11 1.5P_0402_50V9C +1.8V DDR_B_CLK0 R1 C14 1.5P_0402_50V9C 1K_0402_1% DDR_B_CLK#0 2 R2 C15 1.5P_0402_50V9C C12 1K_0402_1% DDR_B_CLK#1 +MCH_REF DDR_B_CLK1 C13 2 1000P_0402_25V8J 0.1U_0402_16V4Z +0.9V +0.9V JCPUB Place them close to CPU within 1" +1.8V R4 1 R3 39.2_0402_1% 2 39.2_0402_1% DDR_A_ODT0 DDR_A_ODT1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_MA[15 0] DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# VTT1 VTT2 VTT3 VTT4 AF10 AE10 MEMZP MEMZN MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9 H16 RSVD_M1 T19 V22 U21 V19 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# T20 U19 U20 V20 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 DDR_CKE0_DIMMA DDR_CKE1_DIMMA J22 J20 MA_CKE0 MA_CKE1 T2 8 D10 C10 B10 AD10 PAD DDR_A_ODT0 DDR_A_ODT1 W10 AC10 AB10 AA10 A10 VTT_SENSE Y10 MEMVREF W17 VTT_SENSE RSVD_M2 B18 MB0_ODT0 MB0_ODT1 MB1_ODT0 W26 W23 Y26 DDR_B_ODT0 DDR_B_ODT1 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 V26 W25 U22 DDR_CS0_DIMMB# DDR_CS1_DIMMB# MB_CKE0 MB_CKE1 J25 H26 DDR_CKE0_DIMMB DDR_CKE1_DIMMB N19 N20 E16 F16 Y16 AA16 P19 P20 MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4 MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4 P22 R22 A17 A18 AF18 AF17 R26 R25 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 R20 R23 J21 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 R24 U26 J26 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# R19 T22 T24 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L U25 U24 U23 PAD T1 PAD T3 +MCH_REF DDR_B_ODT0 DDR_B_ODT1 DDR_CS0_DIMMB# DDR_CS1_DIMMB# DDR_CKE0_DIMMB DDR_CKE1_DIMMB DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 9 9 DDR_B_DM[7 0] DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_MA[15 0] 9 9 9 9 9 9 9 9 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7 MEM:DATA DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7 C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 DDR_A_D[63 0] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 E12 C15 E19 F24 AC24 Y19 AB16 Y13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DM[7 0] DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 8 8 8 8 8 8 8 8 FOX_PZ6382A-284S-41F_GRIFFIN FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket JCPUC DDR_B_D[63 0] DDR_A_CLK0 Athlon 64 S1 Processor Socket CONN@ CONN@ Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc AMD CPU S1G2 DDRII I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 B D +2.5VDDA VDDA=300mA L1 3300P_0402_50V7K FBM_L11_201209_300L_0805 1 1 + 4.7U_0805_10V4Z C17 C18 C19 0.22U_0603_16V4Z 2 2 +2.5VS E +1.8V R10 1 R5 02/27 Change net name to EN0 10K_0402_5% 300_0402_5% @ R6 B @ C16 100U_D2_10VM 02/15 Reserve C16 C A C E CPU_THERMTRIP#_R Q3 PMBT3904_SOT23 R16 R7 0_0402_5% EN0 0_0402_5% 0_0402_5% 37,39 H_THERMTRIP#_EC 33 H_THERMTRIP# 20 JCPUD LDT_RST# H_PWRGD_CPU LDT_STOP# CPU_LDT_REQ# B7 A7 F10 C6 RESET_L PWROK LDTSTOP_L LDTREQ_L CPU_SIC CPU_SID AF4 AF5 AE6 SIC SID ALERT_L R6 P6 HT_REF0 HT_REF1 R8 169_0402_1% 0718 Silego 216 ohm 15 CLK_CPU_BCLK# C21 3900P_0402_50V7K Address:100_1100 R13 R14 +1.2V_HT 1 44.2_0402_1% CPU_HTREF0 44.2_0402_1% CPU_HTREF1 2 R15 300_0402_5% 19 LDT_RST# VDD1_FB_H VDD1_FB_L VDDNB_FB_H VDDNB_FB_L H6 G6 VDD_NB_FB_H VDD_NB_FB_L PAD CPU_TEST23_TSTUPD AD7 TEST23 H10 G9 TEST18 TEST19 CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 T9 PAD T11 PAD CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST27_SINGLECHAIN R25 E9 E8 TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 C2 AA6 TEST9 TEST6 A3 A5 B3 B5 C1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 0_0402_5% @ R814 CPU_SVC CPU_SVD R22 1 R23 1K_0402_5% 2 1K_0402_5% DBREQ_L E10 CPU_DBREQ# TDO AE9 CPU_TDO +1.8V sense no support +CPU_CORE_NB VDD_NB_FB_H 43 VDD_NB_FB_L 43 VDD_NB_FB_H VDD_NB_FB_L R484 10_0402_5% 2 R485 10_0402_5% Close to CPU J7 H8 CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N TEST17 TEST16 TEST15 TEST14 D7 E7 F7 C7 CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0 TEST7 TEST10 C3 K8 TEST8 C4 TEST29_H TEST29_L C9 C8 PAD PAD PAD PAD PAD PAD CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N T5 T6 route as differential as short as possible testpoint under package T7 T8 T10 T12 PAD PAD T13 T14 H18 H19 AA7 D5 C5 RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 C23 G +1.8V 2.09V for Gate 1 FOX_PZ6382A-284S-41F_GRIFFIN CONN@ 34.8K_0402_1%~N 20K_0402_5% 0_0402_5% +1.8V T42 T43 TEST28_H TEST28_L TEST25_H TEST25_L AB8 AF7 AE7 AE8 AC8 AF8 @ R59 0718 AMD > 1K ohm CPU_VDD1_FB_H Y6 CPU_VDD1_FB_L AB6 DBRDY TMS TCK TRST_L TDI @ MMBT3904_NL_SOT23-3 Q2 H_PROCHOT# 19 R17 THERMDC_CPU THERMDA_CPU 43 CPU_VDD1_FB_H 43 CPU_VDD1_FB_L @ C939 0.1U_0402_16V4Z 2 +3VS H_PWRGD_CPU W7 W8 PAD PAD +1.8VS 19 H_PWRGD_CPU THERMDC THERMDA W9 Y9 G10 AA9 AC9 AD9 AF9 @ 300_0402_5% VDDIO_FB_H VDDIO_FB_L R175 CPU_THERMTRIP#_R CPU_PROCHOT#_1.8 CPU_MEMHOT#_1.8V VDD0_FB_H VDD0_FB_L R488 10_0402_5% @ AF6 AC7 AA8 THERMTRIP_L PROCHOT_L MEMHOT_L CPU_PROCHOT#_1.8 02/12 Remove R59 F6 E6 +CPU_CORE_1 R489 10_0402_5% 2CPU_VDD1_FB_H 2CPU_VDD1_FB_L R21 300_0402_5% CPU_SVC 43 CPU_SVD 43 CPU_VDD0_FB_H CPU_VDD0_FB_L Close to CPU LDT_RST# C22 0.01U_0402_25V4Z @ T4 +CPU_CORE_0 R487 10_0402_5% 2CPU_VDD0_FB_H 2CPU_VDD0_FB_L R486 10_0402_5% SVC SVD 43 CPU_VDD0_FB_H 43 CPU_VDD0_FB_L CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI +1.8VS CLKIN_H CLKIN_L CPU_SVC CPU_SVD A6 A4 @ 10K_0402_5% 300_0402_5% C C20 A9 A8 R11 R9 +1.8V M11 W18 KEY1 KEY2 E 15 CLK_CPU_BCLK CPU_CLKIN_SC_P CPU_CLKIN_SC_N 3900P_0402_50V7K VDDA1 VDDA2 B F8 F9 Place close to CPU wihtin 1.5" 0.1U_0402_16V7K G +1.8V CPU_SIC @ Q129 SMB_EC_CK1 SMB_EC_CK1 32,33,34,37 D S R36 300_0402_5% SMB_EC_DA1 02/15 Follow Trinity design 02/15 Change R18 and R19 32,33,34,37 from 390 to 2.2K ohm 03/04 Reserve R175, R814, C939, Q127 and Q129 +1.8V +1.8VS D S CPU_SID SMB_EC_DA1 @ R18 Q127 2.2K_0402_5% FDV301N_NL_SOT23-3 R19 FDV301N_NL_SOT23-3 2.2K_0402_5% +1.8V 0718 AMD , need check with AMD +1.8VS R30 300_0402_5% CPU_LDT_REQ# C27 CPU_LDT_REQ# 11,19 C24 0.01U_0402_25V4Z @ +1.8V C26 U2 THERMDA_CPU THERMDC_CPU 2200P_0402_50V7K 2200p change to 1000p for ADT7421 SCLK SMB_EC_CK2 33 D+ SDATA SMB_EC_DA2 33 D- ALERT# GND VDD THERM# ADM1032ARMZ-2REEL_MSOP8 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO NOTE: HDT TERMINATION IS REQUIRED FOR REV Ax SILICON ONLY HDT Connector JP3 11 13 15 17 19 21 23 10 12 14 16 18 20 22 24 26 CPU_TEST27_SINGLECHAIN R24 @ 300_0402_5% CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 R26 R27 R28 R29 R31 R32 R33 R34 R35 2 2 2 2 1 1 1 1 300_0402_5% @ 300_0402_5% 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% +3VS +3VS FDV301N, the Vgs is: = 0.65V Typ = 0.85V Max = 1.5V U1 HDT_RST# P C25 0.01U_0402_25V4Z @ B G LDT_STOP# A Y @ 220_0402_5% R37 @ 220_0402_5% R38 @ 220_0402_5% R39 @ 220_0402_5% R40 300_0402_5% R41 11,19 LDT_STOP# 0.1U_0402_16V4Z EC is PU to 5VALW @ SAMTEC_ASP-68200-07 LDT_RST# SB_PWRGD 20,33,43 @ NC7SZ08P5X_NL_SC70-5 9/20 SP020016900 Address:100_1101 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc AMD CPU S1G2 CTRL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Friday, March 07, 2008 Sheet E of 54 A B C D L VDD(+CPU_CORE) decoupling +CPU_CORE_0 + 18A/720mil/36vias + C30 330U_X_2VM_R6M + C28 330U_X_2VM_R6M C31 330U_X_2VM_R6M + C29 330U_X_2VM_R6M Near CPU Socket +CPU_CORE_0 +CPU_CORE_1 L ?A/?mil/?vias +CPU_CORE_NB C32 22U_0805_6.3V6M C33 22U_0805_6.3V6M C34 22U_0805_6.3V6M C35 22U_0805_6.3V6M C36 22U_0805_6.3V6M 2 +CPU_CORE_0 C38 22U_0805_6.3V6M C39 22U_0805_6.3V6M +1.8V +CPU_CORE_1 C40 0.22U_0603_16V4Z C37 22U_0805_6.3V6M 1 C41 0.01U_0402_25V4Z 1 C42 180P_0402_50V8J C43 0.22U_0603_16V4Z C44 0.01U_0402_25V4Z ?A/?mil/?vias L L +CPU_CORE_0 +CPU_CORE_1 1 E C45 180P_0402_50V8J Under CPU Socket JCPUE G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 K16 M16 P16 T16 V16 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 18A/720mil/36vias +CPU_CORE_1 +1.8V FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket CONN@ +CPU_CORE_NB VDDIO decoupling +CPU_CORE_NB +1.8V 02/15 Reserve C54 C52 22U_0805_6.3V6M C46 22U_0805_6.3V6M C47 22U_0805_6.3V6M 1 C48 C49 C50 C53 22U_0805_6.3V6M @ C54 22U_0805_6.3V6M VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 FOX_PZ6382A-284S-41F_GRIFFIN Athlon 64 S1 Processor Socket C51 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 2 +0.9V Under CPU Socket VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 CONN@ 0.22U_0603_16V4Z 2 decoupling JCPUF AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 Near Power Supply VTT decoupling C: Change to NBO CAP + C59 220U_Y_4VM Between CPU Socket and DIMM +1.8V +0.9V 1 C55 0.22U_0603_16V4Z C56 0.22U_0603_16V4Z C57 0.22U_0603_16V4Z +1.8V 1 C61 0.01U_0402_25V4Z C58 0.22U_0603_16V4Z +1.8V C60 0.01U_0402_25V4Z 180PF Qt'y follow the distance between CPU socket and DIMM0 C62 180P_0402_50V8J C63 180P_0402_50V8J C64 180P_0402_50V8J C67 4.7U_0805_10V4Z C68 0.22U_0603_16V4Z C69 0.22U_0603_16V4Z C70 1000P_0402_25V8J C71 1000P_0402_25V8J C72 180P_0402_50V8J C73 180P_0402_50V8J Near CPU Socket Right side C65 180P_0402_50V8J +0.9V A: Add C165 and C176 to follow AMD Layout review recommand for EMI +1.8V C66 4.7U_0805_10V4Z 1 C79 4.7U_0805_10V4Z C80 4.7U_0805_10V4Z C81 0.22U_0603_16V4Z C82 0.22U_0603_16V4Z C83 1000P_0402_25V8J 2 C84 1000P_0402_25V8J C85 180P_0402_50V8J C86 180P_0402_50V8J 4 1 C74 4.7U_0805_10V4Z C75 4.7U_0805_10V4Z C76 4.7U_0805_10V4Z C77 4.7U_0805_10V4Z C: Change to NBO CAP + C78 220U_Y_4VM @ Near CPU Socket Left side Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc AMD CPU S1G2 PWR & GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 A B C D E +V_DDR_MCH_REF +1.8V DDR_A_D0 DDR_A_D1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DDR_A_DM[0 7] DDR_A_DM0 DDR_A_DQS[0 7] DDR_A_D6 DDR_A_D7 DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_A_D12 DDR_A_D13 DDR_A_D[0 63] DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_DM[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_DM1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_D14 DDR_A_D15 +1.8V DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 9,15,20,30 SMB_CK_DAT0 9,15,20,30 SMB_CK_CLK0 +3VS C103 0.1U_0402_16V4Z VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 R43 1K_0402_1% DDR_A_D20 DDR_A_D21 +V_DDR_MCH_REF +V_DDR_MCH_REF DDR_A_DM2 DDR_A_D22 DDR_A_D23 C95 C96 1000P_0402_25V8J DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 R44 1K_0402_1% DDR_CKE1_DIMMA DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 C88 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z C90 C89 C91 C92 C93 C94 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47_0804_8P4R_5% RP5 DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_WE# DDR_A_CAS# 47_0804_8P4R_5% RP6 C100 C99 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47_0804_8P4R_5% RP7 DDR_CS0_DIMMA# DDR_A_RAS# DDR_A_MA13 DDR_A_ODT0 C102 C101 0.1U_0402_16V4Z 0.1U_0402_16V4Z C98 C97 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47_0804_8P4R_5% Cross between +1.8V and +0.9V power plan DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_MA13 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 FOX_AS0A426-N8RN-7F CONN@ 9/20 SP07000BZ00/SP07000EU00 DDR2 SOCKET H9.2 (REV) Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc DDRII SO-DIMM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A C87 DDR_A_BS#0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3 0.1U_0402_16V4Z DDR_A_D30 DDR_A_D31 47_0804_8P4R_5% RP2 47_0804_8P4R_5% RP4 DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_A_DQS#2 DDR_A_DQS2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 47_0804_8P4R_5% RP3 DDR_A_MA4 DDR_A_MA2 DDR_A_BS#1 DDR_A_MA0 DDR_A_D16 DDR_A_D17 +1.8V +0.9V RP1 DDR_A_D[0 63] DDR_A_D4 DDR_A_D5 DDR_A_D10 DDR_A_D11 +1.8V JP4 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 A B C +1.8V D E +1.8V DDR_B_D0 DDR_B_D1 C104 1000P_0402_25V8J DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D13 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 +1.8V +0.9V JP5 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 +V_DDR_MCH_REF RP8 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DDR_B_D[0 63] DDR_B_D4 DDR_B_D5 DDR_B_DM[0 7] DDR_B_DM0 DDR_B_DQS[0 7] DDR_B_D6 DDR_B_D7 DDR_B_MA[0 15] DDR_B_DQS#[0 7] DDR_B_D12 DDR_B_D9 DDR_B_D[0 63] DDR_B_MA6 DDR_B_MA2 DDR_B_MA0 DDR_CS0_DIMMB# DDR_B_DM[0 7] DDR_B_DQS[0 7] C105 C106 0.1U_0402_16V4Z 0.1U_0402_16V4Z C108 C107 0.1U_0402_16V4Z 0.1U_0402_16V4Z C109 C110 0.1U_0402_16V4Z 0.1U_0402_16V4Z C111 C112 0.1U_0402_16V4Z 0.1U_0402_16V4Z C114 C113 0.1U_0402_16V4Z 0.1U_0402_16V4Z C116 C115 0.1U_0402_16V4Z 0.1U_0402_16V4Z C118 C117 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47_0804_8P4R_5% DDR_B_MA[0 15] DDR_B_DQS#[0 7] RP9 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA4 DDR_B_DM1 47_0804_8P4R_5% DDR_B_CLK0 DDR_B_CLK#0 RP10 DDR_CKE1_DIMMB DDR_B_MA15 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_D14 DDR_B_D15 47_0804_8P4R_5% 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 DDR_B_D21 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 8,15,20,30 SMB_CK_DAT0 8,15,20,30 SMB_CK_CLK0 +3VS C119 0.1U_0402_16V4Z VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 DDR_B_D20 DDR_B_D16 RP11 DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12 DDR_B_DM2 DDR_B_D22 DDR_B_D23 47_0804_8P4R_5% RP12 DDR_B_D28 DDR_B_D29 DDR_B_MA10 DDR_B_BS#0 DDR_B_MA1 DDR_B_MA3 DDR_B_DQS#3 DDR_B_DQS3 47_0804_8P4R_5% DDR_B_D30 DDR_B_D31 RP13 DDR_CKE1_DIMMB DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS# DDR_B_WE# DDR_CKE1_DIMMB DDR_B_MA15 DDR_B_MA14 47_0804_8P4R_5% DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 RP14 DDR_B_RAS# DDR_B_BS#1 DDR_B_ODT0 DDR_B_MA13 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 47_0804_8P4R_5% DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_MA13 Cross between +1.8V and +0.9V power plan DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 +3VS TYCO_292527-4 CONN@ 9/20 SP07000ET00/SP07000GN00 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D DDRII SO-DIMM Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E of 54 A B C D E U3B PCIE_PTX_C_IRX_P0 PCIE_PTX_C_IRX_N0 PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3 26 PCIE_PTX_C_IRX_P5 26 PCIE_PTX_C_IRX_N5 19 19 19 19 19 19 19 19 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2 GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5 PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN) AC8 AB8 PART OF PCIE I/F GPP PCIE I/F SB TMDS_B_DATA2 18 TMDS_B_DATA2# 18 TMDS_B_DATA1 18 TMDS_B_DATA1# 18 TMDS_B_DATA0 18 TMDS_B_DATA0# 18 TMDS_B_CLK 18 TMDS_B_CLK# 18 PCIE_ITX_PRX_P0 PCIE_ITX_PRX_N0 PCIE_ITX_PRX_P1 PCIE_ITX_PRX_N1 PCIE_ITX_PRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P3 PCIE_ITX_PRX_N3 C152 C153 C154 C155 C156 C157 C158 C159 PCIE_ITX_PRX_P5 PCIE_ITX_PRX_N5 C160 C161 SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C R55 R56 C162 C163 C164 C165 C166 C168 C169 C167 1 1 1 1 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 0.1U_0402_16V7K 1 PCIE_ITX_C_PRX_P0 PCIE_ITX_C_PRX_N0 PCIE_ITX_C_PRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3 1 1 2 2 2 2 1.27K_0402_1% 2K_0402_1% CardReader WLAN LAN10/100 H_CADOP[0 15] 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K New Card 26 26 27 27 26 26 25 25 PCIE_ITX_C_PRX_P5 26 PCIE_ITX_C_PRX_N5 26 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N TV Tuner H_CADON[0 15] 19 19 19 19 19 19 19 19 H_CADOP[0 15] H_CADIP[0 15] H_CADON[0 15] H_CADIN[0 15] H_CADIP[0 15] H_CADIN[0 15] U3A +1.1VS RS780MN_FCBGA528 RS780M Display Port Support (muxed on GFX) GFX_TX0,TX1,TX2 and TX3 DP0 AUX0 and HPD0 GFX_TX4,TX5,TX6 and TX7 DP1 AUX1 and HPD1 9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH 4 4 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 4 4 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 R57 H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N T22 T23 AB23 AA22 HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N M22 M23 R21 R20 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 301_0402_1% C23 A24 HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N H24 H25 L21 L20 HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N M24 M25 P19 R18 HT_RXCALP HT_RXCALN HT_TXCALP HT_TXCALN B24 B25 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N PART OF HYPER TRANSPORT CPU I/F 26 26 27 27 26 26 25 25 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N PCIE I/F GFX D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3 RS780MN_FCBGA528 0718 Place within 1" layout 1:2 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 4 4 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 4 4 R58 301_0402_1% 0718 Place within 1" layout 1:2 NEED CHECK R68 & R69 WITH AMD 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc RS780-HT/PCIE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 10 of 54 A B C D 1 PR401 0_0402_5% PL401 VOUT V5FILT VFB 13 DH_1.8V LL 12 LX_1.8V TRIP 11 V5DRV 10 PR410 0_0402_5% DRVH DH_1.8V_1 PQ401 AO4466_SO8 +5VALW PR406 15.4K_0402_1% 4.7U_0805_25V6-K PC404 PR407 @4.7_1206_5% + 2 PC415 4.7U_0805_10V6K DRVL 15 PGND TPS51117RGYR_QFN14_3.5x3.5 DL_1.8V 1 14.3K_0603_0.1% PC406 470P_0402_50V7K PL402 2.2UH_PCMC063T-2R2MN_8A_20% 1 PR408 +1.8VP PGOOD PC409 1U_0603_10V6K B+ 14 PC412 @680P_0603_50V7K PC408 220U_D2_4VY_R25M TP TON PC402 0.1U_0402_10V7K HCB1608KF-121T30_0603 2 0_0402_5% VBST PR405 EN_PSV PU401 PR404 255K_0402_1% 2 4.7U_0805_25V6-K PC403 BST1_1.8V PR402 0_0402_5% PR403 316_0402_1% +1.8VP 2 BST_1.8V GND 1+5VALW +5VALW @0.1U_0402_25V4K PC414 1.8V_B+ PC401 @1000P_0402_50V7K 2200P_0402_50V7K PC405 26,33,34,36 SYSON +1.8VP PQ402 FDS6690AS_NL_SO8 1 PC413 @10P_0402_50V8J 3 PR409 10K_0603_0.1% PJP401 +1.8VP +1.8V (7A,280mils ,Via NO.= 14) PAD-OPEN 4x4m 4 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Compal Electronics, Inc 1.8VP Document Number Rev 0.4 LA-3941P Friday, March 07, 2008 Sheet D 40 of 54 A B C D E 1 PR501 11.5K_0402_1% 2 PR517 10_0402_5% PR502 24.9K_0402_1% PR503 18.7K_0402_1% PR504 11.5K_0402_1% 2 +1.2VALWP B+++ B+ PL502 HCB2012KF-121T50_0805 1 PR508 10 LX_1.1V 11 LL2 LG_1.1V 12 DR VL2 VBST2 VBST1 22 BST_1.2V DR VH2 DR VH1 21 UG_1.2V LL1 20 LX_1.2V DR VL1 19 LG_1.2V PR507 0_0402_5% 2 UG1_1.2V PR509 0_0402_5% 18 PR512 33K_0402_5% 1 +5VALW 1 PC514 1U_0603_10V6K 2 PR514 3.3_0402_5% PC512 0.1U_0402_16V7K PC515 4.7U_0805_10V6K (4A,160mils ,Via NO.=8) PJP501 3/5V_OK 20,39 (6A,240mils ,Via NO.=12) +1.1VSP PC513 @0.1U_0402_10V7K PC520 470P_0603_50V8J + 26,28,33,36,38 SUSP# +1.2VALWP PR510 17.8K_0402_1% PR513 0_0402_5% PR516 4.7_1206_5% PGND1 TRIP1 PR511 18.2K_0402_1% +1.2VALWP PL503 3.3UH 30% MSCDRI-7030AB-3R3N 4.1A PQ504 AO4468_SO8 PQ503 FDS6690AS_NL_SO8 PC507 0.1U_0402_10V7K TPS51124RGER_QFN24_4x4 17 V5FILT V5IN 16 15 TRIP2 PGND2 14 13 VO1 VFB1 GND 23 PC521 @0.1U_0402_25V4K UG_1.1V PC516 470P_0402_50V7K BST_1.1V TONSEL VO2 24 EN1 PC511 220U_D2_4VY_R25M 0_0402_5% PGOOD1 PC519 470P_0603_50V8J PR515 4.7_1206_5% EN2 + PC509 4.7U_0805_6.3V6K PC508 220U_D2_4VY_R25M PGOOD2 PQ502 AO4466_SO8 1 UG1_1.1V PL501 2.2UH_PCMC063T-2R2MN_8A_20% 1 +1.1VSP PC506 PR506 0.1U_0402_10V7K 0_0402_5% 2 P PAD AO4466_SO8 +1.1VSP PU501 25 PQ501 VFB2 PC503 @0.022U_0603_25V7K VCCP_POK PC510 4.7U_0805_6.3V6K +1.1VSP PC505 2200P_0402_50V7K 1 PR505 0_0402_5% PC518 @0.1U_0402_25V4K 1 PC502 2200P_0402_50V7K 1 PC501 4.7U_0805_25V6-K PC517 4.7U_0805_25V6-K B+++ PC504 4.7U_0805_25V6-K +1.1VSP PR518 0_0402_5% +1.1VS B+++ PJP502 +1.1VS +1.2VALWP PAD-OPEN 4x4m +1.2VALW PAD-OPEN 4x4m PJP503 +1.1VSP +1.1VS PAD-OPEN 4x4m Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D 1.1VSP/1.2VALWP Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 41 of 54 A B C D E 1 +1.8V +1.8V PU603 +5VALW NC TP PC603 1U_0603_16V6K G2992F1U_SO8 NC VREF NC VOUT NC TP +5VALW PR606 1K_0402_1% VOUT VCNTL GND PC613 10U_0805_10V4Z VIN NC VREF NC VCNTL PC609 @10U_0805_10V4Z GND VIN 2 1 PR601 1K_0402_1% 2 PC601 10U_0805_10V4Z PC602 @10U_0805_10V4Z PU601 PC612 1U_0603_16V6K G2992F1U_SO8 PR608 0_0402_5% PC606 @0.1U_0402_16V7K D G S +1.5VSP 1 2 SUSP 1 36 PR607 5.1K_0402_1% S PC605 10U_0805_6.3V6M G PQ602 SSM3K7002FU_SC70-3 PR604 @0_0402_5% +0.9VP PR603 1K_0402_1% D SUSP 36 PC604 0.1U_0402_16V7K PQ601 SSM3K7002FU_SC70-3 1 PR602 0_0402_5% PC611 0.1U_0402_16V7K VREF1.5V 35,36 SYSON# PC614 10U_0805_6.3V6M PC610 @0.1U_0402_16V7K (500mA,40mils ,Via NO.= 1) PU602 APL5508-25DC-TRL_SOT89-3 PAD-OPEN 3x3m PJP603 +1.5VSP +1.5VS (1A,40mils ,Via NO.= 2) +2.5VS (500mA,40mils ,Via NO.= 1) IN OUT +2.5VSP GND (2A,80mils ,Via NO.= 4) PR605 @150_1206_5% +0.9V 2 PC607 1U_0603_6.3V6M +0.9VP +3VS PC608 4.7U_0805_6.3V6K PJP601 PAD-OPEN 3x3m PJP602 +2.5VSP PAD-OPEN 3x3m 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc 0.9VSP/2.5VSP/1.5VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 42 of 54 B C PC258 2200P_0402_50V7K 4.7U_0805_25V6-K UGATE NB1 PC242 1000P_0402_50V7K 2 PR221 16.5K_0402_1% B 47P_0402_50V8J 47P_0402_50V8J 47P_0402_50V8J PC259 PC256 1800P_0402_50V7K PC257 390P_0402_50V7K PC252 47P_0402_50V8J PC222 2200P_0402_50V7K PC221 4.7U_0805_25V6-K PC220 4.7U_0805_25V6-K PR231 16.5K_0402_1% PR233 4.02k_0603_1% PC229 0.1U_0603_25V7K FDS8672S_SO8 PC231 180P_0402_50V8J PR236 6.81K_0402_1% PC236 4.7U_0805_25V6-K PC237 4.7U_0805_25V6-K PC226 2200P_0603_50V7K PC230 1000P_0402_50V7K 1 +CPU_CORE_1 PL204 0.36UH_PCMC104T-R36MN1R17_30A_20% 47P_0402_50V8J PQ208 FDS8672S_SO8 CPU_B+ PR229 4.7_1206_5% PR244 4.7_1206_5% PQ207 ISP ISP 1 PR238 54.9K_0402_1% PC232 1200P_0402_50V7K PR240 1K_0402_1% 2 PR243 255_0402_1% 4700P_0402_25V7K PC233 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A PC249 3300P_0402_50V7K PC250 1800P_0402_50V7K PC211 @47U_25V_M PC248 3300P_0402_50V7K PC254 1800P_0402_50V7K PC255 390P_0402_50V7K PC261 PC213 4.7U_0805_25V6-K PC214 2200P_0402_50V7K PC212 4.7U_0805_25V6-K PR242 PC218 4.7_1206_5% 2200P_0603_50V7K 1 PR220 4.7_1206_5% 2 PC219 0.1U_0603_25V7K PC260 +CPU_CORE_1 ISP PR217 4.02k_0603_1% PQ206 RQW130N03-FD5_PSOP8 PC224 0.22U_0603_10V7K +CPU_CORE_0 PL203 PC240 2200P_0402_50V7K PC235 4.7U_0805_25V6-K PC234 4.7U_0805_25V6-K PC239 330P_0402_50V7K 3 TP PR228 2.2_0603_5% UGATE1_1 49 ISP1 ISN1 24 23 COMP1 VW1 22 21 FB1 20 VDIFF1 VSEN1 18 VSEN1 19 17 RTN1 16 VSEN0 PR226 0_0603_5% 2 PC241 1000P_0402_50V7K PQ205 FDS8672S_SO8 BOOT1 PR241 0_0402_5% 25 VW0 CPU_VDD1_FB_H BOOT1 COMP0 PR239 0_0402_5% 8 BOOT0 UGATE1 UGATE1 CPU_VDD1_FB_L 2 BOOT_NB PHASE NB UGATE NB 37 38 PHASE_NB UGATE_NB PHASE1 26 12 PC215 1000P_0402_50V7K PC253 1 BOOT_NB1 PR207 15.4K_0402_1% 39 LGATE NB PGND_NB LGATE_NB OCSET_NB RTN_NB VSEN_NB 27 PR237 0_0402_5% CPU_VDD0_FB_L PHASE NB LGATE NB PR209 0_0402_5% 43 45 44 FSET_NB COMP_NB VCC FB_NB PHASE1 ISL6265IRZ-T_QFN48_6X6 FB0 11 6.81K_0402_1% PR235 0_0402_5% 46 47 28 PC228 1000P_0402_50V7K CPU_VDD0_FB_H PQ204 FDS8672S_SO8 LGATE1 29 PGND1 PR232 0.36UH_PCMC104T-R36MN1R17_30A_20% LGATE0 LGATE1 RTN1 1200P_0402_50V7K PC227 180P_0402_50V8J 30 VDIFF0 PC225 54.9K_0402_1% 31 PVCC OCSET RTN0 RBIAS ISP0 PR230 32 LGATE0 1K_0402_1% PGND0 ISN0 PHASE0 15 33 10 4700P_0402_25V7K PR227 PHASE0 VSEN0 255_0402_1% UGATE0 SVD 14 82.5K_0402_1% PWROK UGATE0 ENABLE + PQ203 RQW130N03-FD5_PSOP8 0_0603_5% PR219 34 SVC UGATE0_1 2.2_0603_5% 0.22U_0603_10V7K PR214 PC217 2 36 @1000P_0402_50V7K PC244 @1000P_0402_50V7K PC245 @1000P_0402_50V7K PC246 @1000P_0402_50V7K PC247 34.8K_0402_1% PC223 PC210 2.2U_0603_6.3V6K 35 13 VR_ON BOOT0 PGOOD PL202 SMB3025500YA_2P +5VS BOOT_NB OFS/VFIXEN ISP CPU_SVC PR225 VIN +CPU_CORE_0 CPU_SVD 48 PR216 10K_0402_1% PU201 PR246 1100K_0402_5% ISL6265_PWROK PR234 @100K_0402_5% PR218 SVD 0_0402_5% PR222 SVC 0_0402_5% PR223 PR224 2 33 VGATE 19 H_PWRGD 6,20,33 SB_PWRGD 33 PR215 @10K_0402_5% B+ CPU_B+ PR211 1_0603_5% 40 PR212 0_0402_5% PR213 @0_0402_5% PC206 0.1U_0603_16V7K VSEN_NB RTN0 +5VS +3VS 41 PC216 0.1U_0603_25V7K PC243 1000P_0402_50V7K CPU_B+ RTN_NB PR208 2_0402_5% 42 33P_0402_50V8K PC209 2 S 2 PR210 PC208 44.2K_0402_1% 1200P_0402_50V7K 1 PC207 0.1U_0402_16V7K Connect to EC pin 110 PR206 0_0402_5% ISL6265_PWROK PQ209 SSM3K7002FU_SC70-3 PR205 2_0402_5% D G VFIX_EN PR203 0_0402_5% PC204 PC205 1000P_0402_50V7K +5VS 33 4 @680P_0603_50V7K CPU_B+ PC251 PQ202 AO4466_SO8 PQ201 AO4468_SO8 PR204 22K_0402_1% E PC203 2200P_0402_50V7K PC202 220U_D2_4VY_R25M 2 VDD_NB_FB_L 10U_0805_6.3V6M PC201 VDD_NB_FB_H + D 4.7UH 30% MSCDRI-7030AB-4R7N 3.3A PC238 470P_0402_50V7K PL201 +CPU_CORE_NB PR245 @4.7_1206_5% A C D CPU_CORE Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 43 of 54 A B C D E Version Change List ( P I R List ) for Power Circuit Item Page# Title Date Request Owner Issue Description Rev Solution Description 37 DC Connector /CPU_OTP 9/29 Compal for Layout PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805 and add PL4 the same of the value 41 1.1VSP/1.2VALWP 9/29 Compal HW request PC508 and PC511 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M 41 1.1VSP/1.2VALWP 9/29 Compal HW request Add PJP503 43 CPU_CORE 9/29 Compal HW request PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M 43 CPU_CORE 9/29 Compal TI FAE suggested that after he review the layout Add PC241 PC242 PC243, and the value are 1000P_0402_50V7K Reserve PC244 PC245 PC246 PC247, and the value are 1000P_0402_50V7K 43 CPU_CORE 9/29 Compal TI FAE suggested that after he review the layout Add PJP201 38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102 37 10/08 Compal for Layout These two choke are parallel ,it's not series 38 Charger 10/08 Compal the footprint is wrong Change the footprint of PR102 10 40 1.8VP 10/08 Compal PWR request Delete PC410 and PC411 11 41 1.1VSP/1.2VALWP 10/08 Compal PWR request Add PR517 DC Connector /CPU_OTP PJP202 PR518 3 12 37 13 37 14 DC Connector /CPU_OTP 11/01 Compal PWR request Add PD4 3.3VALWP/5VALWP 11/01 Compal for Layout change PQ301, Cencel PQ303 43 CPU_CORE 11/02 Compal EMI request Add PC248, PC249, PC250 15 37 3.3VALWP/5VALWP 11/12 Compal for Layout Change PC310, add PC319 16 37 3.3VALWP/5VALWP 12/31 Compal PWR request 12/31 Compal Vendor request 17 43 CPU_CORE PC12 Add PU302, control signal changed to ACOFF Change Change Change Change and PR231 to 16.6K_ohm and PR233 to 4.02K_ohm to 17.8K_ohm to 100K_ohm Compal Secret Data Security Classification 2007/08/02 Issued Date PR221 PR217 PR223 PR224 2008/08/02 Deciphered Date Title Compal Electronics, Inc Power Changed-List History-1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 44 of 54 A B C D E Version Change List ( P I R List ) for Power Circuit Item Page# Title Date Request Owner Issue Description Rev Solution Description 1 18 19 38 37 Charger DC Connector /CPU_OTP Compal EMI request Add PC128 220pF 01/09 Compal 01/14 Compal for layout Change PC309 to D size and add PC320 AC LED change to KBC control AC_LED# connect to KBC pin 97 20 37 21 38 Charger 02/27 Compal EMI request CHG_B+ Add 1200pF and 330pF 22 43 CPU_CORE 02/27 Compal EMI request CPU_B+ Add 1800pF*2 2200pF*1 and 390pF*2 23 37 3.3VALWP/5VALWP 02/27 Compal EMI request B+ Add 2200pF and 390pF 24 37 02/27 Compal 25 26 27 3.3VALWP/5VALWP 01/08 DC Connector /CPU_OTP 37 3.3VALWP/5VALWP 43 CPU_CORE 43 CPU_CORE 02/27 Compal 02/15 Compal 03/04 Compal EMI request VIN Add 2200pF and 390pF, ADPIN add 820pF Change OTC shun down pin Change OTC shun down pin to PU301 pin13 Change high-side MOS for WWAN issue Change PQ203 and PQ206 to powerpak HW request add H_PWRGD control net 3 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc Power Changed-List History-1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 45 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 25 Date Title LAN 10/29 10/29 10/29 25 16 LAN CRT 29 Audio FAN 29 Request Issue Description Owner HW Change LAN Chip U20 from Marvell 88E8042 to Realtek RTL8102EL HPQ Add POE(Power Over Ethernet) design HW CRT can not display 10/30 11/01 HW HW Speaker no sound FAN Conn not correct part Speaker 11/01 HW Speaker Conn not correct part 34 MDC 11/01 HW MDC Conn not correct part 11,35 11,21 TV_OUT NB/SB Thermal 11/05 11/05 HW HW TV-OUT Function no support NB Thermal Function no support (locate too far) 10 21,31 SB SATA 11/05 HW 11 21 SB SATA 11/05 HW SB SATA Port change to Port for ATI Common Design SB SATA_ACT# Pull High become +3VS 12 21 SB GPIO 11/05 HW Change SB GPIO refer to JBK00 for common 13 14 15 16 17 31 29 25 21,24 36 SB SATA Audio HP OUT LAN Transfermor SB SATA DIM LED 11/05 11/05 11/05 11/06 11/06 HW HW HW HW HW Vertical L51 1< >4 , 2< >3 for layout routing Add 150UF Caps for each DOCK_LOUT_R/L Correct U19 LAN Transfermor pin definition SB SATA Port change to Port for ATI Open Issue Reduce DIM LED unnecessary design 18 27 CardReader 11/06 HW Change CardReader Socket for M/E new part and Chip for JMicron new version Rev Update the LAN Design page and support circuit 0.2 Change the CRT Conn signals connection first Wait correct symbol for fix Add R973(10K_0402) to +3VALW on HP_DET# 0.2 2007/08/02 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Add 150UF Caps for each DOCK_LOUT_R/L Correct U19 LAN Transfermor pin definition Change SB SATA port to port Del R1026 and Q167, add Net "DIM_LED#" for connect Change location from PJP604 to PJP8 Change JREAD to TAITW_R015-B10-LM Reserve R413,C902 close to JREAD.20; R412,C901 close to JREAD.26; R411,C900 close to JREAD.37 Change R457 close to U23.42 Add R455,R456 close to U23.42 Del Q169,R1051 Change net CR_LED# become CR_LED connect U23.21 and Q53.2 Add R454 pull down to GND Change R405,R122 from 200K to 10K pull-high Remove C895,U22 2008/08/02 Deciphered Date Title 0.2 Connect U15.C6 to GND by 0_0402 Change WLOFF# from GPIO50 to GPIO61 Change BT_COMBO_EN# from GPIO51 to GPIO62 Change WWOFF# from GPIO52 to GPIO63 Vertical L51 1< >4 , 2< >3 for layout routing 0.2 Compal Electronics, Inc HW Changed-List History-1 Date: C 0.2 0.2 0.2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B Change R343.1 power rail from +5VS to +3VS Install R343 Compal Secret Data Security Classification A 0.2 Change JP2 PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P Change JP20 PCB Footprint from ACES_85204-04001_4P to ACES_88231-04001_4P Change JP20 PCB Footprint from ACES_88018-124G_12P to ACES_88020-12101_12P Del R59,R60,R61,R115,R116,R117 and TV-OUT related design Cancel NB_THERMAL_DA/DC connection between NB and SB,del C500 Change SB SATA port to port Issued Date Solution Description Update the LAN Design page and support circuit D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 46 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 11/07 11/07 11/07 11/07 11/09 Request Owner HW HW CIC HW HW Normalize CRT design for common Normalize LCD design for common CIC feedback RMA concern for common Normalize KB926 Crystal part for common Change U54 WebCam power design and related Change L83,L84 (10_0402) become R241,R240 (0_0603) Date Issue Description Rev 19 20 21 22 23 16 17 18 33 17 Title CRT LCD LCD KBC WebCam Solution Description 24 25 18 19,32 HDMI SB-CLK-Debug 11/09 11/09 HW HW Reduce HDMI Design Debug Card no function issue Remove R490(100K_0402) 0.2 0.2 26 27 28 29 30 31 25 18 33 35 26 LAN HDMI CPU KBC Holes Mini-Card 11/09 11/09 11/09 11/09 11/09 11/09 HW HW HW HW ME HW RJ45 LED Power correct back Reduce HDMI Design Add H_THERMTRIP# one more way Update KBC Pin Definition for common Update for M/E Drawing Reduce Mini-Card design, change SIM Card design Change JRJ45.13, JRJ45.11 from +3V_LAN_LED to +3V_LAN 0.2 0.2 0.2 0.2 0.2 0.2 32 33 33 27 KBC CardReader 11/09 11/10 HW HW Reserve 0_0603 for KB Back Light Correct CardReader LED part 34 34 LED Function 11/10 HW Correct LED function for common Change R491 from 200_0402 to 200_0805 Change Q43 from AOS3413 to SI2301 Change Y7 from 9H03200413 small to 1TJS125DJ4A420P normal Change U54 from G916-390T1UF to RT9193-39GB Remove R891,R892 if no use G916-390T1UF Add C718 close to U54.4 for RT9193-39GB Remove R1027~R1030 for JP7 no install Change JP7 from 8pin to 6pin Del R1031,add R303 close to R301 and U15.P2 Connect for CLK_PCI_SIO2 to JP41.15 Remove R490(100K_0402) Add R16 close to Q3.1 for H_THERMTRIP# Add H_THERMTRIP# to U33.25 Del H49 H50 H38 H45 for M/E drawing change Replace D17 and D47 become R52 and R53 Del R400 and R46, Change JP6 pin definition for common Add R516 (0_0603) between JP48.1/4 and +5VS_LED 0.2 0.2 HW Change R15.2,R21.2,R36.2,R30.2 connection from +1.8V to +1.8VS; Remove R622, install R581 0.2 11/13 HW Reduce the level shift design for Chip A12 0.2 11/13 11/13 HW HW Update the WebCam+Digital Mic reserver conn Update THERMTRIP# design to EC Del Q6,R87; Q5,R84 and replace by 0ohm (add R67,R68) connect directly Install R371 (10K ohm) 11/13 HW Remove EMI solution become reserve for verify SB-GPIO KBC-GPIO 11/10 11/11 HW HW 37 6,31 CPU,FPR 11/13 38 11 NB 39 40 17 6,33 WebCam CPU,KBC 41 18 Change JP7 from SP02000HC00(8pin) >SP02000IL00(6pin) Add R112,R113,R115~R120 close to each L85~L88 for co-lay Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Date: C 0.2 Compal Electronics, Inc HW Changed-List History-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B 0.2 0.2 Change R16.2 connection from THERMTRIP# to THERMTRIP#_EC for separate A Add HDD_HALTLED# connect from U15.P8 Add R46 10K_0402 PH to +5VL close to U33 Add R514,R515 10K_0402 PH to +3VL close to U33 21 33 0.2 Add one more way for GSENSOR LED# inform pin Add CIR_IN PH to +5VL Add ESB_CLK/DAT PH to +3VL Reduce S3 power consumption 35 36 0.2 0.2 Change D5 from SC500004E00(AQUA_WHITE) to SC500004W00(WHITE) Change LED from D50,D30,D27 SC500004E00 (AQUA_WHITE) to D6,D7,D8 SC500004W00(WHITE) Change LED from D45,D46 SC500004B00 (AQUA_WHITE/AMBER) to D17,D18 SC500005M00 (YELLOW/WHITE); Add Q7,R20 and R42 close to D18 HDMI 0.2 0.2 0.2 0.2 0.2 D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 47 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 42 19.32 Title SB,BIOS 11/13 Request Issue Description Owner HW Reduce SB related design for Chip A12 and others Date 43 21,32 SB,BIOS 11/13 HW BIOS Debug Tool reserve 44 45 46 47 25 13 18 20 LAN NB HDMI SB 11/13 11/13 11/13 11/13 HW HW HW HW Update LAN Chip Symbol link to CIS server Add 0ohm_0603 to separate VDD18_MEM Reduce HDMI related design for common Reduce SB related design for common and A12 chip 48 SB,Cardreader 11/13 HW 49 50 51 20,21, 27 21,33 28,33 33 SB,KBC Codec,KBC KBC 11/13 11/13 11/13 HW HPQ HW Reserve Cardreader D3E function (CR_WAKE# & CR_CPPE#) Reduce SB related design for common EC_BEEP function for KBC add Reduce S5 Power Consumption 52 33 KBC 11/13 HW Reduce KBC Design for common and Ver:C0 Chip Change from SA00001J530 to SA00001J540 53 34 Switch Design 11/13 HW Update CSD function board design for common 54 34 LED 11/14 HW 55 56 57 29 29 4,24 Audio-Dock Holes Multi-Bay 11/14 11/14 11/14 HPQ ME ME Correct T/P On/Off LED design define Correct G-Sensor LED design define For GS mark requirement Update Holes to meet M/E Drawing Update Symbol to meet M/E Drawing 58 59 60 61 62 63 33 20 33 35 33 28,29 Holes SB KBC DOCK K/B AUDIO 11/14 11/16 11/16 11/16 11/16 11/18 ME ATI EC EMC HW HPQ Update Holes to meet M/E Drawing Reserve to fix the OTS325055 Issue Change design for EC team debug Connect DOCK guide pin to GND Fix KB matrix issue Make some Audio related design change 29 AUDIO 11/19 HPQ Del Q155,R986, and add R311 close to U15 Del R1011 become T18, Cancel R1012 and connect to H31 and JP41 directly Add SB_INT_FLASH_SEL and related (JP12,U30,R228,R226,C489 close to U29) Update LAN Chip U20 Symbol link to CIS server Add R1051(0_0603) between +1.8VS & +1.8V_VDD_SP Del R490 (100K_0402) Remove R994 (0_0402) Change U15.F1 connection become test point Remove R1053, change R1052 become 0_0402 0.2 0.2 0.2 0.2 0.2 Add R81 close to U15;Q54,R124 close to U23 for connect U15.F8 to U23.13 ;Add R369 close to U23 for connect U15.M5 to U23.16 Del D51 and R1034, Change the net AC_IN become AC_IN_D 0.2 Add R563 close to C955; Add R544 close to U33.31 Change R1040.1 connection from +3VL_EC to +3VALW Del R546 PH to +3VL_EC, Del D26 replace by add R547 close to U33 for short Del R537 become Test Point, change R516 become 150_0603 Remove R1044, change R1040 from 10K to 100K Change R528.2 , R529.2 connection from +5VALW to +5VL Install C814 (4.7U_0805) Change JP36.1 connection become +3VL;Change R1046.1 and R1047.1 connection become SMB_EC_CK1/DA1 Change JP36.7 connection from GND to +5VALW_LED by Change Q153 from 2N7002DW to 2N7002 Change R988.1 connection from +5VS_LED to +3VS Add R968,R969 close to C775/C776 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Add JDOCK.45/46 to GND Del KSI6 and KSO9 out of page net connect Change C983,C984 from 1UF to 0.022UF Change C1049,C1050,C1040,C1041 from 0.47UF to 0.022UF Change R1002,R1005 from 20K to ohm Change C1044 from 10UF to 4.7UF Remove R1000,R1004; Install R1001,R1003 Change R968,R969 from 40.2_0402 to 47_0603 Compal Secret Data 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title 0.2 Compal Electronics, Inc HW Changed-List History-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: C 0.2 0.2 0.2 Reserve R83 PH to +3VS Change JP34.1 from +5VALW to +5VL Make some Audio related design change B Update JP2,JP9,JP10,JP11,JP20,JP40,JHDMI,JESAT,JCRT, JDOCK Symbol Add back H52 become H_1P5N; Del CF4 Security Classification A 0.2 Add back H52 become H_1P5N; Del CF4 64 Rev Solution Description D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 48 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 65 13 66 67 68 22 22 33,34 69 70 71 72 73 74 75 76 77 23 31 34 33 19 26 28 10~13 78 79 80 81 82 83 84 85 86 87 88 89 19 22 28 34 14 15 28 20,27 32 34 19 90 91 92 33 32 34 06,19, 23 Date Title NB SB SB Function Board 11/20 11/20 11/20 11/20 SB BlueTooth Power On Switch KBC CPU SB Express Card Audio Codec NB, SB SB Codec T/P HDMI CLK Gen Codec SB,CardReader BIOS LED SB SB KBC BIOS LED 11/20 11/20 11/22 11/22 11/22 11/22 11/22 11/22 11/23 11/23 11/26 11/26 11/28 11/28 11/28 11/28 11/28 11/28 11/28 11/30 11/30 11/30 12/03 12/03 Request Issue Description Owner ATI Design Change for NB A12 Version chip Rev Solution Description Remove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017 Install L19, remove L95 0.2 Install R593, remove R592 Remove R12,C543,C544,C547,C536 ATI HW HW Design Change for SB A12 Version chip Reduce SB Power Design-No IDE support Reserve for Rachman UMA selective HW HW HW HW HW HW HW HW HW Make the SB Strap Seeting for common Update BT design for common Cancel one reserved power on switch Modify SMB_EC_DA1/CK1 PH for common Link PROCHOT# between CPU and NB Reserve LPCCLK1 for debug card function To avoid New Card Switch leakage issue Reserve SPDIF OUT1 test point for verify BOM correct for SI-1 SMT build HW HW HW HW ATI HW HW HW HW HW HW ATI Change Crystal Res size for layout space Reduce SB SATA Power Caps (Confirm with ATI FAE) SPDIF0 > design change to follow Vader Change T/P Power for reduce S4/S5 power consumption Fix HDMI no function issue Change design for new version CLK Gen Change EC_BEEP function become reserve Disconnect D3E support for A version to avoid risk Use Ext BIOS as default Cancel WLAN/WWAN ext pull high Fix PA M/E Interfere issue for SI-1 ATI recommend for update HW HW HW Change 32.768KHz Main Source Vendor become EPSON Cancel Ext BIOS reflash design because of +3VL erroe Cancel G-Sensor INT2 LED function 0.2 0.2 0.2 Reserve R555 for +5VALW_LED, add R554 for +3VL close to JP36.1 Reserve R1034 close to JP36.4,R1035 close JP36.5,Remove R1036 Add R513 PH to +3VS close to U33.19 Install R356 (10K_0402) Change R520 from 47K_0402 to 10K_0402 Del SW3 Change R528,R529 pin connection from +5VL to +3VL Add R59 close to Q2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Add R308 22_0402 for U15.E22 close to R362.1, remove R301 Add R54(0_0402) close to U21.6 Add T21 close to U27.45 Update U3(SA00001ZG00 >SA00001ZG20);U10(SA00001Z300 > SA00001Z310);U15(SA00001S510 >SA00001S560) Change R389 from 0603 to 0402 Change C567,C568 from 10U_0805 to 1U_0805 Change U27.48/45 pin connection Remove R235; Add Q85, R645, Q34 Remove R102; Add R101 Remove R1045 Remove R563 Remove R81,R369 Remove R221 Remove R1041 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 change Y3 from SJ100001U00 to SJ100006600 with 10PPM Change R312 from 0_0402 to 33_0402; Change R356 from 10K_0402 to 2.2K_0402; Install C23 as 0.1UF_0402 Change Y7 from SJ100001V00 to SJ132P7K220 Add R221; Remove U30,R226,R228,C489 Remove Q156 0.2 0.2 0.2 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc HW Changed-List History-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 49 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 01 02 03 04 05 06 07 08 09 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 36 19 19 23 29 23 31 32 32 33 34 35 35 34 34 34 33 14 17 22 25 31 19 19 20 21 25 26 33 35 36 34 33 34 34 06 Title SB SB SB Amplifier Speaker Finger Printer BIOS ROM BIOS ROM EC T/P ON/OFF LED Docking MDC Switch board Switch board Switch board EC SB Webcam and Digital MIC SB LAN USB port SB SB SB SB LAN WWAN EC M/B DC-DC Switch board Keyboard connector Lid switch connector Switch board HDT debug port Date 12/26 12/26 12/26 12/26 12/26 12/26 12/26 12/26 12/26 12/26 12/26 12/26 01/03 01/03 01/03 01/07 01/08 01/08 01/08 01/08 01/08 01/09 01/09 01/09 01/09 01/09 01/09 01/09 01/09 01/09 01/10 01/10 01/10 01/10 01/14 Request Owner HW HW HW HW HW HW HW HW HW EC HW ME HW HW HW Power HW HW Issue Description Rev Solution Description Add R303 and connect to CLK_PCI_ISO2 Chage net name to PCI_CLK3 Change value from 4.7uF to 1uF Speaker right and left channel reverse Reverse JP20 pin define Delete R622 Reserve R221 Stuff U30, R228, R226, C489 Change power from +3VALW to +3VL Add pull down resistor R1063 Reverse TP on/off LED Common design Change R572 to 22 ohm and R566 to 2K ohm ME change stand off Change PCB Footprint from 3P3 to 4P0 Useless Delete R556, R557 Useless R1036 Option Cypress and ENE Cap board Connect R1046 to JP36.3 and connect R1047 to JP36.9 Connect VFIX_EN to EC pin 110 Add pull high resistor R1064 Remove reserve circuit for Webcam and Digital MIC Change L61, L63, L66, L60, L67, L68, L69 to ohm resistor Change C528, C543, C566, C504 to MLCC tpye Change C552 from 22uF to 4.7uF HW Realtek Layout EMI EMI EMI DFB DFB EMI HW ME HW HW DFB DFB EMI AMD Chage part number from SA000026Q00 to SA000026Q10 Swap D11, D12, L51 pin define per layout request Add reserve cap C1085~C1087 Fine-tune R302, R303, R308 from 22 ohm to 33 ohm Add reserve cap C1088~C1091 Y4 Change Footprint to the same as Y2 Change Y5 Footprint to the same as Y2 Add C738, C739, C740, C750, C751 as 39pF Connect AC_LED# to PQ3 Add screw hole Remove +1.2V and +3V circuit Add R1065 and R1066 for OPP power button board Change Keyboard connector same as JBK00 Change Lid switch connector type Change R1048 and R1049 from ohm to bead Stuff R26, R28 and R41 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title C HW Changed-List History-2 Date: B 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Remove R303 from PCICLK3 and add R301 as ohm D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 50 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 37 38 39 40 41 42 25 33 11 17 15 15 Title LAN EC NB LVDS Clock GEN Clock GEN Date 01/14 01/14 01/15 01/15 01/15 01/15 Request Owner HW HW HW HW HW Vendor Issue Description Solution Description Rev 8102E (10/100M 48 pin) can not support DSM function Reserve Q1056, Q1057, C1077 and Q144 Change PJP605 to R1067 8102E (10/100M 48 pin) can not support DSM function Reserve R544 No support daul channel panel Remove LVDS signal of Channel B No support daul channel panel Remove LVDS signal of Channel B (remove C1061~C1063) To slove noise issue Chagne C1074~C1076 to 12pF Clock Gen spec update Change R379 to 158 ohm and R380 to 90.9 ohm 0.3 0.3 0.3 0.3 0.3 0.3 2 3 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc HW Changed-List History-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 51 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 25 34 06 06 06 06 07 12 12 13 13 24 27 27 31 31 33 33 34 34 11 11 19 21 32 34 33 35 34 34 34 11 16 16 34 Title LAN S/W board connector CPU CPU CPU CPU CPU NB NB NB NB Multibay connector Card Reader Card Reader BT BT EC EC Debug SW TP LED NB NB SB SB SPI BIOS WL/BT LED control EC Screw hole Date 02/12 02/12 02/12 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/15 02/18 02/18 02/18 02/18 02/18 02/18 02/18 02/19 S/W board connector 02/19 S/W board connector 02/19 S/W board connector 02/22 NB 02/22 CRT connector 02/22 CRT connector 02/22 Lid switch connector 02/22 Request Owner HW HW HW HW HW HW HW HW HW HW HW ME HW HW ME HW HW HW HW ME HW HW HW HW HW HW HW ME ENE ENE HW HW HW HW HW Issue Description Rev Solution Description For ESD protect Reserve D55 To avoid cap sensor board abnormal Reserve R558 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Reserve R59 Follow Trinity design Change CPU SM BUS from EC2 to EC1 Reserve C16 Follow Trinity design Change R18 and R19 from 330 to 2.2K ohm Reserve C54 Remove L96 Change L12, L13 from bead to ohm Change L16, L18, L19, L22 from bead to ohm Remove L95 Change JP10 Footprint Change Card Reader LED active status Reserve Q53 and R454, add R1070 Change Card Reader LED active status Reserve R112 and add pull low resistor R1069 Change JP32 Footprint and reverse pin define Saving Power consumption Change BT power source from +3VALW to +3VS Remove JP34 and reserve R1068 for EC debug To solve can't power on when first plug in AC adapter Change R1040 from 100K to 10K ohm and connect to +3VL_EC Remove SW2 Add D19 for PR sku Change R371 from 10K to 300 ohm Add pull low resistor R1072 Reserve C1085 and R303 To solve can't power on when first plug in AC adapter Add R1071 and D56 to connect to AC_IN Remove U30, C489, R226, and R228 Stuff R221 Modify circuit WLAN/WWAN/BT LED control Follow Trinity design Change R514 and R515 from 10K to 4.7K ohm To slove TP on/off button feeling no good when press Add H57 For ENE cap board Add LDO circuit (U65, R1073, C1097,C1099, J2) For ENE cap board Change R554 pin power plan from +3VL to +3VL_CAP For cap board Add C1098 To splve CRT rising/falling fail issue Reserve R62, R63, R64 To splve CRT rising/falling fail issue Change R211, R214 and R217 from 150 ohm to 75 ohm To splve CRT rising/falling fail issue Change C472, C476, C858 from 22pF to 6pF To solve short issue for lid switch board Move C1100 and C1101 from lid swtich board to M/B Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Date: B C Compal Electronics, Inc HW Changed-List History-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 52 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 67 67 25 35 34 34 33 33 36 31 15 16 17 32 17 34 06 34 11 31 22 13 35 11 11 33 06 19 20 21 21 31 17 15 20 15 15 Title LAN Screw hole Date 02/22 02/22 S/W board connector 02/22 S/W board connector 02/22 EC 02/22 EC 02/22 DC/DC 02/25 USB connector 02/25 Clock GEN 02/25 CRT Connector 02/25 LCD Connector 02/25 Debug connector 02/26 WEBcam LDO 02/26 Lid switch connector 02/26 CPU S/W board connector NB USB connector 02/27 03/03 03/03 03/03 SB 03/03 NB 03/03 Docking connector 03/03 NB 03/03 NB 03/03 EC 03/03 CPU 03/04 SB 03/04 SB 03/05 SB 03/06 SB 03/06 eSATA connector 03/06 LCDVCC circuit 03/06 Clock GEN SB WWAN connector WWAN/WLAN 03/06 03/06 03/06 03/06 Request Owner DFB DFB EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI HW HW POWER EMI EMI EMI HW HW DFB AMD AMD AMD AMD AMD EMI AMD AMD AMD HW HW HW HW HW Issue Description Rev Solution Description To solve kink pin to interfere with PCB To solve EMI issue for ENE cap board Change R1048 and R1049 from bead to ohm To solve EMI issue for ENE cap board Reserve R1074/C1102 for ESB_CLK1 and R1075/C1103 for ESB_DAT1 To solve EMI issue for ENE cap board Add R1076, C1104 and R1077 Add C1105 For EMI request Add C1110~C1117 For EMI request Add C1109 For EMI request Add C1106 For EMI request Add C1107 For EMI request Add C1108 For EMI request Add C1118 To reduce power consumption in S3 mode Add PJP6 to connect to +5VS Stuff R1013 and reserve R1014 Connect JP40 pin to +3VALW Change net name ENTRIP2 to EN0 For EMI request Change R558 to C1119 (0.1uF) For EMI request Change C1120 (0.1uF) For EMI request Change C1121 (0.1uF) Change L60, L61, L63, L66, L67, L68, L69 from ohm to bead Remove L20, L21 and use PJP604 to replace Change JDOCK connector Footprint To support VariBright feature Add D58 and connect to INV_PWM To support VariBright feature Change backlight inform signal (R70, R1072) from LVDS_BLON to LVDS_ENA_BL To support VariBright feature Change JDOCK connector Footprint Reserve R175, R814, C939, Q127 and Q129 To solve can not power on when use single core CPU Change net name from H_PWRGD to H_PWRGD_SB For EMI request Add SSC circuit (U66, R1080, R1081, R1082, R1083, C1122) for HDA_BITCLK For eSATA GEN1 fail issue Change C520 and C521 from 0.01uF to 1000pF For eSATA GEN1 fail issue Change C520 and C521 from 0.01uF to 1000pF For eSATA GEN1 fail issue Change C792 and C793 from 0.01uF to 1000pF To solve LCD power up sequence fail Change R225 from 470 ohm to 220 ohm For IDT CLOCK GEN Add C1123 To avoid CMOS data lose when shutdown suddenly Add D58 and connect to 3/5V_OK To support wake on WWAN feature Add power on/off control circuit (Q167, R1087) To avoid leakage power from SB Add D59 and D60 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date Title Date: B C Compal Electronics, Inc HW Changed-List History-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Update JRJ45 PCB Footprint Change H53 and H54 from non PTH to PTH hole D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 53 of 54 A B C D E Version Change List ( P I R List ) for HW Circuit Item Page# 68 69 70 71 72 73 Title 20 11 25 33 18 18 Date SB 03/06 NB 03/06 LAN 03/06 LAN 03/06 HDMI 03/07 HDMI 03/07 Request Owner HW HW HW HW HW HW Issue Description Rev Solution Description To solve can not power on if use CPU with single core 0.4 0.4 0.4 Stuff Q144, R1056, R1057, C1077 and reserve R1067 0.4 Stuff R544 0.4 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm 0.4 Reserve ohm and stuff common choke 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Compal Secret Data Compal Electronics, Inc Title Stuff R83 To support VariBright feature To reduce power consumption in S3 mode To reduce power consumption in S3 mode To pass HDMI test For EMI request Security Classification 2007/08/02 Issued Date C HW Changed-List History-2 Date: B 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Add R1085 and R1086 D Rev 0.4 LA-4111P Sheet Friday, March 07, 2008 E 54 of 54 ... 42 LED0 38 LAN_ACTIVITY# MDIP0 MDIN0 MDIP1 MDIN1 NC NC NC NC 11 12 LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1- NC CKXTAL1 CKXTAL2 R1061 15K_0402_5% 23 24 LAN_DO LAN_DI LAN_SK_LAN_LINK# LAN_CS HSIP... 15 CLKREQ_LAN# 25 CLKREQB 11,14,19,26,27,32,33 PLT_RST# 27 PERSTB R1060 1K_0402_1% HSIN 17 18 2.49K_0402_1% 20 LAN_PCIE_WAKE# ISOLATEB LAN_X1 LAN_X2 ISOLATEB 46 RSET 26 28 LANWAKEB ISOLATEB 41... DO DI SK CS +3V_LAN Q144 SI2301BDS-T1-E3_SOT23-3 2 G LAN_DO LAN_DI LAN_SK_LAN_LINK# LAN_CS U17 R1057 33 LAN_POWER_OFF @ AT93C46-10SI-2.7_SO8 0_0402_5% 0.1U_0402_16V4Z 1 R1058 Place Close to Chip