5 D C B 01.Block Diagram 02.POWER TREE 03.Power On/Off&Reset Timing 04.Power Sequence map 05.T30 Core & Fuse 06.T30 SYS IF 07.T30 GMI IF 08.T30 DDR 09.T30 DSI/CSI,CAM 10.T30 LCD 11.T30 HDMI,VGA 12.T30 BB,UART 13.T30 AUDIO 14.T30 USB,HSIC,ICUSB 15.T30 SDMMC,eMMC 16.T30 PCIe 17.T30 NC 18.Boot Straps 19.DDR3L 20.LCD data EMI filter 21.LCD panel power 22.eMMC,SDIO I/F 23.Sensor 24.Debug Connector 25.Hall 28.NUVOTON NPCE795L-1 30.EC description 31.SMBus tributaries 32.I/O Connector 33.TP&IO_CON(MB) 34.Coin cell 35.Camera power 36.Camera ISP & Connector 37.Codec_ALC5631Q-VE 38.DSP_FM34 39.Audio Conn 40.HW_RF_Interface 41.WiFi+BT combo II 43.BCM4751 GPS 44.SW CON 46.HDMI Conn 47.EMC 48.Srew Hole 49.DC_JACK & BAT CON 50.Power Sequenc Logic 51.Power_Latch 52.LVDS transmitter_30 53.LCD panel connector_30 a54.TP&IO_Block Diagram a55.TP&IO_Conn&SIM&SD a56.TPIO_ATMXT768EXES a57.TP&IO_TP CON a58.TP&IO_POWER a59.TP&IO_RST_SW 63.ALS_LSC3010 81_PW_+5VSUS_+3VSUS_TPS51125A 86_PW_2.85V&VDD_5V0_SYS 89_PW_Charger(BQ24745) 90_PW_A/D_IN 91.PMU-TPS65911 1/3 92.PMU-TPS65911 2/3 93.PMU-TPS65911 3/3 95.Force_off_recovery 96.Low_Low_BAT# 97.PWR_SW# Selection 99.HISTORY 1.0 ME370T (Nakasi) 2012/02/08 Front Camera module Rear Camera module Aptina 1040 D OV5650 MIPI_CSIB_1V2 Antenna MIPI_CSIA_1V2 CAM_I2C_1V8 HDMI DDC_I2C 5V0 Micro HDMI LCD Panel Transmitter LVDS Audio DSP I2S CODEC HEADSET JACK AICHI AMI304 CAM_I2C_1V8 Gyro sensor Invensense MPU-6050 Controls 32.768KHz PWR_I2C_1V8 Gen1_I2C_1V8 I2S_1V8 ALC5642 Tegra T30L Kai PWR_I2C_1V8 Speaker DMIC KNOWLES SPM0423HD4H-WB E-COMPASS PMIC OnSemi NCT72 DDR3L 256M x8 x4pcs 1333(667MHz) DDR3L x 32_1V35 HSMMC x8_1V8 eMMC 8GB Button FPC GEN2_I2C_3V3 ELAN JTAG_1V8 UART_4_1V8 I/O Board & TP EXTERNAL SD SCOKET PWR_I2C_1V8 Charger SMB347 USB Conn USB_1_3V3 SDIO_1_1V8 UART_3_1V8 32.768KHz Power Button Volume Up & Down Reset Button Debug Port GEN2_I2C_1V8 Battery Gauge C Thermal Sensor XTAL 12MHZ Internal D MIC Touch screen XTAL 32.768KHz MAXIM MAX77663 FM34 EXT MIC XTAL 27.12MHz LSC3010 GEN1_SMB_3V3 HEADSET Light sensor CAM_I2C_1V8 LCD_RGB_1V8 TI SN75LVDS83B NFC NXP PN65 CAM_I2C_1V8 EC NUVOTON NPCE795LA0DX B Antenna WIFI + BT Azurewave AW/NH-665 XTAL 37.4MHz USB_3_3V3 Docking USB Port TCXO 26MHz Gen1_I2C_1V8 USB*3 , Line out , Mic In , DC Jack 32.768KHz Docking UART_2_1V8 Antenna GPS Broadcom BCM4751 A A Title : 01.Block Diagram Engineer: ASUSTeK COMPUTER INC EPAD Size Project Name C Date: Richard Lin Rev ME370T Sheet Friday, March 02, 2012 2.0 of 60 page 52 PMIC ME370T (Nakasi) MAX77663 Power Tree IN_LDO2 LDO2 IN_LDO3/5 LDO3 VDD_PMU_LDO2_2V8 T30 2.8V 150mA, PMIC VDD_DDR_RX VDD_PMU_LDO3_2V8 page 20 2.8V 300mA, PMIC VDD_PMU_LDO5 LDO5 page 31 2.8V 300mA, PMIC USB Conn VDD_USB1_VBUS Dock Conn +3VSUS_CPU Charger DOCK_5V VBATT U1 page T30 Power SW NCT352 Battery D VDDIO_CAM Camera VDDIO Power Source page 49 VCORE_EMMC_S 200mA for eMMC VCC D VDD_FUSE VDD_1V8_GEN_CPU T30 SMB347 T30 T30 VDD_3V3_GMI T30 Power SW NCT352 AVDD_USB page 26 VDDIO_PEX_CTL page 48 Buck-Boost 3.3V 2A TPS63020 page 48 VDD_5V0_SYS Boost RT9276GQW 5V 1A page 22 U30 page 29 LDO S-1167 page 26 MAX77663 MBATT, MON, GPIO_INA & AVSD page 26 T30 CORE 1.2V 3A, PMIC VDD_ALS for Hall Sensor, ALS VDD_GYRO for Gyro VDD AVDD_ECOM for E-compass AVDD WiFi_BT_VCC_3V3 page 26 page 26 IOVCC_30 page 27 for Wifi/BT Module VDDIO_GYRO for Gyro VLOGIC DVDD_ECOM for E-compass DVDD for Audio Codec DBVDD VDD_1V8_CDC CPVDD page 41 VDD_CORE GPS_VDD_BAT_3V3 for GPS 1.2V, 2.5A, Terga 1.8V 2.0A, PMIC LDO6 VDD_PMU_LDO4_1V2 T30 T30 3/1.8V 150mA, PMIC page 27 PMIC VDD_RTC IN_LDO0/1 VDDIO_SDMMC1 U27 LDO0 LDO1 AVDD_CAM1 S-1132 Camera AVDD 2.8V 300mA IN_LDO7/8 CAM1_LDO_EN(T30 KB_ROW6) LDO7 U28 AVDD_VCM S-1132 CAMERA AF VCM LDO8 2.8V 300mA VDD_PMU_LDO0_1V0 T30 1.0V 150mA, PMIC page 27 page 44 VDD_SPK DACREF_CDC VDD_1V8_DMIC VDD_DDR_HS page 41 150mA, PMIC No usage VDD_PMU_LDO7_1V2 T30 1.2V 450mA, PMIC T30 1.2V 300mA, PMIC page 43 GPS_VDD_IO_1V8 for GPS NFC_PVDD for NFC AVDD_DSI_CSI AVDD_PLLA_P_C AVDD_PLLM page 50 AVDD_PLLU_D Codec Speaker Amp PMIC AVDD_PLLX NFC VBAT WiFi_BT_VDDIO_1V8 for Wifi/BT Module page 44 VDD_PMU_LDO8_1V2 T30 NFC_VBAT AVDD_CDC_F VDD_PMU_LDO1 CAM2_LDO_EN(T30 KB_ROW8) A VCP_CDC for DMIC VDD MAX77663 1.2V 150mA, PMIC VDD_PMU_LDO6_3V_1V8 DCVDD page 52 1.35V 1.5A, PMIC VDB_CDC B AVDD +1.35V IN_LDO4/6 LDO IOVCC VDD_1V8_GEN LDO4 page 31 VDDIO_HSMMC for LVDS Transmitter page 41 VDD_CPU SD3 LDO for eMMC VCCQ page 22 SD2 page 31 page 20 AVDD_USB_PLL CORE_PWR_REQ 1.05V, 6.1A, Terga (Tj=90, 1.3GHz) VDD_1V2_SOC SD1 B for LVDS Transmitter VDD_LVDS_PLL_30 PMIC T30 CPU T30 Load SW PMOS PLLVCC page 50~52 1.05V 6A, PMIC Q2 page 14 VDD_LVDS_F_30 page 29 VDD_5V0_SYS enable VDD_1V0_GEN C VDDIO_SDMMC3 LVDSVCC page 25 SD0 for LCD Panel VDD_LVDS_30 for Touch Sensor TP_3V3 3.3V 150mA EN_5V0_SBY(T30 GMI_AD11) VCC_LCD3V3 VCC VDD_LVDS_30 VDDIO_SDMMC4 T30 EN_VDD_PNL (T30 LCD_M1) EN_3V3_SYS(PMU GPIO3) Internal Usage Power SW NCT352 +3VSUS VDD_IO_AUDIO T30 U8 page 21 VDD_PNL VDDIO_UART T30 TBD (no use) C VDDIO_BB T30 for Thermal Sensor T30 VDDIO_LCD T30 VCORE_TEMP VCC_LED VDDIO_CAM T30 EN_AVDD_USB (MAX77663 GPIO2) page 21 VDDIO_SYS T30 U14 page 14 VDD_AC_BAT (VPH_PWR_CHGR) AVDD_OSC EN_VDD_FUSE (T30 LCD_PWR1) MAX77663 A VDDIO_DDR Internal Usage Max 710mA GPIO_INB DRAM Chip 256Mb x8bits x4pcs page 19 170mA x4, each DRAM chip VDD_DDR3L for DDR3L VDD VDDQ_DDR3L for DDR3L VDDQ Title : 02.POWER TREE ASUSTeK COMPUTER INC EPAD Size Project Name Richard Lin Rev ME370T Custom Date: Engineer: Thursday, March 01, 2012 Sheet 2.0 of 60 TF300T_T3 Power On/Off A/D_IN AC_BAT_SYS D D 3.3V AC_OK 3.3V +3VA_PAL(PU8805) 3.3V PWR_SW# 3.3V +3VA_EC (PU8806) AC_BAT_SYS EC to PU8100 P_+5VSO_EN_10 (Q7900) 5V +5VSUS (PU8100) 1.8V VDD_1V8_PMU_VRTC(PMU VRTC) SW# to PMU 3.3V PMU_ONKEY# C C EN_5V0_SBY(PMU GPIO0) 1.8V VDD_5V0_SBY(PQ9106, 2A) PMU to T3 VDD_RTC(PMU LDO4) VDD_1V8_GEN(PMU SWIO) PMU to T3 VDD_CORE(PMU SW1) PMU to T3 VDD_PMU_LDO7(T3 AVDD_PLLx) PMU to T3 CLK_32K_IN(PMU) T3 XTAL System Clock(T3 26MHz) 5V 1.8V 1.2V 1.1V 5.0V EN_VDD_1V35(EN_DDR, PMU GPIO7) 1.8V +1.8V B B 1.35V +1.2V(for DDR3L 1.35V) 5.0V PMU to PU8100 EN_3V3_SYS(PMU GPIO6) T3 to Q1603 1.8V EN_3V3_EMMC(T3) 2.85V VCORE_eMMC_S(Q1603) A PMU to T3 VDD_DDR_HS(PMU LDO8) 1.0V PMU to T3 VDD_SATA(PMU LDO2) PMU to T3 VDD_PEX(PMU LDO1) PMU to T3 SYS_RESET#(PMU) T3 to PMU CPU_PWR_REQ(TERGA) 1.05V 1.05V (EEPROM OFF) 1.8V 1.8V A 1.0V PMU to T3 VDD_CPU(PMU SW) +1.05VS/+1.2VS/+1.5VS OTHERS (PMU LDOs, Switched Rails) Title :Timing ASUSTeK COMPUTER INC EPAD Size Project Name Custom Date: Thursday, March 01, 2012 Engineer: Richard Lin Rev ME370T Sheet 2.0 of 60 PWR_SW# TF300T T3 power on/off map 1201 Button +3VSUS EN_VDD_FUSE P-MOS SI2305DS EN +3VSUS T30 VDD_FUSE CAM1_LDO_EN VDD_PNL(+3VSUS) P_+3VA_EN EN_VDD_PNL D P-MOS SI2305DS EN LCD panel VCC_LCD3V3 Adapter +3VSUS +3V_PAL LDO A/D IN AC_BAT_SYS Buck Boost EN_3V3_COM BAT Charger BQ24740 P_+3VA_EN Power Latch +3VA_EC LDO SW1 +3VSUS CAM2_LDO_EN P-MOS SI2305DS EN WiFi_BT_VCC_3V3 LDO 2.85V RT9193-2HGU5 EN AVDD_CAM1 LDO 2.85V RT9193-2HGU5 EN AVDD_VCM D WIFI+BT +3VSUS(+3VSO1) TI TPS51125ARGER EN1 EN2 SW2 +5VSUS(+5VSO1) P_+5VSO_EN_10 EN_3V3_SYS C N-MOS IRFHS8342TRPBF EN ** VDD_5V0_SBY EN_5V0_SYS N-MOS IRFHS8342TRPBF EN VDD_5V0_SYS +3VA LDO Battery Pack EN_5V0_SBY DOCK_IN +3VSUS EN_VDD_SOC BAT EN_VDD_BL VDD_1V8_GEN EN_1V8_CAM P-MOS SI2305DS EN VCC_LED P-MOS SI2305DS EN VDDIO_CAM P-MOS SI2305DS EN +5VSUS_DOCK P-MOS SI2305DS EN VCC_TCH P-MOS SI2305DS EN VDD_1V2_SOC LCD panel backlight +3VSUS(+3VSO1) B Sequence: > > > > > > > > > > > > > > > > > > > VDD_1V8_GEN T30 SW VDD_CPU VDD_CPU VDD_1V2_GEN VDD_CORE VCC2 SW2 +1.2V A VDD_1V8_GEN VCCIO SWIO VDD_1V8_GEN VCC7 VRTC VDD_1V8_PMU_VRTC VCC6 LDO1 LDO2 VCORE_eMMC_S(core power) VDD_SD_S LDO3 VDDIO_SDMMC1 *** VCC4 B VDD_SATA VDD_RTC VDD_RTC LDO5 VDD_PMU_LDO5 VDDIO_SDMMC1(3.3V) LDO7 GPIO4 GPIO5 PWRDN(power down) HOT_RST PWRON @ LDO4 LDO6 VCC3 VDD_CELL_LCL AP_OVERHEAT# HOT_RST PMU_ONKEY# CPU_PWR_REQ CORE_PWR_REQ SYS_RESET_N PWR_INT_N CLK_32K_IN SW1 VBACKUP @ CPU_PWR_REQ CORE_PWR_REQ SYS_RESET# PWR_INT# CLK_32K_IN VCC1 VDDIO VDD_1V8_PMU_VRTC VDDIO_HDMI_CONN_AIO V5IN VCC5 VDD_5V0_SYS P-MOS SI2305DS EN C EN2 EN1 SLEEP NRESPWRON PWR_INT# CLK32KOUT VDD_5V0_SBY *** HDMI_VBUS_EN_AIO VDD_PMU_LDO6 VDD_PMU_LDO7(T3 AVDD_PLLx) LDO8 VDD_DDR_HS GPIO0 GPIO2 GPIO6 GPIO7 EN_5V0_SBY EN_VDD_SOC EN_3V3_SYS EN_DDR EEPROM +3VSUS +1.2V HVDD_PEX VDD_FUSE AVDD_DSI_CSI(1.2V) * *** AVDD_PLLx VDD_DDR_HS AVDD_USB VDD_DDR_RX AVDD_HDMI VDDIO_GMI VDD_PEX_CTL VDDIO_LCD VDDIO_DDR HVDD_PEX(3.3V) VPP_FUSE(3.3V) A time slot duration: 2ms 5 需需需需 02004-00120000 C.S T30-R-A3 FCBGA-728 BOM MAX77663 LDO4 VDD_RTC VDD_FUSE /@ U1 C IN DIS NCT3521U N/A 0720 VDD_FUSE_DISABLE C24 0.1U6.3VX5RC1K N/A OUT GND EN R2 300R1F N/A VDDIO_UART Unmount R3 100KR1J /@ 10 EN_VDD_FUSE R4 100KR1J N/A 0720 default disable FUSE function B A GND_001 GND_002 GND_003 GND_004 GND_005 GND_006 GND_007 GND_008 GND_009 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054 GND_055 GND_056 GND_057 GND_058 GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_068 GND_069 GND_070 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 1 VDD_RTC_0001 VDD_RTC_0002 V22 V23 VDD_RTC 1 1 N/A C5 4.7U6.3VX5RC2M /@ C29 4.7U6.3VX5RC2M N/A C9 4.7U6.3VX5RC2M N/A C11 8P25VNPOC1J VDD_CPU 1 0.9~1.0V (0.9 ~ 1.0V) VDD_CPU_01 VDD_CPU_02 VDD_CPU_03 VDD_CPU_04 VDD_CPU_05 VDD_CPU_06 VDD_CPU_07 VDD_CPU_08 VDD_CPU_09 VDD_CPU_10 VDD_CPU_11 VDD_CPU_12 VDD_CPU_13 VDD_CPU_14 VDD_CPU_15 VDD_CPU_16 VDD_CPU_17 VDD_CPU_18 VDD_CPU_19 VDD_CPU_20 VDD_CPU_21 VDD_CPU_22 H10 J10 J8 K8 K9 M7 M8 M9 N8 N9 P14 P15 P16 P17 R14 R17 T14 T17 U14 U15 U16 U17 VDD_CPU 0906 NV add 1220 add VDD_CORE 1 N/A C14 22U6.3VX5RC5M N/A C17 22U6.3VX5RC5M VDD_CORE 1 1 1 1 1.0~1.2V N/A C15 0.1U6.3VX5RC1K N/A C12 0.1U6.3VX5RC1K N/A C20 0.1U6.3VX5RC1K N/A C22 4.7U6.3VX5RC2M N/A C18 4.7U6.3VX5RC2M N/A C26 4.7U6.3VX5RC2M N/A C27 4.7U6.3VX5RC2M N/A C28 4.7U6.3VX5RC2M N/A C25 33P25VNPOC1J 1 C (1.0 ~ 1.2V) VDD_CORE_01 VDD_CORE_02 VDD_CORE_03 VDD_CORE_04 VDD_CORE_05 VDD_CORE_06 VDD_CORE_07 VDD_CORE_08 VDD_CORE_09 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_17 VDD_CORE_18 VDD_CORE_19 VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28 M13 M15 M17 M19 N12 N14 N16 N18 N7 P13 P19 R12 R18 R7 R8 R9 T13 T19 T8 T9 U18 V13 V15 V17 V19 W14 W16 W18 VDD_CORE 0614 remove VDD_CPU_SENSE Note: Place the 0402 shunts close to Tegra side VDD_CPU_SENSE_T30 GND_CPU_SENSE_T30 AB12 VDD_CPU_SENSE_T30 AB15 GND_CPU_SENSE_T30 VDD_CORE_SENSE_T30 VVDD_CPU_SENSE VGND_CORE_SENSE VDD_CORE_SENSE GND_CORE_SENSE 51 /@ GND_CPU_SENSE GND_CPU_SENSE 51 PJP2 SHORT_PIN B PJP3 SHORT_PIN /@ VDD_CORE_SENSE P05 P05 GND_CORE_SENSE_T30 VDD_CPU_SENSE MAX77663 SD0 sense Short Copper GND_CPU_SENSE VDD_CPU_SENSE P05 P05 Short Copper VDD_CPU_SENSE PJP1 SHORT_PIN /@ VDD_CORE_SENSE 51 MAX77663 SD1 sense /@ GND_CORE_SENSE GND_CORE_SENSE 51 PJP4 SHORT_PIN AB16 AA23 W23 VDD_CORE_SENSE_T30 W22 GND_CORE_SENSE_T30 VDD_FUSE (3.3V) VPP_FUSE (3.3V) VPP_KFUSE AB8 AA4 VPP_KFUSE R5 10KR1J N/A R6 1KR1J /@ C30 0.1U6.3VX5RC1K N/A A Unmount Title : T30 Core & Fuse Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: N/A C16 4.7U6.3VX5RC2M N/A C19 4.7U6.3VX5RC2M /@ C21 4.7U6.3VX5RC2M /@ C23 0.1U6.3VX5RC1K VDD_CORE T30L-R-P-A3 T30 D Unmount N/A C2 0.1U6.3VX5RC1K N/A C4 0.1U6.3VX5RC1K N/A C6 0.1U6.3VX5RC1K N/A C8 4.7U6.3VX5RC2M N/A C7 4.7U6.3VX5RC2M N/A C3 4.7U6.3VX5RC2M N/A C10 4.7U6.3VX5RC2M N/A C13 4.7U6.3VX5RC2M (1.0 ~ 1.2V) A2 A29 AC11 AC14 AC17 AC2 AC20 AC23 AC26 AC29 AC5 AC8 AF11 AF14 AF17 AF2 AF20 AF23 AF26 AF29 AF5 AF8 AJ1 AJ11 AJ14 AJ17 AJ2 AJ20 AJ23 AJ26 AJ29 AJ30 AJ5 AJ8 AK2 AK29 B1 B11 B14 B17 B2 B20 B23 B26 B29 B30 B5 B8 E11 E14 E17 E2 E20 E23 E26 E29 E5 E8 H11 H14 H17 H2 H20 H23 H26 H29 H5 H8 L2 L23 L26 L29 L5 L8 M12 M14 M16 M18 N13 N15 N17 N19 P12 P18 P2 P23 P26 P29 P5 P8 R13 R15 R16 R19 T12 T15 T16 T18 U13 U19 U2 U23 U26 U29 U5 U8 V12 V14 V16 V18 W12 W13 W15 W17 W19 Y2 Y23 Y26 Y29 Y5 Y8 VDD_CORE R1 0R2J 1.2V 1/22 CORE POWER MAX77663 SD1(3A) +3VSUS_CPU VDD_CPU VDD_CPU VDD_1V2_SOC 0622 N/A C1 0.1U6.3VX5RC1K U2A MAX77663 SD0(6A) D 1.0~1.2V 0906 NV add 0.9~1.0V VDD_1V0_GEN VDD_RTC 0620 VDD_PMU_LDO4_1V2 1.2V Project Name Richard Lin Rev ME370T Saturday, March 24, 2012 Sheet 2.0 of 60 MAX77663 LDO8 1.2V VDD_PMU_LDO8_1V2 VDD_PMU_LDO8_1V2_CPU 1.2V VDD_PMU_LDO8_1V2_CPU AVDD_PLLA_P_C 1.2V VDD_PMU_LDO8_1V2_CPU AVDD_PLLU_D 1.2V Remove AVDD_PLLX 1.2V Remove AVDD_PLLM Power from MAX77663 MAX77663 LDO8 1.2V to T30 AVDD_PLLx MAX77663 SD2 1.8V (VDD_1V8_PMU_DCDC2) to VDD_1V8_GEN Signal to & from MAX77663 R8 1.8V VDD_1V8_GEN N/A 0R3J 1.8V VDD_1V8_GEN_CPU VDD_1V8_GEN_CPU SYS_RESET# from MAX77663 nRSTIO, check reset circuit(p.32) and PMU side VDDIO_SYS L7 D MAX77663 SD2 (2A) 1.8V VDD_1V8_GEN_CPU N/A PWR_INT# from MAX77663 nIRQ, check PU resister in PMU side(100k PU to VDD_1V8_GEN) AVDD_OSC D CORE_PWR_REQ to MAX77663 EN1, check PU resister in PMU side(100k PU to VDD_1V8_GEN) 30Ohm/100Mhz VDD_1V8_PMU_DCDC2 CPU_PWR_REQ to MAX77663 EN2, check PD resister in PMU side(100k PD) 0906 NV change U2B CLK_32K_IN from MAX77663 GPIO4, check PU resister in PMU side(100k PU to VDD_1V8_GEN) 2/22 OSC, PLL & SYS F30 AVDD_OSC AVDD_OSC XTAL_IN T30 XTAL_IN T29 XTAL_OUT R9 N/A 2MR2J VDD_PMU_LDO7 R10 0R1J N/A AD7 /@ AVDD_PLLE_no_use AA22 2 C32 12P50VNPOC2J N/A USB&DSI VDDIO_SYS VDDIO_SYS C AVDD_PLLU_D2 1.05V AVDD_PLLE PCIE&SATA R11 1KR1J N/A R12 1KR1J N/A SHORT_PIN PWR_I2C_SCL PWR_I2C_SDA SYS_RESET_N PWR_INT_N PUPD B Deep Sleep PinState PUPD After Wake COL0 UP 100K PU Config Reset COL1 UP 100K PU Config Reset COL2 UP 100K PU Config Reset COL3 UP 100K PU Config Reset COL4 UP 100K PU Config Reset COL5 UP 100K PU Config Reset COL6 UP 100K PU Config Reset COL7 UP 100K PU Config Reset ROW0 DOWN 100K PD Config Reset ROW1 DOWN 100K PD Config Reset ROW2 DOWN 100K PD Config Reset ROW3 DOWN 100K PD Config Reset ROW4 DOWN 100K PD Config Reset ROW5 DOWN 100K PD Config Reset ROW6 DOWN 50K PD Config Reset ROW7 DOWN 50K PD Config Reset ROW8 DOWN 50K PD Config Reset ROW9 DOWN 50K PD Config Reset ROW10 DOWN 50K PD Config Reset ROW11 DOWN 50K PD Config Reset VDDIO_SYS VDDIO_SYS_1 VDDIO_SYS_2 CORE_PWR_REQ CPU_PWR_REQ SYS_CLK_REQ CLK_32K_IN CLK_32K_OUT PWR_I2C_SCL PWR_I2C_SDA N28 SYS_RESET# PWR_INT# M22 1227 R0732 100K -> 10K VDDIO_SYS PWR_I2C_SCL PWR_I2C_SDA SYS_RESET# Unmount R16 1KR1J N/A 26,27,49,50 26,27,49,50 R14 100KR1J N/A 20,32,50 JTAG_TRST# PWR_INT# 0229 NV change 10k -> 100k 50 CORE_PWR_REQ CPU_PWR_REQ N25 R24 T23 CORE_PWR_REQ 14,50 CPU_PWR_REQ 50 CLK_32K_IN CLK_32K_OUT R22 U27 CLK_32K_IN CLK_32K_OUT R15 100KR1J N/A 50 40,41,43 POR VDDIO_SYS (1.8/3.3V) 1.8V M24 N27 Short Copper K29 K30 C32 & C33 change to 12pF TXC/7V12000011 Change (1.1V) (1.05V) 1.2V 0721 DRAM KB_COL00 KB_COL01 KB_COL02 KB_COL03 KB_COL04 KB_COL05 KB_COL06 KB_COL07 KB_ROW00 KB_ROW01 KB_ROW02 KB_ROW03 KB_ROW04 KB_ROW05 KB_ROW06 KB_ROW07 KB_ROW08 KB_ROW09 KB_ROW10 KB_ROW11 KB_ROW12 KB_ROW13 KB_ROW14 KB_ROW15 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG_RTCK ROW12 DOWN 50K PD Config Reset THERM_DN THERM_DP ROW13 DOWN 50K PD Config Reset OWR ROW14 DOWN 50K PD Config Reset HDMI_CEC ROW15 DOWN 50K PD Config Reset TEST_MODE_EN J30 N26 V25 R26 W26 R30 P27 N29 T26 M23 V27 M28 N24 N30 T24 T25 R27 M26 R25 M27 N23 V28 M25 V26 PCB_ID2 PCB_ID5 0802 ID5 PCB_ID3 KB_ROW0 KB_ROW1 KB_ROW2 SNN_KB_ROW3 SNN_CAM_I2C_SEL0 SNN_CAM_I2C_SEL1 CAM1_LDO_EN CAM2_LDO_EN CAM3_LDO_EN SNN_CAM1_AF_PWDN* SNN_CAM2_AF_PWDN* CAM3_AF_PWDN* SNN_KB_ROW12 SNN_KB_ROW13 SNN_KB_ROW14 SNN_KB_ROW15 PCB_ID4 PCB_ID0 PCB_ID1 CAM1_LDO_EN NC CAM2_LDO_EN LL_BAT_T30 1V8_O_LID# T27 R29 T28 R23 T22 V24 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRT_N JTAG_RTCK M30 M29 THERMD_N THERMD_P KB_COL0 KB_COL1 KB_COL2 KB_COL3 SNN_KB_COL4 SNN_KB_COL5 SNN_KB_COL6 SNN_KB_COL7 PWR_SW#_BUTTON_R 33 KB_ROW0 32,33 B NFC_GPIO4_R PCBID ID1 ID0 0 AW-NH660 44 CAM1_LDO_EN 31 ROW10, 11 for charger control CAM2_LDO_EN 31 SMB347_USB51HC 33 SMB347_SUSP 33 TEMP_ALERT#_KAI LL_BAT_T30 1V8_O_LID# NFC_VEN 44 BCM4330 VDD_1V8_GEN_CPU TEMP_ALERT#_KAI form Thermal Sensor 25 PCB_ID0 R21 /@ 0R1J JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# JTAG_RTCK 24 24 24 24 24 24 100KR1J R18 100KR1J R17 /@/PCBID/WIFI /PCBID/WIFI PCB_ID1 100KR1J R19 100KR1J R20 /PCBID/WIFI /@/PCBID/WIFI 100KR1J R22 100KR1J R27 /PCBID/GPS /@/PCBID/GPS 100KR1J R23 100KR1J R25 /@/PCBID/PROJECT /PCBID/PROJECT Unmount JTAG_TRT_N PCB_ID2 Unmount THERMD_N THERMD_P 26 26 PCB_ID3 R26 0R1J N/A Unmount PCB_ID4 100KR1J R31 100KR1J R28 /@/PCBID/PROJECT /PCBID/PROJECT Unmount PCB_ID5 T30L-R-P-A3 N/A A BCM4330 AW-NH665 33 R24 100KR1J N/A TEST_MODE_EN Pin to Pin 26 N22 R28 for ME370T SR3 PCBID ID2 = for BCM47511 ID2 = for BCM4751 Unmount Unmount AC18 PCBID ID5 ID4 ID3 0 CPU_PWR_REQ PD 100k in KAI design VOL_UP_BUTTON 32 VOL_DWN_BUTTON 32 PJ1 (1.1V) AVDD_PLLU_D remove PLL_S_PLL_LF 2 C38 0.1U6.3VX5RC1K N/A 1.2V NC37 CPU AA8 AVDD_PLLU_D C (1.1V) AVDD_PLLM VDDIO_SYS C37 0.1U6.3VX5RC1K N/A 1.2V Change C33 12P50VNPOC2J N/A AVDD_PLLU_D (1.1V) H12 J13 AUDIO&PERIPHERAL AVDD_PLLA_P_C AVDD_PLLX X1 change to 12MHz XTAL J12 (1.1V) 1.2V Remove C35, C36 for AVDD_PLLX & AVDD_PLLM C34 0.1U6.3VX5RC1K N/A H13 AVDD_PLLA_P_C X1 N/A 12MHz 1 C31 4.7U6.3VX5RC2M N/A 2 AVDD_PLLA_P_C Change 1 XTAL_OUT_R AVDD_OSC 1.1V 1.2V R1.0 R1.2 XTAL_OUT PMU 1.8V (1.8V) 100KR1J R30 100KR1J R29 /@/PCBID/PROJECT /PCBID/PROJECT A Title : 01.Block Diagram Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Thursday, March 22, 2012 Sheet 2.0 of 60 R35 3.3V +3VSUS 0R3J N/A 3.3V +3VSUS_CPU +3VSUS_CPU VDD_3V3_GMI TPS63020 buck-boost D D U2D N/A C39 10U6.3VX5RC3M N/A C40 0.1U6.3VX5RC1K VDD_3V3_GMI 4/22 GMI (1.8/3.3V) VDD_3V3_GMI C1 C2 D1 VDDIO_GMI_1 VDDIO_GMI_2 VDDIO_GMI_3 3.3V POR VDDIO_GMI PUPD PUPD After Wake AD00 None Z Disable Reset AD01 None Z Disable Reset AD02 None Z Disable Reset AD03 None Z Disable Reset AD04 None Z AD05 None Z Disable Reset AD06 None Z Disable Reset AD07 None Z Disable Reset AD08 None Z Disable Reset Disable GMI_A16 GMI_A17 GMI_A18 GMI_A19 Reset GMI_CS0_N GMI_CS1_N GMI_CS2_N GMI_CS3_N GMI_CS4_N GMI_CS6_N GMI_CS7_N AD09 None Z Disable Reset AD10 DOWN 100K PD Disable Reset AD11 DOWN 100K PD Disable Reset AD12 None Z Disable Reset AD13 None Z Disable Reset AD14 None Z Disable Reset GMI_RST_N GMI_WAIT GMI_WP_N AD15 None Z Disable Reset GMI_IORDY A16 None Z Config Hold A17 None Z Config Hold A18 None Z Config Hold Z Config Hold CS0 UP 100K PU Config Reset None CS1 UP 100K PU Config Reset CS2 UP 100K Disable Reset CS3 UP 100K Disable Reset CS4 UP 100K PU Config Reset CS6 UP 100K PU Disable Reset CS7 UP 100K PU Config Reset None Disable Reset None ADV_N CLK Disable Reset RST_N UP 100K Disable Reset WAIT UP 100K PU Disable Reset WP_N UP 100K PU Config Reset IORDY UP 100K PU Config Reset OE_N None Disable Reset WR_N None Disable Reset DQS None Z Disable Reset GMI_ADV_N GMI_CLK GMI_OE_N GMI_WR_N GMI_DQS NAND_D0 NAND_D1 NAND_D2 NAND_D3 NAND_D4 NAND_D5 NAND_D6 NAND_D7 LCD_BL_PWM NC TS_WAKEUP# TS_IRQ# TS_RESET#_3V3 H4 J6 C4 J3 NC NC NC NC J4 K7 F6 A3 D6 J5 J7 NC NC NC NC LCD1_BL_PWM PWM_3D LCD1_BL_EN EN_VDD_BL1 TS_IRQ* TS_RESET* CARD_PEX_RST# NAND_D0 NAND_D1 NAND_D2 NAND_D3 NAND_D4 NAND_D5 NAND_D6 NAND_D7 LCD_BL_PWM 18 18 18 18 18 18 18 18 23 TS_WAKEUP# TS_IRQ# 29,48 29 TS_RESET#_3V3 Boot Straps PCBID ID7 ID6 0 1 1 ALC5631Q WM8903 ALC5642 Reserved 29 TS_WAKEUP# for TS 5V enable (PD 1M on page.48) PCBID ID8 Reserved SPI4_SCK SPI4_DOUT SPI4_DIN SPI4_CS1 PCB_ID6 VDD_3V3_GMI 100KR1J R37 100KR1J R36 /@/PCBID/CODEC /PCBID/CODEC Unmount FTM_MODE# SNN_GMI_CS0 PCB_ID6 CHARGER_STAT PCB_ID7 PCB_ID8 LCD_LANDSCAPE SNN_TP_IRQ# SNN_GMI_CS6 WW_WAKE* PCB_ID7 SNN_GMI_CS2 100KR1J R38 100KR1J R39 /PCBID/CODEC /@/PCBID/CODEC Unmount PCB_ID8 100KR1J R40 100KR1J R41 /@/PCBID /PCBID C E6 NAND_ALE A4 NAND_CLE NAND_ALE NAND_CLE SNN_GMI_RST* RECOVERY_MODE* MFG_MODE_R D4 B4 D5 18 LCD_BL_PWM 18,26 R43 N/A 330KR1J NAND_CLE for AP thermal shut down in KAI C3 F2 G4 NAND_RE# NAND_WE# NAND_RE# NAND_WE# 18 18 G3 VDD_3V3_GMI VDD_3V3_GMI SNN_GMI_DQS R44, R45 (GEN2_I2C PU) placed on P.29 VDD_3V3_GMI GEN2_I2C_SCL GEN2_I2C_SDA G5 G7 GEN2_I2C_SCL GEN2_I2C_SDA GEN2_I2C_SCL GEN2_I2C_SDA 29 29 TS I2C A19 B PinState F8 G6 D3 E4 G2 D2 B3 G1 H6 F4 E7 F3 F5 F7 J2 F1 R316 1MR1J N/A C Deep Sleep GMI_AD00 GMI_AD01 GMI_AD02 GMI_AD03 GMI_AD04 GMI_AD05 GMI_AD06 GMI_AD07 GMI_AD08 GMI_AD09 GMI_AD10 GMI_AD11 GMI_AD12 GMI_AD13 GMI_AD14 GMI_AD15 FTM_MODE# T30L-R-P-A3 N/A T51 /@ tpc40t_np_68 B A A Title : T30 GMI IF Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Wednesday, March 21, 2012 Sheet 2.0 of 60 U2C 3/22 DDR3/LPDDR2 D 2.8V 1.35V MAX77663 LDO2 VDD_PMU_LDO2_2V8 VDD_DDR_RX from PMIC 1.0V DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 MAX77663 LDO0 VDD_PMU_LDO0_1V0 VDD_DDR_HS VDD_DDR_RX A27 (2.8/3.3V) VDD_DDR_RX from PMIC VDDIO_DDR 1 1 1 C N/A C41 0.1U6.3VX5RC1K N/A C43 0.1U6.3VX5RC1K N/A C44 4.7U6.3VX5RC2M N/A C42 4.7U6.3VX5RC2M N/A C45 4.7U6.3VX5RC2M N/A C46 10U6.3VX5RC3M N/A C47 10U6.3VX5RC3M N/A C48 10U6.3VX5RC3M VDD_DDR_HS E10 H9 DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 (1.00V) VDD_DDR_HS_1 VDD_DDR_HS_2 DDR_DQS0N DDR_DQS0P DDR_DQS1N DDR_DQS1P 1.0V DDR_DQS2N DDR_DQS2P 0503 DDR_DQS3N DDR_DQS3P DDR_A00 DDR_A01 DDR_A02 DDR_A03 DDR_A04 DDR_A05 DDR_A06 DDR_A07 DDR_A08 DDR_A09 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 C60 N/A 4.7U6.3VX5RC2M C61 N/A 4.7U6.3VX5RC2M C64 N/A 4.7U6.3VX5RC2M C67 N/A 4.7U6.3VX5RC2M 2 2 VDD_DDR_HS N/A C49 4.7U6.3VX5RC2M VDD_DDR_RX N/A C50 4.7U6.3VX5RC2M VDDIO_DDR 3.3V DDR_RAS_N DDR_CAS_N DDR_WE_N DDR_BA0 DDR_BA1 DDR_BA2 DDR_CS0_N DDR_CS1_N DDR_ODT0 DDR_ODT1 B DDR_CKE0 DDR_CKE1 DDR_CLK_N DDR_CLK DDR_RESET DDR_QUSE0 DDR_QUSE1 DDR_QUSE2 DDR_QUSE3 DDR_DQ[31 0] D24 B25 A25 D21 A24 A21 A22 B22 C15 A13 C12 B13 C13 A10 B10 C10 G22 D22 D25 F23 G21 E25 F24 F22 F13 G13 G10 D13 G9 F10 D10 F12 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 C22 D12 E22 G12 DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 B24 C24 DDR_DQS0N DDR_DQS0P B12 A12 DDR_DQS1N DDR_DQS1P E24 D23 DDR_DQS2N DDR_DQS2P E12 D11 DDR_DQS3N DDR_DQS3P D20 G15 A18 D14 B19 A16 C21 A15 D15 C16 E16 D18 E15 A19 B16 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 G18 D17 DDR_RAS_N DDR_CAS_N DDR_RAS_N DDR_CAS_N 19 19 D19 DDR_WE_N DDR_WE_N 19 F15 E21 F21 DDR_BA0_N DDR_BA1_N DDR_BA2_N DDR_BA0_N DDR_BA1_N DDR_BA2_N 19 19 19 19 19 19 D DDR_DM[3 0] F16 E19 DDR_CS0_N DDR_CS1_N DDR_CS0_N DDR_CS1_N D16 F18 DDR_ODT0_N DDR_ODT0_N 19 F19 E18 DDR_CKE0 DDR_CKE0 19 B18 C18 DDR_CLKN DDR_CLKP C19 DDR_RESET_N D27 D26 E9 F9 DDR_QUSE0 DDR_QUSE1 DDR_QUSE2 DDR_QUSE3 DDR_DQS0N DDR_DQS0P 19 19 DDR_DQS1N DDR_DQS1P 19 19 DDR_DQS2N DDR_DQS2P 19 19 DDR_DQS3N DDR_DQS3P DDR_A[14 0] 19 19 19 19 C VDDIO_DDR Unmount DDR_RESET_N 10KR1J R48 /@ 0906 NV change to UM B No Use No Use DDR_CLKN DDR_CLKP DDR_RESET_N 19 R49 0R1J 0R1J R52 R50 45.3R2F N/A /@ /@ 19 19 MAX77663 SD3(2A) (1.2/1.25/1.35/1.5) VDDIO_DDR_01 VDDIO_DDR_02 VDDIO_DDR_03 VDDIO_DDR_04 VDDIO_DDR_05 VDDIO_DDR_06 VDDIO_DDR_07 VDDIO_DDR_08 VDDIO_DDR_09 VDDIO_DDR_10 VDDIO_DDR_11 VDDIO_DDR_12 VDDIO_DDR_13 VDDIO_DDR_14 VDDIO_DDR_15 VDDIO_DDR_16 R51 45.3R2F N/A 0620 G16 G19 H15 H16 H18 H19 H21 H22 J15 J16 J18 J19 J21 J23 K22 K23 +1.35V VDDIO_DDR from PMIC VDDIO_DDR DDR_CLK_R_C DDR_COMP_PD B21 DDR_COMP_PU B15 DDR_COMP_PD 40.2R2F R54 VDDIO_DDR DDR_COMP_PU Unmount R53 40.2R2F N/A N/A C51 0.01U10VX7RC1K N/A T30L-R-P-A3 N/A A A Title : T30 DDR Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Wednesday, March 21, 2012 Sheet 2.0 of 60 0502 1.2V T30 VI MAX77663 LDO7 VDD_PMU_LDO7_1V2 AVDD_DSI_CSI T30 GPIO T30S pin VI_MCLK PRO_RST# BB AA1 VI_PCLK HDMI_VBUS_EN_OC# BB W5 VI_HSYNC VI_VSYNC EN_VDDIO_SD EN_VDD_MC BB BB PUPD W5 AA3 2 C52 0.1U6.3VX5RC1K N/A AVDD_DSI_CSI D VI_DO0 VI_DO1 VI_DO2 VI_DO3 VI_DO4 VI_DO5 VI_DO6 VI_DO7 VI_DO8 VI_DO9 VI_DO10 VI_DO11 C53 4.7U6.3VX5RC2M N/A BAT_IN_CPU# COMPASS_DRDY ALS_INT#_MB GS_INT LVDS_SHTDN# CAM_RST_2M EN_VDD_PNL DSP_RST# EN_VDD_FUSE EN_HVDD_PEX DSP_PWDN# SDMMC1_WP BB BB BB BB LCD CAM UART BB UART XX CAM AUDIO V4 AC11 AF6 AA9 AP18 AM14 AG33 V8 AM36 X AM16 D36 GPIO 0620 U2H 7/22 DSI & CSI (1.2V) AVDD_DSI_CSI CSI_CLKAN CSI_CLKAP 1.2V CSI_D1AN CSI_D1AP CSI_D2AN CSI_D2AP C CSI_CLKBN CSI_CLKBP CSI_D1BN CSI_D1BP CSI_D2BN CSI_D2BP DSI_CLKAN DSI_CLKAP DSI_D1AN DSI_D1AP DSI_D2AN DSI_D2AP DSI_CSI_RUP AD3 AD2 CSI_D1AN CSI_D1AP AE2 AE3 CSI_D2AN CSI_D2AP AG3 AG2 CSI_CLKBN CSI_CLKBP AD1 AE1 CSI_D1BN CSI_D1BP CSI_CLKAN CSI_CLKAP 31 31 CSI_D1AN CSI_D1AP 31 31 CSI_D2AN CSI_D2AP 31 31 CSI_CLKBN CSI_CLKBP CSI_D1BN CSI_D1BP After Wake D00 DOWN 15K PD Disable Hold D01 DOWN 15K PD Disable Hold D02 DOWN 15K PD Disable Hold D03 DOWN 15K PD Config Hold D04 DOWN 15K PD Disable Hold D05 DOWN 15K PD Disable Hold D06 DOWN 15K PD Disable Hold D07 DOWN 15K PD Disable Hold D08 DOWN 15K PD Disable Hold D09 DOWN 15K PD Disable Hold D10 DOWN 15K PD Disable Hold D11 DOWN 15K PD Disable Hold MCLK DOWN 15K PD Disable Hold PCLK DOWN 15K PD Disable Hold HSYNC DOWN 15K PD Disable Hold VSYNC DOWN 15K PD Disable Hold D Camera (Rear) C 31 31 Camera (Front) 31 31 AH2 AH1 AA1 AB1 AB2 AB3 AVDD_DSI_CSI AA2 AA3 R56 453R2F N/A AG4 DSI_CSI_RUP AJ3 DSI_CSI_RDN AB4 DSI_CSI_TEST_OUT DSI_CSI_RDN CSI_CLKAN CSI_CLKAP PUPD AVDD_DSI_CSI AC4 AD4 Deep Sleep PinState AB6 POR VDDIO_VI R57 49.9R2F N/A R58 49.9R2F N/A B 1.8V PUPD PinState PUPD After Wake PBB0 None Z Config Hold PBB3 None Z Config Hold PBB4 None Z Config Hold PBB5 None Z Config Hold PBB6 None Z Config Hold 0626 PBB7 None Z Config Hold VDD_1V8_GEN PCC1 UP 50K PU Config Hold PCC2 UP 50K PU Config Reset 0626 VDD_1V8_GEN_CPU VDDIO_CAM_T30S 0626 C55 N/A 4.7U6.3VX5RC2M U2G R59 2.2KR1J N/A 0626 R60 2.2KR1J N/A 18/22 CAM C54 0.1U6.3VX5RC1K N/A 2 VDD_1V8_GEN 0626 VDDIO_CAM_T30S Deep Sleep POR VDDIO_CAM T30L-R-P-A3 N/A DSI_CSI_TEST_OUT B (1.8/2.8 ~ 3.3V) VDDIO_CAM 1.8V CAM_I2C_SCL CAM_I2C_SDA CAM_MCLK GPIO_PBB0 GPIO_PBB3 GPIO_PBB4 GPIO_PBB5 GPIO_PBB6 GPIO_PBB7 A AG5 AH7 CAM_I2C_SCL CAM_I2C_SDA AD5 VI_MCLK AF6 AD6 AG7 AE5 AE6 AE7 CAM_RST_5M CAM_I2C_SCL 25,26,31,44 CAM_I2C_SDA 25,26,31,44 PWDN_5M CAM2_PWDN PWDN_2M CAM_RST_5M 31 PWDN_5M 31 PWDN_2M 31 R61 N/A 33R2J AD9 VDDIO_CAM_T30S C56 /@ 33P25VNPOC1J CAM_MCLK 31 CW/0228 Check SI A Unmount 12/23 RF add 33P GPIO_PCC1 GPIO_PCC2 AC6 NC AG6 FRONT_SEL TEMP_ALERT# TEMP_ALERT# 26 Title : T30 DSI/CSI,CAM T30L-R-P-A3 N/A Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 of 60 U2I 8/22 LCD 1.8V VDD_1V8_GEN_CPU 1.8V VDDIO_LCD AB13 AC13 VDDIO_LCD VDDIO_LCD_1 VDDIO_LCD_2 (1.8 ~ 3.3V) LCD_PCLK LCD_WR_N LCD_DE LCD_HSYNC LCD_VSYNC D VDDIO_LCD 1 LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23 N/A C57 0.1U6.3VX5RC1K N/A C58 0.1U6.3VX5RC1K C59 N/A 0.1U6.3VX5RC1K AG11 LCD_PCLK AH16 AG9 AF16 AF10 SNN_LCD_ER# LCD_DE LCD_HSYNC LCD_VSYNC AE8 AF12 AD10 AK15 AK16 AK10 AK12 AG16 AG8 AD15 AK9 AJ12 AF9 AC12 AD12 AE18 AF13 AH15 AE9 NC AE10 NC AH13 NC AH9 NC AE13 NC AK13 NC LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_PCLK 22 LCD_DE 22 LCD_HSYNC 22 LCD_VSYNC 22 LCD_D[17 0] 22 D POR VDDIO_LCD PUPD LCD_M1 LCD_PWR0 LCD_PWR1 LCD_PWR2 LCD_SCK LCD_CS0_N LCD_CS1_N LCD_SDOUT LCD_SDIN C LCD_DC0 LCD_DC1 CRT_HSYNC CRT_VSYNC DDC_SCL DDC_SDA HDMI_INT EN_VDD_PNL EN_VDD_PNL1 AJ9 NC AG10 AH12 NC EN_VDD_FUSE SNN_LCD_PWR0 EN_3V3_FUSE SNN_LCD_PWR2 AG15 AJ15 AC10 AJ13 AH10 COMPASS_DRDY SDMMC_WP* BAT_DET* COMPASS_DRDY SNN_LCD_SDOUT ALS_IRQ* AG12 AE15 AE12 ALS_INT#_MB LVDS_SHTDN# LVDS1_SHTDN* SNN_LCD_DC1 EN_VDD_PNL 21,48 EN_VDD_FUSE PUPD After Wake DOWN 100K PD Disable Hold LCD_PWR0 DOWN 100K PD Disable Hold LCD_PWR1 DOWN 100K PD Disable Hold LCD_PWR2 DOWN 100K PD Disable Hold LCD_SCK UP 100K PU Disable Hold LCD_CS0_N UP 100K PU Disable Hold LCD_CS1_N UP 100K PU Disable Hold LCD_SDOUT UP 100K PU Disable Hold LCD_SDIN UP LCD_M1 Deep Sleep PinState 100K PU Disable Hold LCD_DC0 DOWN 100K PD Disable Hold LCD_DC1 DOWN 100K PD Disable Hold 0502 0621 COMPASS_DRDY ALS_INT#_MB 25 LVDS_SHTDN# 22 26 C 0721 SNN_CRT_HSYNC SNN_CRT_VSYNC AD13 AJ16 AG14 AJ10 AG13 T30L-R-P-A3 N/A B B A A Title : T30 LCD Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 10 of 60 Camera VDDIO 1.8V Camera AVDD Camera VCM Power VDDIO_CAM VDD_5V0_AC_BAT VDD_5V0_AC_BAT VPH_PWR_CHGR AVDD_CAM1 0226 VDDIO_CAM change to PMU LDO5 1 D S-1132B28-I6T2G /@ R262 1MR1J N/A C399 1U6.3VX5RC2K /@ 2 C398 1U6.3VX5RC2K /@ VIN VOUT VSS2 VSS1 ON/OFF NC C400 1U6.3VX5RC2K N/A VCM_AVDD_EN CAM2_LDO_EN S-1132B28-I6T2G N/A R261 1MR1J N/A C397 1U6.3VX5RC2K N/A CAM1_AVDD_EN CAM1_LDO_EN Delete Q13, Q14, R258, R260, R263, C279 Change R259 from 1M -> 0ohm VDDIO_CAM AVDD_VCM U28 VIN VOUT VSS2 VSS1 ON/OFF NC D VPH_PWR_CHGR U27 VDD_PMU_LDO5 N/A 2 R259 0R2J MAX77663 LDO5 1 1201 1201 R3427 100K -> 1M R3428 100K -> 1M N/A C286 1U6.3VX5RC2K N/A C287 0.1U6.3VX5RC1K MIPI 5M Camera (Rear) PWDN_5M CAM_RST_5M AVDD_VCM 9 CSI_CLKAP CSI_CLKAN 9 CSI_D1AN CSI_D1AP 9 9,25,26,44 9,25,26,44 CSI_D2AN CSI_D2AP CSI_CLKAP CSI_CLKAN CSI_CLKAP_R CSI_CLKAN_R CSI_D1AN CSI_D1AP CSI_D1AN_R CSI_D1AP_R CSI_D2AN CSI_D2AP CSI_D2AN_R CSI_D2AP_R CAM_I2C_SCL_5R CAM_I2C_SDA_5R CAM_I2C_SCL CAM_I2C_SDA AVDD_CAM1 AVDD_CAM1 VDDIO_CAM 23 24 25 J4 N/A R265 15R1J CAM_MCLK CAM_MCLK_R_1M2 11 13 15 17 19 Unmount 9 C290 10P50VNPOC1J /@ CSI_CLKBP CSI_CLKBN CSI_CLKBP CSI_CLKBN 26 11 13 15 17 19 SIDE3 SIDE4 AVDD_CAM1 PWDN_5M_R CAM_RST_5M_R SIDE1 10 11 12 13 14 15 16 17 18 19 SIDE2 20 21 22 23 24 CON3 /@ SIDE1 SIDE2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDIO_CAM PWDN_2M 10 12 14 16 18 20 10 12 14 16 18 20 J4 2nd source PANASONIC/AXT520124 12G161H0020A 9 PWDN_2M N/A 1MR1J B R266 C294 0.1U6.3VX5RC1K /@ 1 C293 0.1U6.3VX5RC1K /@ C296 0.1U6.3VX5RC1K /@ C292 0.1U6.3VX5RC1K /@ 2 R269 C291 0.1U6.3VX5RC1K /@ CSI_CLKAP CSI_CLKAN CAM_I2C_SCL CAM_I2C_SDA CSI_CLKBP CSI_CLKBN CAM_RST_5M_R CSI_D1BP CSI_D1BN GND GND N/A 1MR1J CAM_RST_2M 12 CAM_I2C_SCL 9,25,26,44 CAM_I2C_SDA 9,25,26,44 R267 2 N/A 1MR1J 12016-00100000 BTOB_CON_20P N/A B PWDN_5M_R PWDN_2M_R CAM_RST_2M_R 21 22 Unmount C289 10P50VNPOC1J /@ CAM_MCLK_R_5M C288 10P50VNPOC1J /@ 2 Unmount /@ R264 15R1J CAM_MCLK C 1.2M Camera (Front) 12018-00050000 FPC_CON_24P C CAM_RST_2M C295 0.1U6.3VX5RC1K /@ N/A 1MR1J R268 GND Unmount GND Unmount C301 0.1U6.3VX5RC1K /@ 1 C300 0.1U6.3VX5RC1K /@ C299 0.1U6.3VX5RC1K /@ C298 0.1U6.3VX5RC1K /@ CSI_D1BP CSI_D1BN 2 C297 0.1U6.3VX5RC1K /@ CSI_D1AN CSI_D1AP CSI_D2AN CSI_D2AP C302 0.1U6.3VX5RC1K /@ RF Requst A A Title : 01.Block Diagram Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Tuesday, March 27, 2012 Sheet 2.0 31 of 60 HOT_RST# inverse for PMIC VDD_5V0_AC_BAT Reset Button MAX77663 SD2 (2A) VDD_1V8_PMU_DCDC2 VPH_PWR_CHGR VDD_1V8_GEN HOT_RST_R1 1 PMU internal PD 200~400k R279 330KR1J N/A HOT_RST D SYS_RESET# 6,20,50 Q8B UM6K1N N/A C304 1000P25VX7RC1K N/A R271 100KR1J N/A 2 C305 1U6.3VX5RC2K /@ D4 N/A BAT54CW D SYS_RESET# to MAX77663 nRSTIO & T30 SYS_RESETn R312 N/A 0R1J SYS_RESET#_SOURCE G N/A RST_SW# R277 0R1J R278 4.7KR1J N/A 11 HOT_RST# Q15 SI2305DS N/A 24 S 2 R276 10KR1J N/A D SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23 Unmount PWRON Key long press RESET for PMIC VDD_5V0_AC_BAT FORCE_RECOVERY# VPH_PWR_CHGR +3VSUS PWR_SW#_RESET_DELAY 11 G 3 D CW:T30 pull high 50~100K internally R305 330KR1J N/A VOL_UP_BUTTON SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23 18,24 TF201 0901 modify Q F_RECOVERY# R275 N/A 0R1J FORCE_R_Q1 HOT_RST_R2 Q16B UM6K1N N/A Q23 SI2305DS N/A FORCE_R_Q2 Q17B UM6K1N N/A C S 2 PWR_SW# R274 100KR1J N/A R272 100KR1J N/A VPH_PWR_CHGR C303 1U6.3VX5RC2K N/A R273 100KR1J /@ VPH_PWR_CHGR PWR_SW#_DELAY_RC2 Unmount VDD_5V0_AC_BAT PWR_SW# VDD_5V0_AC_BAT 2 Q16A N/A UM6K1N 33 VDD_1V8_GEN R270 10MR1J N/A Q17A UM6K1N N/A C C333 2.2U6.3VX5RC2M /@ GND GND Unmount GND VOL_UP H = 1.8V L = 0V A B Q 0 0 1 1 1 B B 8pin Button Connector CON4 N/A FPC_CON_8P 33 PWR_SW#_CTL 33 PWR_SW#_BUTTON PWR_SW#_CTL R314 0R1J N/A PWR_SW#_CTL_CONN PWR_SW#_BUTTON R315 0R1J N/A PWR_SW#_BUTTON_CONN VOL_DWN_BUTTON VOL_UP_BUTTON KB_ROW0 R297 0R1J R286 0R1J R280 0R1J N/A N/A N/A VOL_DWN_BUTTON_R VOL_UP_BUTTON_R KB_ROW0_SW T10 T11 T12 T14 T13 T17 1 1 1 PWR_SW#_CTL_CONN PWR_SW#_BUTTON_CONN VOL_DWN_BUTTON_R KB_ROW0_SW VOL_UP_BUTTON_R RST_SW#_BUTTON 1 VOL_DWN_BUTTON VOL_UP_BUTTON 6,33 KB_ROW0 /@ /@ /@ /@ /@ /@ SIDE2 SIDE1 10 12018-00210800 C306 33P25VNPOC1J /@ Unmount Change RST SW Unmount N/A PWR_SW#_CTL_CONN PWR_SW#_BUTTON_CONN VOL_UP_BUTTON_R VOL_DWN_BUTTON_R KB_ROW0_SW RST_SW#_BUTTON PWR_SW#_CTL PWR_SW#_BUTTON A R304 0R1J 2 VOL_DWN_BUTTON RST_SW# /@ C324 220P50VNPOC2J 07019-00010000 /@ C323 220P50VNPOC2J 07019-00010000 /@ C325 220P50VNPOC2J 07019-00010000 /@ C329 220P50VNPOC2J 07019-00010000 /@ C322 07019-00010000 220P50VNPOC2J /@ C330 07019-00010000 220P50VNPOC2J VOL_UP_BUTTON KB_ROW0 RST_SW# Change C309 220P50VNPOC2J N/A 07019-00010000 GND ESD C309 change to 07019-00010000 ESD change to 07019-00010000 N/A C307 220P50VNPOC2J 07019-00010000 N/A C308 220P50VNPOC2J 07019-00010000 N/A C310 220P50VNPOC2J 07019-00010000 N/A C311 220P50VNPOC2J 07019-00010000 N/A C312 07019-00010000 220P50VNPOC2J A Change ESD C307, C308, C310, C311, C312 change to 07019-00010000 Title : Buttons /Conn Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Wednesday, March 21, 2012 Sheet 2.0 32 of 60 ACOK#_PMIC to MAX77663 ACOK, check Polarity(active Low) on PMU side VDD_5V0_AC_BAT VPH_PWR_CHGR PWR_SW# 32 11 1230 EMC add C314 0.1U6.3VX5RC1K /@ 3 D ONKEY_R1 R295 10KR1J N/A GND Unmount R283 10KR1J N/A Q20 SI2305DS N/A Q18B UM6K1N N/A PMU_ONKEY# VPH_PWR_CHGR 12 ONKEY_R2 D SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23 Signal to MAX77663 50 PMU_ONKEY# PMU_ONKEY# to MAX77663 EN0, check Polarity on PMU side Q21B UM6K1N N/A Q22A UM6K1N N/A VDD_5V0_AC_BAT 2 2MR1J R288 N/A C AP_ONKEY# VPH_PWR_CHGR ONKEY_PMIC PWR_SW#_DELAY 3 R289 220KR1J N/A R290 100KR1J N/A PWR_SW# AP_ONKEY# Q21A UM6K1N N/A BAT_LOW# VDD_5V0_AC_BAT Q22B UM6K1N N/A R287 N/A 1KR1J 1 R285 1MR1J N/A G S 2 PWR_SW#_CTL R282 1MR1J N/A 32 C313 0.1U6.3VX5RC1K N/A PWR_SW#_CTL_0ohm PWR_SW# PWR_SW#_BUTTON PWR_SW#_CTL 2 R284 0R1J N/A 32 PWR_SW#_BUTTON Tegra KB ROW0 D VDD_1V8_GEN PR 0217 KB_ROW0 Q19B N/A UM6K1N 6,32 Q19A N/A UM6K1N KB_ROW0_NMOS VPH_PWR_CHGR DAU BD PWR_SW# BUTTON R281 10KR1J N/A Tegra KB COL0 VDD_5V0_AC_BAT PWRBTN Logic Page 32 PWR_SW#_BUTTON_R Power Button PWR_SW#_DELAY_RC1 Q18A UM6K1N N/A C C315 2.2U6.3VX5RC2M N/A Charger Related Signals VDD_5V0_AC_BAT VPH_PWR_CHGR R299 N/A 10KR1J RESET_IC Signal to MAX77663 ACOK#_PMIC ACOK#_PMIC C318 10U6.3VX5RC3M N/A U29 VDD NC OUT VSS BAT_LOW#_R S-1000N34-I4T1G N/A 2 11 G S Q27 SI2305DS N/A D R301 LL_BAT_R 1KR1J N/A LL_BAT_T30 LL_BAT_T30 B 50 12 AP_CHARGING# BAT_LOW# SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23 R294 10KR1J N/A Signal from SMB347 AP_CHARGING# N/A R302 100KR1J N/A VDD_1V8_GEN To Tegra3 R300 0R1J ACOK#_PMIC_R R303 0R1J N/A C317 0.1U6.3VX5RC1K N/A VBATT RB520CS 2nd Source 07004-00030200 - SCHOTTKY BAT54TM SOD923 07G004045223 SCHOTTKY RB520CS-30 VMN2 [GA] ROHM 07G004250110 SCHOTTKY RB520G-30 SOD723 [GA] PANJIT R296 100KR1J N/A 3% Battry capacity : 3.4V VBATT 49 SMB347_ACOK# Charger OD output (INOK/SYSOK, SMB347 E2 pin) PU 1M (VPH_PWR) on charger page(p.49) preset to ACtive Low L > AC/USB IN VDD_1V8_GEN Signal from SMB347 R291 1MR1J N/A B AP_ACOK# AP_ACOK# D6 RB520CS_30 N/A To Tegra3 12 R298 10KR1J N/A VDD_5V0_AC_BAT Battery Voltage Low Detection VPH_PWR_CHGR VDD_1V8_GEN 0R1J N/A R292 SMB347_STAT 49 Charger OD output (STAT, SMB347 F5 pin) PU 1M (VPH_PWR) on charger page(p.49) preset to ACtive Low L > charging H > other status A A From Tegra3 SMB347_USB51HC 0R1J N/A R306 SMB347_SUSP 0R1J N/A R307 SMB347_USB51HC_CHGR SMB347_SUSP_CHGR 49 49 Signal to SMB347 ROW10, 11 for charger control Title : T30 Core & Fuse Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Wednesday, March 21, 2012 Sheet 2.0 33 of 60 Unmount CLIP1 CLIP2 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ CLIP3 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ D SHIELDING_5P 13GOK0310M100-10 /@ CLIP9 CLIP8 5 GND1 GND2 GND3 GND4 GND5 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ CLIP5 CLIP6 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ CLIP7 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ D CLIP10 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ SHIELDING_5P 13GOK0310M100-10 /@ CLIP4 GND1 GND2 GND3 GND4 GND5 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ Unmount CLIP11 PTH NPTH H1 /@ C138D75 H5 /@ C138D75 H2 /@ C138D75 H3 /@ C59D59N /@ C138D75 H4 H11 /@ C59D59N H8 /@ C138D75 CLIP13 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ H10 H7 /@ C138D75 GND /@ C59D59N H6 /@ C138D75 C H9 /@ C138D75 H12 /@ C43D43N CLIP12 CLIP14 GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ GND1 GND2 GND3 GND4 GND5 C SHIELDING_5P 13GOK0310M100-10 /@ GND U61 N/A EMI_SPRING_PAD U62 N/A EMI_SPRING_PAD GND B B A A Title : EMC, Screw hole Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Tuesday, March 27, 2012 Sheet 2.0 39 of 60 VDD_1V8_GEN R4018 47KR1J /@ CW/0318 Add EMI Cap SDIO_CLK_SPI_CLK R4002 SDIO_CMD_SPI_DI SDIO_CMD_SPI_DI 15 SDMMC3_DAT0 SDMMC3_DAT0 0R1J R4003 SDIO_DATA0_SPI_DO SDIO_DATA0_SPI_DO 15 SDMMC3_DAT1 SDMMC3_DAT1 0R1J R4004 SDIO_DATA1_SPI_IRQ SDIO_DATA1_SPI_IRQ 15 SDMMC3_DAT2 SDMMC3_DAT2 0R1J R4005 SDIO_DATA2_SPI_NC SDIO_DATA2_SPI_NC 41 15 SDMMC3_DAT3 SDMMC3_DAT3 0R1J R4006 SDIO_DATA3_SPI_CS SDIO_DATA3_SPI_CS 41 41 12,41 WLAN_MAC_WAKEN WF_RST# WL_SHUTDOWN_N_RST_N WLAN_MAC_WAKEN WL_HOST_WAKE WL_HOST_WAKE SDIO_DATA1_SPI_IRQ C4008 100PF5VNPOC1J /@ D C4011 100PF5VNPOC1J /@ SDIO_DATA3_SPI_CS C4010 100PF5VNPOC1J /@ C4012 100PF5VNPOC1J /@ 15,41 12,41 CW/0322 Add EMI VARISTOR 6,41,43 C4002 100PF5VNPOC1J /@ WL_EN 1 WiFi_RTC_CLK SDIO_CMD_SPI_DI 41 WL_SHUTDOWN_N_RST_N CLK_32K_OUT 6,41,43 CLK_32K_OUT 41 0R1J 15,41 WF_RST# SDIO_DATA2_SPI_NC C4009 100PF5VNPOC1J /@ SDMMC3_CMD C4007 100PF5VNPOC1J /@ 15 SDMMC3_CMD CW/0228 Follow Cardhu, change to 0ohm SDIO_DATA0_SPI_DO 41 SDIO_CLK_SPI_CLK SDIO_CLK_SPI_CLK R4001 1 0R1J D R4017 47KR1J /@ Unmount 1 R4016 47KR1J /@ R4015 47KR1J /@ R4014 47KR1J /@ R4013 47KR1J /@ 1 C4001 8P25VNPOC1J /@ R4012 47KR1J /@ 2 Unmount R4011 47KR1J /@ SDMMC3_CLK 1 Unmount WIFI SDIO 15 SDMMC3_CLK D4003 TVL040201AB0 /@ Unmount WL_EN 15,41 15,41 WIFI_EN C C remove FM BT 0502 12,41 BT_UART3_RXD BT_UART_TXD 12,41 12,41 BT_UART3_TXD BT_UART_RXD 12,41 12,41 BT_UART3_RTS# BT_UART_CTS_N 12,41 12,41 BT_UART3_CTS# BT_UART_RTS_N 12,41 BT_RST_N 1MR1J R4089 BT_WAKE CW/0322 Add PD 1MR1J R4090 remove FM audio interface, 1201 R4089 & R4090 100K -> 1M GND GND B B BT_WAKE 12,41 BT_WAKEUP BT_WAKE BT_HOST_WAKE 12,41 BT_IRQ# BT_HOST_WAKE BT_RST_N BT_RST_N 12,41 BT_EN 12,41 BT PCM 0502 12,41 12,41 C4003 100PF5VNPOC1J /@ Unmount 12,41 DAP4_SCLK BT_PCM_CLK 12,41 DAP4_FS BT_PCM_SYNC 12,41 DAP4_DIN 12,41 DAP4_DOUT GPS BT_PCM_IN 12,41 BT_PCM_SYNC 12,41 BT_PCM_OUT 12,41 BT_PCM_IN 12,41 0502 GPS_nCTS 12,43 GPS_UART2_RTS# GPS_nRTS 12,43 GPS_UART2_CTS# GPS_TX 12,43 GPS_UART2_RXD 6,41,43 CLK_32K_OUT 1MR1J 12,43 12,43 12,43 GPS_RTCCLK GPS_RTCCLK 6,41,43 GPS_POWER_ON# GPS_POWER_ON# GPS_POWER_ON# remove proximity to 3G path control 0609 A 12,43 C4004 100PF5VNPOC1J /@ N/A Unmount R4091 CW/0322 Add PD 12,43 GPS_nRTS GPS_TX 12,43 GPS_PWRON GPS_nCTS GPS_RX GPS_RX 12,43 GPS_UART2_TXD A BT_PCM_OUT BT_PCM_CLK 1201 R4091 100K -> 1M Title : RF Interface GND Size C Date: Engineer: ASUSTeK COMPUTER INC EPAD Project Name Richard Lin Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 40 of 60 L4106 1.8V N/A VDD_1V8_GEN 0221 ME370T L4110 unmount R4105/R4110 0ohm RF solution WiFi_BT_VDDIO_1V8 Main Ant 120Ohm R4105 2.7NH/300mA 10G212000004010 N/A 0825 3.3V D +3VSUS N/A ANT_BT_WL_3 L4102 60Ohm/100Mhz WiFi_BT_VCC_3V3 L4104 $1.3NH /@ NBS_L0603_H39_000S 10G213000003010 U7912 ANT_BT_WL_4 2 L4109 $1.3NH /@ U7913 D N/A EMI_SPRING_PAD 1 N/A EMI_SPRING_PAD L4110 0.5pF/50V 11G23200R564320 /@ Change 1 R4104 0R2J N/A ANT_BT_WL_1 L4102 change to 0ohm WiFi_BT_VCC_3V3 1 2 C9719 10U6.3VX5RC3M N/A C4138 0.1U6.3VX5RC1K N/A C4142 4.7U6.3VX5RC2M N/A CLOSE PIN A2 C C4143 0.1U6.3VX5RC1K N/A WiFi_BT_VDDIO_1V8 U4303 C Azurewave AW-NH665 0C011-00060000 C4145 N/A 0.1U6.3VX5RC1K C4150 N/A 4.7U6.3VX5RC2M VDD1P2_LNLDO1_OUT Close to C2 Close to A3 Close to C1 1 VDD_2P5_OUT N/A C4140 4.7U6.3VX5RC2M N/A C4149 0.1U6.3VX5RC1K N/A C4144 0.1U6.3VX5RC1K N/A C4147 1U6.3VX5RC2K C4151 N/A 0.1U6.3VX5RC1K C4135 N/A 1U6.3VX5RC2K C4136 N/A 4.7U6.3VX5RC2M C4148 N/A 0.1U6.3VX5RC1K Close to H2 Close to J3 VDD_1P4 1 SR_PA_OUT C4146 N/A 0.1U6.3VX5RC1K VDD1P2_LNLDO1_OUT SR_PA_OUT VDD1P2_LNLDO1_OUT WiFi_BT_VCC_3V3 SR_PA_OUT ANT_BT_WL_1 WiFi_BT_VDDIO_1V8 L4107 N/A 2.2UH Irat=1.7A VDD_2P5_OUT C4139 10U6.3VX5RC3M N/A CBUCK_OUT 1 VDD_1P4 12 BT_HOST_WAKE BT_HOST_WAKE SR_PA_OUT VDD_1P4 VDD1P2_LNLDO1_OUT R4133 12,40 BT_RST_N 0R1J N/A BT_SHUTDOWN_N BT_RST_N WL_GPIO_6 BT_WAKE VDD1P2_LDO_OUT N/A C4366 4.7U6.3VX5RC2M C4367 N/A 0.1U6.3VX5RC1K R4132 0R1J N/A AZWAVE/AW-NH665 0C011-00060000 N/A VDD_WL_PA GND16 WL_UART_RX GND15 BT_PCM_OUT BT_PCM_SYNC SDIO_CMD_SPI_DI SDIO_DATA2_SPI_NC SDIO_CLK_SPI_CLK GND14 BT_UART_TXD BT_UART_CTS_N WL_HOST_WAKE BT_PCM_CLK BT_PCM_IN SDIO_DATA3_SPI_CS SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ G9 G8 G7 G6 G5 G4 G3 G2 G1 F9 F8 F7 F6 F5 F4 F3 F2 F1 WiFi_BT_VCC_3V3 WL_UART_RX T4306 /@ For Debug use only BT_PCM_OUT BT_PCM_SYNC SDIO_CMD_SPI_DI SDIO_DATA2_SPI_NC SDIO_CLK_SPI_CLK BT_PCM_OUT 12 BT_PCM_SYNC 12 SDIO_CMD_SPI_DI SDIO_DATA2_SPI_NC SDIO_CLK_SPI_CLK 40 BT_UART_TXD BT_UART_CTS_N WL_HOST_WAKE BT_PCM_CLK BT_PCM_IN SDIO_DATA3_SPI_CS SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ BT_UART_TXD 12 BT_UART_CTS_N 12 WL_HOST_WAKE 12 BT_PCM_CLK 12 BT_PCM_IN 12 SDIO_DATA3_SPI_CS SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ B 40 40 40 40 40 Close to D1 VDD1P2_LDO_OUT GND1 VBAT_IN SR_PA_OUT GND2 ANT_FM_RX ANT_FM_TX FM_AUDIO_R FM_AUDIO_L GND3 CBUCK_OUT GND4 VOUT_2P5_OUT VOUT_2P5_IN GND5 BT_I2S_CLK BT_HOST_WAKE GND6 VDD_BT_PA VIN_LDO VDD_LN_OUT BT_SHUTDOWN_N BT_RST_N GND7 WL_GPIO_6 BT_I2S_WS BT_WAKE GND8 12,40 BT_WAKE GND24 GND23 ANT_2G4 GND22 GND21 GND20 VDD_LN_IN HSIC_STROBE GND19 VDD_WL_PA_A_MODE NC2 GND18 ANT_AUX_EN GND17 ANT_MAIN_EN HSIC_DATA VDDIO_RF VDDIO B U4303 A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 VDD1P2_CLDO_OUT WL_SHUTDOWN_N_RST_N RTC_CLK GND9 BT_I2S_DO WL_GPIO_5 BT_I2S_DI GND10 NC1 GND11 VDD_CORE WL_UART_TX WL_GPIO_2 GND12 WL_GPIO_1 BT_UART_RTS_N BT_UART_RXD GND13 WiFi_BT_VCC_3V3 SR_PA_OUT D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E6 E7 E8 E9 SR_PA_OUT Close to B9 J9 J8 J7 J6 J5 J4 J3 J2 J1 H9 H8 H7 H6 H5 H4 H3 H2 H1 Close to B3 & B4 Close to E2 15,40 WL_EN 15,40 WL_SHUTDOWN_N_RST_N A 0R1J N/A R4137 0R1J /@ R4131 0R1J N/A VDD1P2_LDO_OUT Unmount WL_EN_RST_N BT_UART_RXD BT_UART_RXD RTC_CLK_EXT_WIFI 6,40,43 WiFi_RTC_CLK R4136 /@ C4117 0.1U6.3VX5RC1K /@ WL_UART_TX BT_UART_RTS_N BT_UART_RTS_N For Debug use only 12 A 12 WL_EN_RST_N Unmount T4107 R4138 1MR1J N/A R4138 100K -> 1M Title : Wifi/BT Combo 1201 Size C Date: Engineer: ASUSTeK COMPUTER INC EPAD Project Name Richard Lin Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 41 of 60 02G561020900 02038-00010100 U7915 BCM4751 BCM47511 02G561020900 02038-00010100 09G061041350 09G061226010 N/A GPS_BCM_IN3 C7919 1PF/25V (0201) N/A /GPS Unbalance_port1 Unbalance_port2 GND1 GND3 GND2 C7925 9.1NH GPS_IN_BCM2 2GPS_IN_BCM0 N/A BCM47511_VDD1P2_GRF D UPC8236T6N-E2-A GPS_BCM_IN2 N/A C7917 1000PF/25V (0201) 1580MHZ 09G061041350 L4306 600Ohm/100Mhz N/A L4308 1.8PF/50V N/A U7915 GND2 VCC1 VCC2 GND1 OUTPUT INPUT POWER_SAVE L4302 $4.7NH /@ U4301 SAW FILTER 1575.42MHZ SAW FILTER 1580MHZ C4310 2.2U6.3VX5RC2M N/A R4306 N/A 0R1J (0201) ST Pre-LNA C.S BCM4751IFBG FBGA100 C.S BCM47511IFBG FBGA100 0221 ME370T L4111 unmount R4316/R4317 0ohm C4306 N/A 2.2U6.3VX5RC2M J8 J9 K8 K10 E10 K6 H10 K7 GPS_VSSIF GPS_VSSPLL GPS_VSSLNA1 GPS_VSSLNA2 GNDIFP VDD1p2_GRF GPS_RFIP GPS_VDDPLL K9 REG_1V8 GPS_VDDIF /GPS U4301 BCM4751IFBG GPS_IN_BCM0 J10 GPS_LNA_EN Unmount GPS_VDDLNA D 09G061041350 09G061226010 2GPS_BCM_ANT3 REG_1V8 GPS_BCM_IN1 GPS_BCM_ANT1 U4302 L4303 5.6NH N/A C7916 1000PF/25V N/A 2 600Ohm/100Mhz L4309 N/A RF GPS_AUXOP GPS_AUXON J7 H8 26MHZ N/A C4315 $0.22U6.3VX5RC2K BCM47511_RTCCLK_R 0R1J R4302 A8 N/A Unmount A7 R4305 N/A 100KR1J GPS_VDD_IO_1V8 BCM47511_RST# A5 J4 12,40 GPS_POWER_ON# U7909 H2 K1 B3 N/A GPS_CAL TCXO LPO_IN ADCP VDDADC ADCN CAL_REQ CLK IF SYS IF VSSADC1 VSSADC2 AUX_HI 6,40,41 GPS_RTCCLK 1 A4 G10 K2 F10 F8 G9 BCM47511_TCXO_OUT_26M /@ Unmount L4112 $1.3NH /@ GPS_SYNC/PPS_OUT VDD_AUX_O VDD_AUX_IN IF_VALID HOST_REQ RST_N LNA_EN REGPU C_GPIO_6 C_GPIO_7 TM1 TM2 TM3 D_GPIO_5 D_GPIO_6 EMI_SPRING_PAD REF_CAP N/A D2 C1 N/A C7920 1000PF/50V Ant_4 EMI_SPRING_PAD 10G212000004010 R4317 2.4P50VNPOC2J N/A L4115 $1.3NH /@ 1 N/A F2 F7 H3 H4 J2 G8 G7 J1 EMI_SPRING_PAD U7931 L4116 $1.3NH /@ N/A 1 RART/I2C IF SCL2/UART_TX SDA2/UART_RX UART_nRTS UART_nCTS REG_1V8 K4 H6 H7 GPS_VDD_BAT_3V3 A6 C GPS_LNA_EN B6 A3 B5 GPS_VDD_IO_1V8 Unmount A2 H1 J6 C4311 0.22U6.3VX5RC2K N/A BCM47511_REF_CAP C4312 N/A 0.01U10VX7RC1K E1 D1 B2 A1 R4304 $100KR1J /@ GPS_TX GPS_RX GPS_nRTS GPS_nCTS 12 12 12 12 XA_1 XA_2 XA_3 XA_4 XA_5 XA_6 XA_7 XA_8 MEMORY XD_0 XD_1 XD_2 XD_3 XD_4 XD_5 XD_6 XD_7 E5 B1 E6 D4 C4 E3 F6 E7 EMI_SPRING_PAD SDA1 SCL1 H9 F9 U7930 Ant_3 U7908 B7 NC1/VCO/ENABLE/DISABLE# VCC NC2 NC3 GND OUTPUT GPS_BCM_ANT1 1 /@ N/A C7918 1000PF/50V 2 L4111 8.2NH /@ C Ant_2 10G212000004010 R4316 2.4P50VNPOC2J N/A Ant_1 X4301 G6 G4 G1 F1 G5 C10 C8 D5 Unmount B GPS_VDD_BAT_3V3 D8 D6 D9 J5 BCM47511_VDD_PRE C4308 2.2U6.3VX5RC2M N/A H5 E9 G2 C7 C3 2 C4309 2.2U6.3VX5RC2M N/A BCM47511_VDD1P2_CORE K5 C6 D7 F3 GPS_VDD_IO_1V8 XD_8 XD_9 XD_10 XD_11 XD_12 XD_13 XD_14 XD_15 XA_17 XA_18 XA_19 XCS_N XWE_N XOE_N VDD_BAT VDD_PRE B F5 E4 E2 PWR NC VDDIFP VDDC1 VDDC2 VDDC3 AVSS1 AVSS2 VDD1p2_CORE VSSC1 VSSC2 VSSC3 VSSC4 VSSC5 VDDIO1 VDDIO2 VDDIO3 C2 D10 B4 A9 A10 B9 C9 B10 E8 J3 K3 G3 F4 B8 C5 D3 VDD_1V8_GEN GPS_VDD_IO_1V8 L4304 2 120Ohm C4305 0.1U6.3VX5RC1K N/A C4314 2.2U6.3VX5RC2M N/A +3VSUS GPS_VDD_BAT_3V3 GPS_VDD_RF L4305 N/A A 120Ohm A EP101 PR 0213 GPS_VDDIO N/A 2 C4307 2.2U6.3VX5RC2M N/A XA_9 XA_10 XA_11 XA_12 XA_13 XA_14 XA_15 XA_16 C4313 2.2U6.3VX5RC2M N/A CW/0228 Check VDD_BAT & VDDIO & RST_N sequence Title : GPS Size C Date: Engineer: ASUSTeK COMPUTER INC EPAD remove proximity to 3G path control 0609 Project Name Richard Lin Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 43 of 60 RX VMID 1 /@ C3637 1 C3607 180pF/50V N/A R4453 0Ohm N/A 1.8V VDD_1V8_GEN NFC_PVDD VDD_5V0_AC_BAT NFC_VBAT R4412 0R2J VPH_PWR_CHGR NFC_PVDD N/A N/A NFC_VBAT C3616 180pF/50V N/A N/A C4401 1U6.3VX5RC2K N/A C4402 0.1U6.3VX5RC1K PF1 NFC_IF1 NFC_SDA NFC_SCL NFC_IRQ C4410 0.1U6.3VX5RC1K N/A R4406 0R1J N/A NFC_IF1 NFC_VEN TX1 TX2 RX VMID PF1 PF2 18PF/50V N/A A6 B6 C5 D5 E5 H2 F3 G2 G3 C6 E3 D3 C3 C2 B1 B2 B3 A1 A7 E6 H1 A2 F4 F5 H8 H5 B5 D2 H3 E2 E1 F1 U7921 feed3 D N/A Feed3 R4455 0Ohm N/A TX23 EMI_SPRING_PAD C3638 10PF/50V /@ U7920 feed4 N/A Feed4 C3634 10PF/50V N/A EMI_SPRING_PAD C3639 10PF/50V /@ C3642 39PF/50V /@ C3635 39PF/50V N/A C3636 39PF/50V N/A C3643 39PF/50V /@ NFC_PVDD C NFC_PVDD NFC_GPIO4 1 NFC_TVDD C4409 1UF6.3VX5RC2K N/A C3632 C3641 10PF/50V N/A R4454 0Ohm N/A R4407 100KR1J N/A NFC_GPIO6 2 C4408 0.1U6.3VX5RC1K N/A NFC_PVDD C4407 1UF6.3VX5RC2K N/A TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 RFU1 RFU2 RFU3 IFSEL0 IFSEL1 IFSEL2 TVSS2 TVSS1 PVSS DVSS AVSS2 AVSS1 XTAL1 XTAL2 UNMOUNT TX13 IF_SEL1 NFC_AVDD NFC_DVDD VBAT VBAT2 VCO_VDD VDHF PMUVCC PMU_GND VSS AVDD_in AVDD_out DVDD PVDD TVDD TVDD_OUT VEN_MON VEN IF0 IF1 IF2 IF3 IRQ SVDD SIGIN SIGOUT SIMVCC SWIO EXT_SW_CTRL TX1 TX2 RX VMID ANT1 ANT2 R4408 0R1J /@ NFC_XTAL1 NFC_XTAL2 1 C4406 N/A 1UF6.3VX5RC2K 1 C4405 0.1U6.3VX5RC1K N/A C D8 F8 D1 C1 A8 G7 F6 G1 F2 A5 A4 G8 F7 E8 B7 E4 B4 C4 D4 A3 C8 E7 D7 B8 C7 D6 H6 H7 H4 G4 G5 G6 UNMOUNT N/A C4403 1U6.3VX5RC2K N/A C4404 0.1U6.3VX5RC1K U4401 NFC_VCO NFC_VDHF 18PF/50V /@ C3640 18PF/50V TX22 PF2 NFC_VBAT 18PF/50V C3631 L4452 N/A 2TX21 560NH R4411 0R2J N/A 560NH R4405 1MR1J N/A TX2 TX12 2 N/A L4451 2TX11 TX1 R4452 0Ohm N/A NFC_SDA NFC_SCL NFC_IRQ NFC_GPIO4 N/A N/A N/A N/A R4401 R4402 R4403 R4404 2 2 2 1 1 UNMOUNT 0R1J 0R1J 0R1J 0R1J R4451 N/A 1KOhm C3620 100NF10V N/A ANT Matching R9814 2KOhm N/A NFC_SDA_R NFC_SCL_R NFC_IRQ_R NFC_GPIO4_R NFC_VEN CAM_I2C_SDA CAM_I2C_SCL 13 NFC_IRQ_R NFC_GPIO4_R NFC_VEN C3619 RXV 1NF/25V N/A 9,25,26,31 9,25,26,31 D 2 UNMOUNT PN65NET1/C205020 N/A NFC_XTAL1 N/A X4401 27.12Mhz NFC_XTAL2 2 1 C4411 10P50VNPOC1J N/A B ADDRESS 28H 29H 2AH 2BH IF0(ADDR0)IF1(ADDR1) 0 1 1 C4412 10P50VNPOC1J N/A B A A Title : NFC Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Jamie Tseng Rev ME370T Thursday, March 22, 2012 Sheet 2.0 44 of 60 SYSTEM Page.48 D VDD_5V0_SYS VBATT Page.49 VDD_USB1_VBUS Page.49 VPH_PWR_CHGR D VBATT DOCK_5V Page.49 +3VSUS VDD_5V0_SYS Page.49 Power +3VSUS Page.48 SMB347_DC_IN VDD_USB1_VBUS VDD_AC_BAT MAX77663 SD0(6A) Page.51 VDD_CPU Page.51 VDD_CORE Page.51 VDD_1V8_GEN VDD_1V0_GEN MAX77663 SD1(3A) VDD_1V2_SOC MAX77663 SD2 (2A) VDD_1V8_GEN MAX77663 SD3(2A) Page.51 +1.35V +1.35V C C B B A A Title : BB-POWER I/F Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Richard Lin Rev ME370T Sheet Thursday, March 01, 2012 2.0 45 of 60 BAT=3V~4.2V +3VSUS POWER SUPPLY VDD_AC_BAT +3VSUS_Iout = 2.5A Iq=50uA , Isd=1uA +3VSUS +3VO PL8201 N/A 80Ohm/100Mhz P_+3VSO_VIN_S 11 10 P_+3VSO_EN_10 12 P_+3VSO_VINA_10 P_+3VSO_PS/SYNC_10 GND /@ PR8211 13 16 0Ohm VIN2 VIN1 VOUT_1 VOUT_2 EN FB GND GND PG 14 P_+3VSO_PG_10 PR8202 1MOHM 2 +3VO GND1 GND2 PR8204 N/A 68KOhm 15 GND 1 P_+3VSO_FB_R_10 N/A PC8201 N/A 4.7pF/50V PR8206 /@ 1MOhm nbs_r0201_h12_000s PR8203 N/A 180KOhm GND Vo=0.5*(1+R1/R2)=3.28V PR8201 0Ohm N/A nbs_r0201_h10_000s GND (50mil PS/SYNC D GND P_+3VSO_FB_10 GND PS/SYNC N/A VINA PGND N/A TPS63020DSJR N/A nbs_r0201_h10_000s N/A 120 mil /@ R0805 nbs_r0805_short_h28_000s PJ8200 SHORT_PIN /@ PC8212 22UF/6.3V L2_1 L2_2 L1_1 L1_2 PC8209 22UF/6.3V N/A PR8200 0Ohm PC8204 /@ 0.1UF/10V N/A PWM Mode PJP8201 4.4x4.2x1.2mm PU8200 GND 10,21 EN_VDD_PNL 120mil P_+3VSO_LX2_S N/A PC8208 22UF/6.3V N/A GND 2.2UH Irat=2.75A 22UF/6.3V PC8205 22UF/6.3V PC8200 N/A GND Power Save Mode PL8200 P_+3VSO_LX1_S 2 P_+3VSO_VIN 0.1UF/10V PC8211 120mil D >1.2V GND External Clock PR8208 C 50 EN_3V3_SYS C P_+3VSO_EN_10 PC8207 1000PF/50V /@ PR8207 100KOhm r0201 /@ N/A 0Ohm r0201 VDD_5V0_SYS +5VSUS POWER SUPPLY 10 EN_5V0_SBY PR8403 1MR2F /@ 11 RT9276_FB EN GND1 GND2 RT9276GQW /@ PC8403 10U6.3VX5RC3M /@ PC8405 0.1U6.3VX5RC1K /@ PR8404 110KOHM /@ B 1 PR8401 1MR1J /@ B PC8401 10P25VNPOC1J /@ LBO PGND PGOOD# LBI VOUT FB/NC RT9276_VOUT LX VBAT 2 PR8400 100KR1J /@ PC8400 /@ N/A RT9376_LBI 5VO PU8400 Irat=1.7A VDD_AC_BAT PL8401 PL8400 /@ 80Ohm/100Mhz /@ r0805_short_h28 BAT=3V~4.2V PJP8400 Iq=25uA , Isd=1uA /@ 2.2UH RT9276_SW +5VSUS_Iin = 1A PS/SYNC , EN Hi > over 1.2V Low > under 0.4V External Sync Mode PR8405 1MR1J RT9276_LBO_R /@ VDD_1V8_GEN PR8402 1MR1J N/A 7,29 EN_5V0_SBY A A Title : 5V & 3.3V External Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Timmy Wu Rev ME370T Wednesday, March 21, 2012 Sheet 2.0 48 of 60 BAT CON 453R2F PR8904 N/A VBATT PU8900 0Ohm B1 MIDUSBIN A2 10UF/16V N/A 10UF/16V N/A B2 PC8916 22NF/16V N/A USBIN1 USBIN2 BOOT DCIN2 PC8917 PC8918 A4 0805 PC8919 PC8922 10UF/16V N/A 1U10VX5RC2K N/A SMB347_VDDCAP SW1 C1 SW2 /@ USB1_ID F1 VSYS1 OTG/ID VSYS2 For layout FETDRV D4 STAT VDD_AC_BAT C2 PWR_I2C_SDA SMB_I2C_SCL F2 SMB_I2C_SDA F3 D3 SDA VCHG SMB347_EN C4 SMB347ET1699Y N/A VDD_AC_BAT 1 VDD_AC_BAT PC8906 N/A 22U6.3VX5RC5M PC8907 N/A 0.1U6.3VX5RC1K PC8908 N/A 1000P25VX7RC1K C 0Ohm nbs_r0201_h12_000s N/A VDD_AC_BAT VDD_AC_BAT PRT8900 10KOHM N/A P_CHG_SW VDD_AC_BAT PC8902 N/A 4.7UF6.3VX5RC2K PC8904 N/A 0.1U6.3VX5RC1K SMB347_THRM USB5/1/HC(USB9/1.5/HC) EN PC8911 N/A 22U6.3VX5RC5M C3 THERM D- Charger preset to LOW enable D+ VBATT PR8901 10KR1J N/A PR8906 D2 33 SMB347_USB51HC_CHGR PC8920 47PF/50V N/A VBATT 1 E1 D1 SMB347_VDDCAP VBATT VBATT GND1 100R1J USB1_D_FP_SMB347 100R1J USB1_D_FN_SMB347 GND2 PR8902 PR8903 N/A B4 SHORT_PIN /@ INOK/SYSOK(CHG_DET_N) F4 C N/A PJP8901 C5 14,28 USB1_DP 14,28 USB1_DN E2 E3 SUSP VCHG 33 SMB347_ACOK# E5 SCL VBATT 33 SMB347_SUSP_CHGR PQ8902 P261AFEA N/A CHGOUT2 0R2J 0R2J E4 6,26,27,50 PR8907 PR8908 PWR_I2C_SCL 240 mil D CHGOUT1 6,26,27,50 D WTOB_CON_6P N/A D5 S 33 SMB347_STAT PWR_I2C_SCL PWR_I2C_SDA 1UH B3 G F5 VDDCAP T8900 c0805 P_CHG_SW A3 PD8901 MMSZ5245B-7-F N/A N/A SIDE1 4 PC8921 N/A 10UF/16V PC8923 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s 2 1 PL8902 SIDE2 A1 MIDDCIN B5 R9947 N/A CON7312 DCIN1 VDD_USB1_VBUS SMB347_DC_IN 453R2F PR8905 N/A SMB457_BOOT BAT54CW SMB347_DC_IN A5 D N/A SMB347_USB_IN from Micro USB Conn PD8900 SMB347_VDDCAP SMB347_DC_IN from Docking Conn SMB347_USB_IN 2 PC8909 N/A 0.1U6.3VX5RC1K N/A PC8910 1000P25VX7RC1K PC8869 N/A 470PF/50V nbs_c0603_h37_000s P_CHG_SNB_S PR9128 100KOhm 5% N/A PR9121 100KOhm 5% /@ 2 B PR9129 100KOhm 5% N/A SMB347_SUSP_CHGR SMB347_EN SMB347_USB51HC_CHGR PR9127 100KOhm 5% /@ 2 PR9120 100KOhm 5% N/A PR8804 1Ohm N/A PR9130 100KOhm 5% /@ B VDD_AC_BAT Delete PR9131 because PU resistor is placed on page33(R294) SMB347_STAT A A Title : Charger SMB347 Engineer: ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Timmy Wu Rev ME370T Wednesday, March 21, 2012 Sheet 2.0 49 of 60 Main PMIC Page of (DC I/P, Reset, GPIO & Crystals) PU900C PC9105 N/A 0.1UF/6.3V nbs_c0201_h13_000s 1/3 GPIO_INA G6 VDD_AC_BAT INI2C 1 GPIO_INB VDD_1V8_GEN G5 N/A PC9111 0.1UF/6.3V nbs_c0201_h13_000s 2 MBATT PC9106 N/A 0.1UF/6.3V nbs_c0201_h13_000s A2 PC9110 0.1UF/6.3V N/A nbs_c0201_h13_000s MON PR9109 N/A 100KR1J nbs_r0201_h12_000s 5% VDD_1V8_GEN PR9110 100KR1J N/A nbs_r0201_h12_000s 5% PR9111 47KR1J N/A G7 EN_AVDD_USB from MAX77663 GPIO2, check PU resister in PMU side(100k PU to VPH_PWR_CHGR) GPIO0 VDD_AC_BAT C3 VDD_AC_BAT SDA SCL F2 E2 PMU_I2C_SDA PMU_I2C_SCL 0R2J 0R2J PR9131 PR9132 6,26,27,49 PWR_I2C_SDA 6,26,27,49 PWR_I2C_SCL E3 2 VDD_1V8_GEN 0R1J N/A PMU_VBACKUP D10 nbs_r0201_h12_000s Note: 1.1K is not needed for this battery GPIO2 GPIO3 PC9107 N/A 0.1UF/6.3V nbs_c0201_h13_000s A10 MAX_XTAL_IN BBATT B10 XGND_1 XIN X3101 32.768khz VDD_1V8_GEN MAX_XTAL_OUT PMU_CGND 6,14 CORE_PWR_REQ CPU_PWR_REQ C10 XOUT N/A PR9113 N/A 100KR1J nbs_r0201_h12_000s 5% C9 Active Low Active - High N/A PR9115 0R1J nbs_r0201_h12_000s PR9116 N/A 0R1J nbs_r0201_h12_000s Active - High GPIO5 GPIO6 GPIO7 C7 CORE_PWR_REQ_PMU C5 CPU_PWR_REQ_PMU C6 E10 E5 Active High or Low 33 ACOK#_PMIC C8 D2 PWR_INT# PMU_CLK32K_OUT_GPIO4 G3 PR9124 N/A 0R1J nbs_r0201_h12_000s N/A PR9125 0R1J nbs_r0201_h12_000s PR9126 N/A CLK_32K_IN CLK_32K_IN 48 nbs_r0201_h12_000s H3 G4 33R1J EN_AVDD_USB 14 EN_3V3_SYS CPU_PWR_REQ_PMU_GPIO PWM, VRTC domain PR9122 N/A 0R1J nbs_r0201_h12_000s CPU_PWR_REQ ???? H4 0229 EMI add NRST_IO SYS_RESET# F9 PC9109 0.1UF/6.3V nbs_c0201_h13_000s /@ XGND_2 D9 PMU_CLK32K_OUT EN0 PR9117 33R1J /@ nbs_r0201_h12_000s EN2 SHDN GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND(SNSN_SD4) GND(SNSP_SD4) GND(FB_SD4) LID ACOK NIRQ E4 D5 D6 D7 E6 E7 F3 F4 F5 SYS_RESET# FB_SD0 6,20,32 CLK_32K_IN GPIOx GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 EN1 CORE_PWR_REQ to MAX77663 EN1, PU resister R14 in CPU side (100k PU to VDD_1V8_GEN), delete R9114 CPU_PWR_REQ to MAX77663 EN2, PD resister R15 in CPU side(100k PD), delete R9118 EN_3V3_SYS_R H8 SYS_RESET# to MAX77663 nRSTIO & T30 SYS_RESETn, R278 PU 4.7K to VDD_1V8_GEN on page.32, delete PR9112 32K_OUT PMU_ONKEY#_R_PMIC Active - Low 26 AP_OVERHEAT# GPIO4 EN_AVDD_USB_PMIC G8 BAT_COINCELL H7 30 BAT_COINCELL GPIO1 MAX77663 PR9107 Alternate Mode Low-Power Mode Control Input Flexible Power Sequencer Output Flexible Power Sequencer Output Flexible Power Sequencer Output 32kHz Output (32K_OUT1) SD0 Dynamic Voltage Scaling Input SD1 Dynamic Voltage Scaling Input Reference Output 1.25V buffered reference output 51 MAX77612AEMJ+ N/A 26 THERMAL#_R 0R1J /@ /@ nbs_r0201_h12_000s 0R1J N/A nbs_r0201_h12_000s 1 R2613 PJ9102 PR9114 PMU_ONKEY#_R PJ9101 SHORT_PIN 33 PMU_ONKEY# PC9108 0.1UF/6.3V nbs_c0201_h13_000s /@ PMU_CGND SHORT_PIN /@ 0229 EMI add Title : PMIC 1/3 ASUSTeK COMPUTER INC EPAD Size Custom Date: Project Name Engineer: Timmy Wu Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 50 of 60 Main PMIC Page of (Main DC/DC Converters) VDD_AC_BAT PU900A VDD_AC_BAT VDD_1V0_GEN 2/3 AVSD 6000mA LXB_SD0 Irat=4.2A N/A PL9305 1UH Irat=4.2A N/A H6 J6 VDD_AC_BAT PGA_SD0_1(PG_SD0) PGA_SD0_2(PG_SD0) LXA_SD0 J3 J4 PGB_SD0_1(PG_SD4) PGB_SD0_2(PG_SD4) PJP9306 VDD_AC_BAT_INB_SD0 R0805 nbs_r0805_short_h28_000s H2 J2 PC9303 10UF/6.3V N/A FB_SD0 SNSP_SD0 SNSN_SD0 VDD_AC_BAT F6 VDD_AC_BAT_IN_SD1 R0603 H10 J10 IN_SD1_1 IN_SD1_2 PC9304 10UF/6.3V N/A LX_SD1_1 LX_SD1_2 PCE9301 100UF/6.3V /@ GND FB_SD0 50 F7 F8 PL9306 N/A FB_SD0 G9 G10 VDD_CPU_SENSE GND_CPU_SENSE 1UH VDD_1V2_SOC PJP9312 LX_SD1 VDD_PMU_1V2_DCDC1_RS /@ Irat=4.2A N/A R0805 nbs_r0805_short_h28_000s 3000mA /@ PJP9307 N/A INB_SD0_1(IN_SD4) INB_SD0_2(IN_SD4) 2 PJP9301 SHORT_PIN /@ F10 PG_SD1 /@ H5 J5 + remove and bypass the shunt after routing LXB_SD0_1(LX_SD4) LXB_SD0_2(LX_SD4) J7 J8 LXA_SD0_1(LX_SD0) LXA_SD0_2(LX_SD0) INA_SD0(IN_SD4) INA_SD0(IN_SD0) 2 H9 J9 PC9302 10UF/6.3V N/A 22UF/6.3V PC9308 VDD_AC_BAT_INA_SD0 R0805 nbs_r0805_short_h28_000s 1UH 22UF/6.3V PC9309 /@ PL9304 22UF/6.3V PC9307 B2 PJP9305 remove and bypass the shunt after routing PJP9302 SHORT_PIN /@ N/A For layout VDD_AC_BAT 1UH N/A 2520/2.3A E1 F1 FB_SD2 D3 FB_SD2 PC9310 10UF/6.3V nbs_c0603_h37_000s N/A PC9312 10UF/6.3V nbs_c0603_h37_000s N/A /@ R0805 nbs_r0805_short_h28_000s remove and bypass the shunt after routing PJP9303 SHORT_PIN /@ LX_SD3_1 LX_SD3_2 C1 C2 LX_SD3 +1.35V 1UH N/A 2520/2.3A PG_SD3 D1 PR9151 0R1J nbs_r0201_h12_000s N/A nbs_c0805_h55_000s D4 D_SD3 FB_SD3 C4 PJP9304 SHORT_PIN /@ remove and bypass the shunt after routing FB_SD3 MAX_D_SD3 PC9306 10UF/6.3V N/A 2000mA PC9318 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s IN_SD3_1 IN_SD3_2 B1 A1 2 VDD_AC_BAT N/A PG_SD2_1 PG_SD2_2 22UF/6.3V PC9311 VDD_AC_BAT_IN_SD3 R0603 LX_SD2_1 LX_SD2_2 VDD_1V8_PMU_DCDC2 PL9302 2 PJP9311 1 /@ 2000mA PJP9309 1 IN_SD2_1 IN_SD2_2 PC9305 10UF/6.3V N/A VDD_1V8_GEN LX_SD2 PC9317 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s 5 PL9303 G1 G2 H1 J1 VDD_CORE_SENSE GND_CORE_SENSE 2 R0603 VDD_AC_BAT_IN_SD2 E9 E8 PJP9308 /@ D8 VDD_AC_BAT MAX77663 FB_SD1 SNSP_SD1 SNSN_SD1 PR9152 0R1J nbs_r0201_h12_000s /@ MAX77612AEMJ+ N/A Unmount D_SD3 Logic Level SD3 Default Voltage MBATT (logic high) 1.35V Unconnected 1.5V GND (logic low) 1.2V Title : PMIC 2/3 ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Engineer: Timmy Wu Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 51 of 60 Main PMIC Page of (LDO's) PU900B 3/3 PR9205 B8 IN_LDO0_1 OUT_LDO1 PMU_LDO_OUT_1 B9 150mA A6 IN_LDO2 OUT_LDO2 PC9214 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s B4 IN_LDO4_6 PMU_LDO_OUT_4 B3 OUT_LDO6 PMU_LDO_7_8_IN_1V35 IN_LDO7_8 N/A PR9215 0R2J nbs_r0402_h16_000s PR9216 /@ 0R2J nbs_r0402_h16_000s PC9211 N/A 4.7U6.3VX5RC2M nbs_c0402_h22_000s PR9217 N/A 0R2J nbs_r0402_h16_000s VDD_PMU_LDO4_1V2 to T30 AVDD_DSI_CSI VDD_PMU_LDO6_3V_1V8 to T30 VDDIO_SDMMC1 No use VDD_PMU_LDO7_1V2 to T30 AVDD_DSI_CSI N/A PC9217 1U6.3VX5RC2K nbs_c0402_h22_000s 300mA PMU_LDO_OUT_8 A9 OUT_LDO8 MAX77612AEMJ+ N/A 0R2J nbs_r0402_h16_000s A8 2 VDD_PMU_LDO3_2V8 to eMMC Vcore(VCORE_EMMC_S) to Camera 1.8V PC9210 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s PMU_LDO_OUT_7 A7 OUT_LDO7 +1.35V VDD_PMU_LDO2_2V8 to T30 VDD_DDR_RX VDD_PMU_LDO5 PC9209 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s PMU_LDO_OUT_6 B5 150mA 450mA N/A PC9208 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s OUT_LDO4 150mA PC9216 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s PMU_LDO_OUT_5 A5 PMU_LDO_4_6_IN_VPH PR9209 PR9213 N/A 0R2J nbs_r0402_h16_000s PC9207 N/A 2.2U6.3VX5RC2M nbs_c0402_h22_000s OUT_LDO5 150mA 0R2J nbs_r0402_h16_000s PC9206 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s IN_LDO3_5 N/A PC9215 1U6.3VX5RC2K nbs_c0402_h22_000s N/A VDD_AC_BAT PR9212 N/A 0R2J nbs_r0402_h16_000s 1 PR9208 A4 no use PMU_LDO_OUT_3 A3 PMU_LDO_3_5_IN_3V3 MAX77663 PR9207 N/A 0R2J nbs_r0402_h16_000s VDD_PMU_LDO0_1V0 to T30 VDD_DDR_HS VDD_PMU_LDO1 PMU_LDO_OUT_2 B6 150mA OUT_LDO3 N/A PC9205 1U6.3VX5RC2K nbs_c0402_h22_000s PMU_LDO_2_IN_3V3 300mA +3VSUS N/A PC9204 1U6.3VX5RC2K nbs_c0402_h22_000s N/A PC9213 1U6.3VX5RC2K nbs_c0402_h22_000s PR9206 N/A 0R2J nbs_r0402_h16_000s +3VSUS 1 0R2J nbs_r0402_h16_000s PMU_LDO_0_1_IN_1V35 N/A +1.35V N/A PR9210 0R2J nbs_r0402_h16_000s PMU_LDO_OUT_0 B7 OUT_LDO0 150mA N/A PC9212 2.2U6.3VX5RC2M nbs_c0402_h22_000s PR9218 N/A 0R2J nbs_r0402_h16_000s VDD_PMU_LDO8_1V2 to T30 AVDD_PLLx Title : PMIC 3/3 ASUSTeK COMPUTER INC EPAD Size C Date: Project Name Engineer: Timmy Wu Rev ME370T Tuesday, March 20, 2012 Sheet 2.0 52 of 60 www.s-manuals.com ... to 07 019 -00 0 100 00 N/A C 307 220P50VNPOC2J 07 019 -00 0 100 00 N/A C 308 220P50VNPOC2J 07 019 -00 0 100 00 N/A C3 10 220P50VNPOC2J 07 019 -00 0 100 00 N/A C311 220P50VNPOC2J 07 019 -00 0 100 00 N/A C312 07 019 -00 0 100 00. .. R 304 0R1J 2 VOL_DWN_BUTTON RST_SW# /@ C324 220P50VNPOC2J 07 019 -00 0 100 00 /@ C323 220P50VNPOC2J 07 019 -00 0 100 00 /@ C325 220P50VNPOC2J 07 019 -00 0 100 00 /@ C329 220P50VNPOC2J 07 019 -00 0 100 00 /@ C322 07 019 -00 0 100 00. .. /@ C322 07 019 -00 0 100 00 220P50VNPOC2J /@ C3 30 0 701 9 -00 0 100 00 220P50VNPOC2J VOL_UP_BUTTON KB_ROW0 RST_SW# Change C 309 220P50VNPOC2J N/A 07 019 -00 0 100 00 GND ESD C 309 change to 07 019 -00 0 100 00 ESD change