Acer aspire 9100 COMPAL LA 2351

5 COMPAL CONFIDENTIAL D MODEL NAME : EDL70/71 COMPAL P/N : PCB NO : Revision : 1B D EDL70/71 Schematics Document uFCBGA/uFCPGA Mobile Dothan Intel Alviso + ICH6M C C 2005-02-25 REV : 1B B B A A Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Sheet Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA2351 Sheet 1 of 59 Compal confidential Model : EDL71 FAN +5VS Pentium-M Dothan uFCPGA CPU Thermal(CPU) +3VS G781 page page +VCCP (1.05V) +CPU_CORE Clock Generator page 5,6,7 478pin D ICS954226 +3VS H_A#(3 31) System Bus D page 17 H_D#(0 63) +VCCP 400/533 MHz TV OUT INTEL Alviso 1257BGA page 25 +1.5VS CRT CONN +1.8VS page 25 CRT Signal +VGA_CORE Internal LVDS LVDS CONN page 24 ATI M24P +2.5V +3VS +VCCP +2.5VS +3VS +1.2VS page 18,19,20,21 +2.5VS Frame Buffer 64/128 C +1.5VS PCI-E 16X +3VS IDSEL:AD20 (PIRQA,B#,GNT#2,REQ#2),SIRQ IDSEL:AD16 (PIRQE#,GNT#0,REQ#0) WIRELESS TV Turner VT6301S ENE CB712 1394 Controller +S1_VCC page +3VS page 34 +3VS 32 1394 CONN B page 34 Card Reader 48MHz INTEL ICH6-M 609 BGA +3VS +3V +VCC_5IN1 page 33 RTL8110SBL /8100CL PCMCIA Slot +S1_VCC +S1_VPP page 33 page 35 +1.5V +1.8VS/ +VGA_CORE Port DEBUG +5VS +3VS page 54 CPU_CORE page 55 page 43 RJ45 +3VALW 33MHz Cable Parallel ATA +5VS page 31 AC97 Codec ALC250 B +5VAMP +3VS X BUS RJ11 page 44 page 36 IDE CD-ROM page 41 SST39VF040 +5VCD page 31 page 42 Int.KBD page 43 AMP & INT Speaker Power On/Off SW & LED +5VAMP page 45 HeadPhone & MIC CONN +5VAMP page 45 page 43 52 3V/5V/12V page 49 MDC +5VS +3VS +3V page 39 KB910 page 36 Touch Pad & LID SW A CHARGER ATA100 page 48 2.5V/+1.2VS/ +1.25VS page page 40 AC-LINK LPC BUS page 50 DC IN +5VALW 24.576MHz page 27,28,29,30 +1.5VS/+VCCP RTC BATT USB Ports X4 USB[0,2,4,6] +2.5VS +5VS +3VALW page 53 C +3VALW 33MHz PCI BUS +3VALW page 37,38 page 14,15 +1.5VS 100MHz IDSEL:AD17 (PIRQF#,GNT#3,REQ#3) CardBus Controller +1.25VS page 9,10,11,12,13 +1.5VS Minipci CONN X2 BANK 0, 1, 2, DMI G781-1 page 26 IDSEL:AD18 (PIRQG#,PIRQH#,GNT#1,REQ#1) IDSEL:AD19 (PIRQH#,PIRQG#,GNT#4,REQ#4) DDRI-DIMM X2 2.5V 333 MHz +2.5V Thermal(VGA) page 22,23 Memory BUS (DDRI) DC/DC Interface page 51 A +5VS page 43 page 47 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Sheet Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 D D AC Adapter in MAINPWON VIN VS LM358 Thermal Protector P48 P50 SWITCH ADPPWR VL FAN5234 DC/DC (2.5V) P49 RUN BATT+ +3VALWP P53 MAX1902 DC/DC (3V/5V/12V) B+ +2.5V 7.106A SUSP VCC MB3887 Charger +5VALWP P52 SHDN# VS Vcc VMB +1.5VP 5A 3VALW MAX8743 DC/DC (1.5V/VCCP) TPO610T SWITCH P50 ALP5331 DC/DC (1.25V) P53 P55 EN SUSP CPU_CORE (+1.308V B+ VS_ON1/VS_ON2 CHGRTC G920 RTC BATT Charger C 2.5VP 2.5VREF 51_ON# SHDN# MAX1532 DC/DC (CPU_CORE) +1.25V 1A C P50 VR_ON B+ +5VS +12VALWP 25A) P54 ON1/ON2 +VCCP 6.420A P50 Battery A Cell B+ B B Battery Connector A P48 CHG/DIS BATT+ SWITCH BATT P48 VS LM393 BATT OVP P49 BATT_OVP A A Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Power Rail Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 Board ID Table for AD channel Vcc Ra Voltage Rails Power Plane D C Board ID Description S0-S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A OFF +CPU_CORE Core voltage for CPU ON OFF +PCIE_1.2VS +PCIE_1.2VS power rail for VGA PCIExpress ON OFF OFF +0.9VS 0.9VS for DDR2 Termination ON OFF OFF +VGA_CORE VGA Core Power ON OFF OFF +1.5VS MCH & ICH Core Power ON OFF OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5VS 2.5VS switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V power rail ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +12VALW 12V always on power rail ON ON ON* +RTCVCC RTC power ON ON ON 3.3V +/- 5% 100K +/- 5% Rb 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V Board ID * V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V D PCB Revision 0.1 0.2 0.3 0.4 0.5 0.6 1.0 1.B C SKU ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Vcc Ra Board ID External PCI Devices Device IDSEL# REQ#/GNT# Interrupts PIRQA VGA B 1394 AD16 LAN AD17 PIRQF C ardBus AD20 PIRQA,B Mini-PCI AD18 PIRQG/PIRQH Mini-PCI II for TV Turnner AD19 PIRQH/PIRQG EC SM Bus1 address PIRQE Device Address Device Address Smart Battery 0001 011X b G781 1001 100X b EEPROM(24C16/02) 1010 000X b G781-1 1001 101X b Device Address Clock Generator ( ICS954206) 1101 001Xb DDRII DIMM0 1010 000Xb DDRII DIMM1 1010 001Xb SKU ID * EC SM Bus2 address ICH6 SM Bus address A 3.3V +/- 5% 100K +/- 5% Rb 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V B EDL71 SKU EDL71 10/100 LAN WO/TV TUNER EDL71 GIGA LAN W/TV TURNER EDL71 10/100LAN W/TV TUNER EDL71 GIGA WO/TV TUNER EDL71 10/100 LAN WO/TV TUNER EDL71 10/100LAN W/TV TUNER EDL71 GIGA WO/TV TUNER EDL71 GIGA LAN W/TV TURNER NOTE1: SWDJ@ : SWDJ NOSWDJ@ : W/O SWDJ TV@ : TV Tunner 100@ : 10/100M LAN GIGA@ : 10/100M/1000M LAN 1@XX : Pop for Integrated Graphic @XX : Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Depop component 2@XX : Pop for External Graphic V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V Notes List Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 H_A#[3 31] H_REQ#[0 4] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 9 H_ADSTB#0 H_ADSTB#1 H_ADSTB#0 H_ADSTB#1 P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 R2 P3 T2 P1 T1 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# Dothan ADDR GROUP DATA GROUP REQ0# REQ1# REQ2# REQ3# REQ4# U3 AE5 ADSTB0# ADSTB1# A16 A15 ITP_CLK0 ITP_CLK1 B15 B14 BCLK0 BCLK1 H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRD Y# H_HIT# H_HITM# H_IERR# H_LOCK# H_RESET# N2 L1 J3 N4 L4 H2 K3 K4 A4 J2 B11 ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H1 K1 L2 M3 RS0# RS1# RS2# TRDY# C8 B8 A9 C9 BPM0# BPM1# BPM2# BPM3# @ R801 0_0402_5% CPU_ITTP CPU_ITTP# @ R802 0_0402_5% CLK_CPU_BCLK 17 CLK_CPU_BCLK CLK_CPU_BCLK# 17 CLK_CPU_BCLK# +VCCP 9 9 9 R72 56_0402_5% 9 9 H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM# H_LOCK# H_RESET# H_RS#[0 2] H_TRDY# HOST CLK CONTROL GROUP D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 +3V R63 150_0603_1% ITP_DBRESET# D +VCCP R64 54.9_0603_1%@ R65 @ 54.9_0603_1% +VCCP ITP_TDO H_RESET# R66 39.2_0603_1% ITP_TMS R68 150_0603_1% ITP_TDI This shall place near CPU R70 680_0402_5% ITP_TRST# R71 27.4_0603_1% ITP_TCK C +3VS +VCCP H_D#[0 63] C 17 CLK_CPU_ITP 17 CLK_CPU_ITP# JP1A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 D 28 H_CPUPWRGD 9,28 H_CPUSLP# H_THERMDA H_THERMDC 8,9,28 H_THERMTRIP# H_CPUSLP# ITP_TCK ITP_TDI ITP_TDO TEST1 TEST2 ITP_TMS ITP_TRST# PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST# H_THERMDA B18 H_THERMDC A18 C17 MISC H_DSTBN#[0 3] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 B C23 K24 W25 AE24 C22 L24 W24 AE25 R731 1K_0402_5% R730 56_0402_5% PROCHOT# 41 H_DSTBP#[0 3] R147 56_0402_5% E4 A6 A13 C12 A12 C5 F23 C11 B13 DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# 9 9 C Q67 2SC2411K_SC59 B E H_PROCHOT# DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DBSY# H_DPSLP# H_DPRSLP# H_DPWR# A7 M2 B7 G1 C19 A10 B10 B17 D25 J26 T24 AD20 28 28 ITP_DBRESET# H_DBSY# H_DPSLP# H_DPRSLP# DINV0# DINV1# DINV2# DINV3# B H_PROCHOT# THERMAL A20M# FERR# IGNNE# INIT# LINT0 LINT1 C2 D3 A3 B5 D1 D4 H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI STPCLK# SMI# C6 B4 H_STPCLK# H_SMI# H_A20M# 28 H_FERR# 28 H_IGNNE# 28 H_INIT# 28 H_INTR 28 H_NMI 28 LEGACY CPU THERMDA DIODE THERMDC THERMTRIP# R149 TEST2 TEST1 H_STPCLK# 28 H_SMI# 28 @ 1K_0402_5% R148 @ 1K_0402_5% A A H_THERMDA, H_THERMDC routing together Trace width / Spacing = 10 / 10 mil +VCCP R88 75_0402_5% H_THERMTRIP# +VCCP R74 200_0402_5% H_CPUPWRGD TYCO_1612365-1_Dothan 75ohm pull-up of H_THERMTRIP# should be within 2" from the series resistor Add pullups for PWRGOOD and THERMTRIP per INTEL Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Dothan Processor in mFCPGA479 Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 +CPU_CORE +VCCA_PROC R78 0_0603_5% +VCCP C18 0.01U_0402_16V7K +1.5VS C19 10U_0805_10V4Z D JP1B VCCSENSE VSSSENSE AE7 AF6 VCCSENSE VSSSENSE F26 B1 N1 AC26 VCCA0 VCCA1 VCCA2 VCCA3 P23 W4 VCCQ0 VCCQ1 D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L5 L21 M6 M22 N5 N21 P6 P22 R5 R21 T6 T22 U21 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC H_PSI# E1 PSI# VID0 VID1 VID2 VID3 VID4 VID5 E2 F2 F3 G3 G4 H4 VID0 VID1 VID2 VID3 VID4 VID5 C +CPU_CORE 55 PSI# 55 55 55 55 55 55 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 AD26 V_CPU_GTLREF JP1C Dothan POWER, GROUNG, RESERVED SIGNALS AND NC R75 @ 54.9_0603_1% 2 R76 @ 54.9_0603_1% GTLREF B 17 CPU_BSEL0 17 CPU_BSEL1 14.5 mil mil 14.5 mil mil CPU_BSEL0 CPU_BSEL1 C16 C14 BSEL0 BSEL1 COMP0 COMP1 COMP2 COMP3 P25 P26 AB2 AB1 COMP0 COMP1 COMP2 COMP3 B2 C3 E26 AF7 AC1 RSVD RSVD RSVD RSVD RSVD R81 54.9_0603_1% R82 27.4_0603_1% R83 54.9_0603_1% 2 R_B Resistor placed within 0.5" of CPU pin.Trace should be at least 25 miles away from any other toggling signal R79 1K_0603_1% V_CPU_GTLREF R80 27.4_0603_1% R_A +VCCP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 TYCO_1612365-1_Dothan F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18 AE9 AE11 AE13 AE15 AE17 AE19 AF8 AF10 AF12 AF14 AF16 AF18 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Dothan POWER, GROUND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24 D C B TYCO_1612365-1_Dothan R84 2K_0603_1% A A Layout close CPU Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Dothan Processor in mFCPGA479 Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 +CPU_CORE +CPU_CORE 1 C20 10U_1206_6.3V6M 2 C21 10U_1206_6.3V6M C22 10U_1206_6.3V6M C23 10U_1206_6.3V6M C24 10U_1206_6.3V6M C25 10U_1206_6.3V6M C26 10U_1206_6.3V6M 2 C27 10U_1206_6.3V6M C28 10U_1206_6.3V6M C29 10U_1206_6.3V6M D D +CPU_CORE +CPU_CORE 1 C30 10U_1206_6.3V6M 2 C31 10U_1206_6.3V6M C32 10U_1206_6.3V6M C33 10U_1206_6.3V6M C34 10U_1206_6.3V6M +CPU_CORE C36 10U_1206_6.3V6M 2 C37 10U_1206_6.3V6M C38 10U_1206_6.3V6M C39 10U_1206_6.3V6M +CPU_CORE 1 C40 10U_1206_6.3V6M C35 10U_1206_6.3V6M C41 10U_1206_6.3V6M C42 10U_1206_6.3V6M C43 10U_1206_6.3V6M C44 10U_1206_6.3V6M C45 10U_1206_6.3V6M C46 10U_1206_6.3V6M 2 C47 10U_1206_6.3V6M C48 10U_1206_6.3V6M C49 10U_1206_6.3V6M +CPU_CORE 1 C50 10U_1206_6.3V6M C 2 C51 10U_1206_6.3V6M C52 10U_1206_6.3V6M C53 10U_1206_6.3V6M 10uF 1206 X5R -> 85 degree C54 10U_1206_6.3V6M High Frequence Decoupling C Near VCORE regulator + + + C58 330U_D2E_2.5VM_R9 C57 330U_D2E_2.5VM_R9 C56 330U_D2E_2.5VM_R9 C55 330U_D2E_2.5VM_R9 @ +CPU_CORE ESR 880uF + B B 9mOhm 7343 PS CAP 9mOhm 7343 PS CAP 9mOhm 9mOhm 7343 7343 PS CAP PS CAP +VCCP 1 + C59 150U_C_4VM C60 0.1U_0402_16V4Z C61 0.1U_0402_16V4Z C62 0.1U_0402_16V4Z C63 0.1U_0402_16V4Z C64 0.1U_0402_16V4Z C65 0.1U_0402_16V4Z C66 0.1U_0402_16V4Z C67 0.1U_0402_16V4Z C68 0.1U_0402_16V4Z C69 0.1U_0402_16V4Z A A Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CPU Bypass Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 Fan Control circuit +12VALW +5VS U3A EN_FAN1 1U_0603_10V4Z S -IN R163 10K_0402_5% SI3456DV-T1_TSOP6 LM358A_SO8 C140 OUT FAN1 G G +IN EN_FAN1 D Q31 P 41 D +3VS 2 C73 0.1U_0402_16V4Z D FANSPEED1 41 C143 2200P_0402_50V7K 2 R162 100K_0402_5% JP2 + D23 RB751V_SOD323 ACES_85205-0300 C72 C C17 0.001U_0402_50V7M 22U_A_4VM FANVOUT1 R150 150K_0402_5% C C145 0.01U_0402_16V7K Thermal Sensor G781 H_THERMDA +VCCP R145 300_0402_5% C146 @ 1U_0603_10V4Z +3VS H_THERMDA H_THERMDC H_THERMDC @ W=1 5mil C147 B B C Q8 2SC2411K_SC59 E H_THERMTRIP# 5,9,28 H_THERMTRIP# C148 MAINPWON 48,50,51 2200P_0402_25V7K U4 H_THERMDA D+ VDD1 H_THERMDC D- ALERT# @ R146 10K_0402_5% @ 1 B 0.1U_0402_16V4Z SDATA +2.5V SCLK EC_SMD_2 EC_SMC_2 41 41 R513 8.2K_0402_5% +12VALW THERM# GND G781_SOP8 R512 8.2K_0402_5% +3VALW R1018 10K_0402_1% U3B +IN -IN OUT R1019 A 10K_0402_1% +V_DDR_MCH_REF A LM358A_SO8 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC FAN & Thermal Sensor Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 H_RS#[0 2] ALVISO_BGA1257 R85 221_0603_1% 2 DDR_CKE0 DDR_CKE1 DDR_CKE2 DDR_CKE3 14 14 15 15 DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3 AA33 AB37 AC33 AD37 DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 Y33 AA37 AB33 AC37 DMITXP0 DMITXP1 DMITXP2 DMITXP3 DDR_CLK0 DDR_CLK1 AM33 AL1 AE11 AJ34 AF6 AC10 SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5 AN33 AK1 AE10 AJ33 AF5 AD10 SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5# DDR_CKE0 DDR_CKE1 DDR_CKE2 DDR_CKE3 AP21 AM21 AH21 AK21 SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3 AN16 AM14 AH15 AG16 SM_CS0# SM_CS1# SM_CS2# SM_CS3# AF22 AF16 AP14 AL15 AM11 AN10 SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 AK10 AK11 AF37 AD1 AE27 AE28 AF9 AF10 SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT DDR_CLK0# DDR_CLK1# DDR_CLK3# DDR_CLK4# 15 DDR_CLK3# 15 DDR_CLK4# 14 14 15 15 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DDR_CLK3 DDR_CLK4 15 DDR_CLK3 15 DDR_CLK4 14 DDR_CLK0# 14 DDR_CLK1# DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 +VCCP M_OCDOCMP0 M_OCDOCMP1 +2.5V H_VREF H_XRCOMP H_XSCOMP H_YRCOMP H_YSCOMP H_SWNG0 H_SWNG1 +VCCP R760 SMRCOMPN SMRCOMPP 80.6_0603_1% +V_DDR_MCH_REF R761 80.6_0603_1% CFG/RSVD DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 Y31 AA35 AB31 AC35 DMI 29 29 29 29 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DDR MUXING R86 100_0603_1% DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 14 DDR_CLK0 14 DDR_CLK1 R87 221_0603_1% J11 C1 C2 T1 L1 D1 P1 C70 0.1U_0402_16V4Z HVREF HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING 29 29 29 29 DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25 CFG0 MCH_CLKSEL1 MCH_CLKSEL0 CFG5 CFG6 CFG7 CFG0 11 MCH_CLKSEL1 17 MCH_CLKSEL0 17 CFG9 CFG12 CFG13 CFG16 CFG18 CFG19 BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN# DREF_CLKN DREF_CLKP DREF_SSCLKP DREF_SSCLKN Layout Note: H_XRCOMP & H_YRCOMP trace width and spacing is 10/20 H_R_CPUSLP# @ @ CFG9 11 CFG12 CFG13 11 11 CFG16 11 CFG18 CFG19 11 11 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 A24 A23 D37 C37 DREFCLK# 17 DREFCLK 17 DREF_SSCLK 17 DREF_SSCLK# 17 +1.5VS R1054 0_0402_5% R1055 0_0402_5% 2@ AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37 2@ B +2.5VS R101 40.2_0402_1% R99 0_0402_5% 11 11 11 ALVISO_BGA1257 Layout Note: Route as short as possible R100 40.2_0402_1% H_CPUSLP# CFG5 CFG6 CFG7 J23 PM_BMBUSY# 29 PM_EXTTS#0 J21 PM_EXTTS#1 H22 F5 H_THERMTRIP# 5,8,28 AD30 VGATE VGATE 17,29,55 AE29 PLTRST_R# PLTRST# 27,29,35,39,41,46 R90 100_0402_5% M_OCDOCMP0 M_OCDOCMP1 5,28 H_CPUSLP# D PAD T3 PAD T4 C CLK PM HADS# HTRDY# HDPWR# HDRDY# HDEFER# HEDRDY# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2# DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AA31 AB35 AC31 AD35 NC F8 B5 G6 H_DRD Y# F7 H_DEFER# E6 TP_H_EDRDY# F6 H_HITM# D6 H_HIT# D4 H_LOCK# B3 H_BR0# E7 H_BNR# A5 H_BPRI# D5 H_DBSY# C6 H_R_CPUSLP# G8 H_RS#0 A4 H_RS#1 C5 H_RS#2 B4 H_ADS# H_TRDY# H_SWNG0 29 29 29 29 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 C901 0.1U_0402_16V4Z H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# T6 PAD H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# +VCCP DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 C900 0.1U_0402_16V4Z 5 5 29 29 29 29 HCPURST# R94 100_0603_1% H10 H_RESET# H_RESET# H_SWNG1 U2B R89 100_0603_1% HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3 +VCCP B G4 K1 R3 V3 G5 K2 R2 W4 H8 K3 T7 U5 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 5 5 5 5 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 HCLKN HCLKP Note : CFG3:17 has internal pullup, CFG18:19 has internal pulldown R96 200_0603_1% Layout Guide will show these signals routed 5 differentially AB1 AB2 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 C74 0.1U_0402_16V4Z H_DSTBP#[0 3] HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2 C71 0.1U_0402_16V4Z 17 CLK_MCH_BCLK# 17 CLK_MCH_BCLK H_DSTBN#[0 3] A11 A7 D7 B8 C7 A8 B9 E13 H_D#[0 63] HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# Alviso R92 54.9_0603_1% H_ADSTB#0 H_ADSTB#1 TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 H_ADSTB#1 HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# R91 54.9_0603_1% T5 PAD H_REQ#[0 4] G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13 R97 24.9_0603_1% H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 D C U2A H_A#[3 31] HOST R98 24.9_0603_1% Note: "Do not install R99 for Dothan-A, Install R99 for Dothan-B" PM_EXTTS#0 R102 10K_0402_5% PM_EXTTS#1 R103 10K_0402_5% A A Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Alviso(1 of 5) Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet of 59 14 DDR_A_BS#0 14 DDR_A_BS#1 T18 PAD 15 DDR_A_DM[0 7] 15 DDR_A_DQS[0 7] DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 AK15 AK16 AL21 SA_BS0# SA_BS1# SA_BS2# DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3 SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# C 14 DDR_A_MA[0 13] 14 DDR_A_CAS# 14 DDR_A_RAS# T20 PAD T22 PAD 14 DDR_A_WE# DDR MEMORY SYSTEM A U2C D DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 DDR_A_CAS# DDR_A_RAS# TP_MA_RCVENIN# TP_MA_RCVENOUT# DDR_A_WE# AN15 AP16 AF29 AF28 AP15 SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# B SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63 AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 U2D DDR_A_D[0 63] 15 15 DDR_B_BS#0 15 DDR_B_BS#1 T19 PAD DDR_B_BS#0 AJ15 DDR_B_BS#1 AG17 DDR_B_BS#2 AG21 This Symbol as same as Intel CRB schematic, So Layout Guide will show these signals routed differentially 15 DDR_B_MA[0 13] 15 DDR_B_CAS# 15 DDR_B_RAS# T21 PAD T23 PAD 15 DDR_B_WE# ALVISO_BGA1257 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 D SB_BS0# SB_BS1# SB_BS2# AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 DDR_B_CAS# AH14 DDR_B_RAS# AK14 TP_MB_RCVENIN# AF15 TP_MB_RCVENOUT# AF14 DDR_B_WE# AH16 DDR SYSTEM MEMORY B SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE# SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63 AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5 C B ALVISO_BGA1257 A A Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Alviso(2 of 5) Size Document Number Date: Wednesday, March 02, 2005 Rev 1B EDL71 LA-2351 Sheet 10 of 59 A B C D Left Speaker Connector +5VAMP Right Speaker Connector Audio Amplifier E R459 100K_0402_5% SHUTDOWN# AMP_RIGHT HP_L HP_R 21 23 20 17 TPA0232PWP_TSSOP24 C567 1 @ 2 @ R465 1.5K_0603_5% 0.1U_0402_16V4Z R466 1.5K_0603_5% ACES_85203-1202 @ R463 10K_0402_5% NBA_PLUG C5571 20.1U_0402_16V4Z 12 13 24 41,44 22 15 14 11 16 10 PVDD SHUTDOWN# PVDD SE/BTL# VDD PC-BEEP BYPASS HP/LINE# LOUTVOLUME ROUTLOUT+ LIN ROUT+ RIN LLINEIN RLINEIN GND LHPIN GND RHPIN GND GND CLK 18 19 EAPD R462 100K_0402_5% U23 C559 1U_0603_10V4Z C561 1U_0603_10V4Z AMP_LEFT C562 0.47U_0603_16V4Z AMP_RIGHT C566 0.47U_0603_16V4Z 2 S EC_MUTEO 41 INTSPK_L2INTSPK_R2- 44 C568 0.047U_0402_16V4Z C563 C564 NBA_PLUG INTSPK_L1+ INTSPK_L2INTSPK_R1+ INTSPK_R2- L75 L77 L76 L78 INTSPK_R1-3 INTSPK_L1-3 L79 10_0603_5%2 L80 10_0603_5%2 INTSPK_R1-3_C INTSPK_L1-3_C MIC-1 MIC-2 L81 10_0603_5%2 L82 10_0603_5%2 MIC-1_C MIC-2_C L83 10_0603_5%2 NBA_PLUG_C NBA_PLUG C565 10_0603_5%2 10_0603_5%2 10_0603_5%2 10_0603_5%2 INTSPK_L1+_C INTSPK_L2-_C INTSPK_R1+_C INTSPK_R2-_C 10 11 12 10 11 12 JP36 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 24 INTSPK_L1+_C INTSPK_L2-_C INTSPK_R1+_C INTSPK_R2-_C INTSPK_R1-3_C INTSPK_L1-3_C MIC-1_C MIC-2_C NBA_PLUG_C 44 AMP_LEFT C558 0.47U_0603_16V4Z AMP_RIGHT C560 0.47U_0603_16V4Z AMP_LEFT +5VAMP C556 4.7U_0805_10V4Z CH751H-40_SC76 2 D36 G 2N7002_SOT23 Q19 L92 0_0603_5% 44 INTSPK_L1+ INTSPK_R1+ 1 NBA_PLUG 0_0402_5% VOLAMP R464 VOL_AMP 41 0.47U_0603_16V4Z C555 C975 0.47U_0603_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z D 0.47U_0603_16V4Z W=40Mil CH751H-40_SC76 D35 +5VAMP CHANGE CONN 3 fo=1/(2*3.14*R*C)=225Hz R=1.5K / C=0.47U HEADPHONE OUT JACK EC Beep 41 System Beep To AC97' Codec BEEP# +3VALW +3VALW R467 47_0402_5% 2INTSPK_R1-2 INTSPK_R1-3 150U_4A_6.3VM INTSPK_L1+ INTSPK_L1-2 2 INTSPK_L1-3 C571 150U_4A_6.3VM R469 47_0402_5% R470 8.2K_0402_5% I U25A SN74LVC14APWLE_TSSOP14 O G 0.1U_0402_16V4Z +AVDD_AC97 C574 1U_0603_10V4Z +3V POWER 74AHCT1G125GW_SOT353-5 C575 0.22U_0603_16V4Z 2 R471 560_0402_5% 14 U24 Y C570 P P A G OE# C572 0.1U_0402_16V4Z R468 100K_0402_5% + INTSPK_R1+ + C569 +5VS R472 10K_0402_5% MICROPHONE IN JACK +3V POWER 2 C576 10U_0805_10V4Z R473 10K_0402_5% 32 PCM_SPK# C577 MONO_IN 1U_0603_10V4Z MONO_IN 44 C578 CardBus Beep R475 560_0402_5% Q21 MMBT3904_SOT23 1U_0603_10V4Z R476 2.4K_0402_5% PCI Beep I U25B +AUD_VREF C580 O +3V POWER 1U_0603_10V4Z SN74LVC14APWLE_TSSOP14 R482 560_0402_5% 44 R483 10K_0402_5% D17 CH751H-40_SC76 MIC-2 MIC-1 MIC SPKR G 29 P 14 +3VALW Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Audio_AMP&JACKs Size Document Number Date: Wednesday, March 02, 2005 R ev 1B EDL71 LA-2351 Sheet E 45 of 59 A B C D E +5VS +3VS CF15 CF16 CF17 CF7 CF18 CF8 CF19 CF9 CF11 1 CF20 CF21 CF22 CF12 CF23 29 IDERST_HD# PLTRST# 9,27,29,35,39,41 PLTRST# CF24 14 U54A EC_IDERST 41,44 EC_IDERST P CF6 CF5 A O B A U54B B 74VHC08MTC_TSSOP14 HD_IDERST# O HD_IDERST# 31,43 74VHC08MTC_TSSOP14 CF14 CF4 G CF13 CF3 CF2 14 10K_0402_5% CF1 +5VS 0.1U_0402_16V4Z P C905 G 1 R769 CF25 FD4 FD5 +3VS FD6 +3VALW +5VS H16 HOLEE H17 HOLEE H18 HOLEE H19 HOLEE H20 HOLEE A 12 B 74VHC08MTC_TSSOP14 P 13 O B 14 74VHC08MTC_TSSOP14 NOSWDJ@ R1208 0_0402_5% +5VS H DD_IRQ D IDE_IRQ 28,31 IDE_IRQ +3VALW 80 mil HDD_IRQ 31 +5VALW HD_IDERST# U55ASWDJ@ O SIDE_RST# SIDE_RST# 31 NOSWDJ@ 0_0402_5% R1158 Q98 2N7002_SOT23 SWDJ@ I SN74LVC125APWLE_TSSOP14 SWDJ@ R773 10K_0402_5% H30 HOLEE P SD_IDERST# 11 80 mil R1159 0_0805_5% NOSWDJ@ Q69 SWDJ@ +5VCD SI2301BDS_SOT23 G 1 H29 HOLEE H28 HOLEE 1 1 H27 HOLEE 1 H26 HOLEE H25 HOLEE U54C O D H24 HOLEE A S H23 HOLEE 1 H22 HOLEE 1 H21 HOLEE SWDJ@ G U54D R772 10K_0402_5% SWDJ@ 14 PLTRST# PCMRST# PCMRST# G H11 HOLEE 10 IDERST_CD# H13 HOLEE 29 1 1 1 1 1 +5VS H12 HOLEE 41 10K_0402_5% H10 HOLEE R1198 SWDJ@ SWDJ@ +3VS 10K_0402_5% 1 SWDJ@ C908 10U_0805_10V4Z 2 C907 10U_0805_10V4Z SWDJ@ C909 0.1U_0402_16V4Z SWDJ@ 14 R775 10K_0402_5% SWDJ@ 1U_0603_10V4Z SWDJ@ Q70 DTC124EK_SC59 SWDJ@ NOSWDJ@ R1209 0_0402_5% U25D Q71 DTC124EK_SC59 SWDJ@ I R1141 O 0_0402_5% SN74LVC14APWLE_TSSOP14 VS_ON1 53 SUSP# 35,39,41,44,47 SUSP# SN74LVC14APWLE_TSSOP14 R1142 100K_0402_5% R1160 0_0402_5% NOSWDJ@ +5VCD 2 CD_PLAY 41,44 CD_PLAY +3VALW +3VALW 0_0402_5% 10K_0402_5% SWDJ@ VS_ON2 PLTRST# SW_IDE_SDCS1# SW_IDE_SDCS1# 31 +5VCD D G S Q72 2N7002_SOT23 SWDJ@ VCC= +3VALW 28,31 IDE_DCS3# G_PCI_RST# O R1196 100K_0402_5% I SN74LVC125APWLE_TSSOP14 53 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 28,31 IDE_DCS1# 13 O R1139 R782 10K_0402_5% SWDJ@ SWDJ@ U55C 12 I R785 10K_0402_5% SWDJ@ U55D SWDJ@ OE# I 12 14 13 G O 10 I U25F P P U25E G 11 VS_ON1 R1195 100K_0402_5% C1129 0.022U_0402_16V7K 53 VS_ON11 14 R783 OE# 10 VCC= +3VALW +3VALW O O G I HDD_IOR# 31 P P 14 U25C O C910 SWDJ@ SN74LVC125APWLE_TSSOP14 +3VALW G C1100 0.1U_0402_16V7K 35,39,41,44,47 SUSP# R1140 20K_0402_5% SUSP# I U55B SWDJ@ 240K_0402_5% R774 28,31 IDE_DIOR# +3VALW +5VALW 10K_0402_5% R1200 Q97 2N7002_SOT23 SWDJ@ S HD_IDERST# G OE# D 2 H9 HOLEE 14 H8 HOLEE P H7 HOLEE G H6 HOLEE H5 HOLEE H4 HOLEE S H3 HOLEE G H2 HOLEE 0.1U_0402_16V4Z R771 H1 HOLEE +5VCD C906 1 1 FD2 FD3 OE# FD1 SW_IDE_SDCS3# 11 SW_IDE_SDCS3# 31 SN74LVC125APWLE_TSSOP14 NOSWDJ@ R1161 0_0402_5% Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D SW DJ,RESET CKT,SW,LED BOAR Size Document Number Date: Wednesday, March 02, 2005 R ev 1B EDL71 LA-2351 Sheet E 46 of 59 +5VALW to +5VS Transfer +12VALW +5V +5VALW to +5V Transfer S 1 C738 R679 + D C739 22U_A_4VM 470_0402_5% SI4800BDY_SO8 2 2@ C741 C740 S S S S G 0.1U_0402_16V4Z Q95 SYSON# G 2N7002_SOT23 D D D D D Q34 S SUSP G 2N7002_SOT23 D Q33 G 4.7U_0805_10V4Z D 0.1U_0402_16V4Z SUSP 1@ 0.01U_0402_16V7Z C1059 10K_0402_5% +12VALW 2N7002_SOT23 R1177 10U_0805_10V4Z C1058 Q45 C142 1M_0402_5% 0.47U_0603_16V4Z 1 D +5VS R678 10K_0402_5% R680 G +5VALW 0.1U_0402_16V4Z C1057 S D 2N7002_SOT23 Q79 +5VALW +5VALW RUNON R681 10K_0402_5% 4.7U_0805_10V4Z +3VALW R682 C745 0.1U_0402_16V4Z D S C +3VS +12VALW Q36 SYSON# G 2N7002_SOT23 + 2 D D D D S S S G 0.1U_0402_16V4Z C747 C746 22U_A_4VM + SI4800BDY_SO8 C748 SYSON 39,41,52 SYSON +3VALW to +3VS Transfer Q47 10K_0402_5% SYSON# SYSON# D S Q35 2N7002_SOT23 G R684 C 470_0402_5% 10U_0805_10V4Z 40 C742 +5VALW D RUNON Q37 SUSP G 2N7002_SOT23 R683 10K_0402_5% S SI4800BDY_SO8 0.1U_0402_16V4Z C743 1 CE2 100U_C_4VM 4.7U_0805_10V4Z S S S G C744 D D D D +3VALW to +3V Transfer +3V Q46 +3VALW D Q38 S 2N7002_SOT23 G 35,39,41,44,46 SUSP# +2.5V to +2.5VS Transfer +2.5V SUSP 52,54 SUSP +2.5VS C1128 22U_A_4VM B 2 Discharge circuit C1072 + C1073 22U_A_4VM B 2N7002_SOT23 SUSP D Q39 S 2N7002_SOT23 G +5V +3V A Q43 SYSON# G 2N7002_SOT23 R1064 470_0402_5% D Q80 S SYSON# G 2N7002_SOT23 R602 470_0402_5% SI4800BDY_SO8 Q41 S D SUSP G 3 R738 470_0402_5% 3 2N7002_SOT23 Q40 S R741 470_0402_5% D SUSP G S S S S G +1.5VS 1 +2.5VS R745 470_0402_5% D D D D D RUNON +1.25VS A + C1075 10U_0805_10V4Z 0.1U_0402_16V4Z Q82 Compal Electronics, Inc Title DC/DC Circuits THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Rev 1B EDL71 LA2351 Date: Sheet Wednesday, March 02, 2005 47 of 59 A B C D Vin Detector Min typ Max H >L 16.976V 17.257V 17.728V L >H 17.430V 17.901V 18.384V PR1 - PR3 AC IN O PACIN PU4B LM393M_SO8 29,41,51 PACIN 49 PR8 10K_0402_5% PR10 1.5K_1206_5% PR9 ACIN + 2 PC5 1000P_0402_50V7K RLZ24B_LL34 PJP12 3MM DCI N- PZD1 PR7 20K_0402_1% 1 PC4 560P_0402_50V7K @ OC8070-A301~D PL20 2 PR6 22K_0402_5% PZD2 RLZ4.3B_LL34 PC3 12P_0402_50V8J SINGA_2DC-G213-B04 PR5 10_1206_5% PR4 10K_0402_5% P VS PR2 84.5K_0402_1% G 0.1U_0603_25V7K PC2 12P_0402_50V8J G G PC1 560P_0402_50V7K VIN 1M_0402_1% PC6 1 P1 1 FBM-L18-453215-900LMA90T_1812 PL1 P1 PJPD1 1 VIN VIN 10K_0402_5% 1 RTCVREF 10K_0402_5% PD1 1N4148_SOD80 VIN+ VIN @ PR174 100K_0402_5% VS PU1A LM393M_SO8 6C/8C# 49 BATT++ + - O PR13 1.5K_1206_5% PR14 2.2M_0402_5% VL PR175 @1K_0402_5% B+ PR25 100_0402_5% B 2 1 2 G PR24 47K_0402_5% PACIN 49 PQ2 DTC115EUA_SC70 PR26 66.5K_0402_1% +5VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A RHU002N06_SOT323 PQ1 S BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V D PC10 1000P_0402_50V7K VL PR20 499K_0402_1% EC_SMC_1 Precharge detector Min typ Max 26,41,42 H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V PR23 34K_0402_1% 1 ACIN PR19 191K_0402_1% PRG++ PC11 0.1U_0603_25V7K 2 EC_SMD_1 26,41,42 PR22 100_0402_5% - + O PC12 1000P_0402_50V7K +3VALWP PR21 25.5K_0402_1% RB715F_SOT323 PR17 499K_0402_1% PU1B LM393M_SO8 P ACON PD2 PC9 0.01U_0402_25V7Z 1 49 8,50,51 MAINPWON PR18 1K_0402_5% G SM ART Batter y: 1.BAT+ ID B/I 4.TS 5.SMD SMC GND PR16 100K_0402_1% PJPB1 battery connector BATT_TEMP 41 PR15 1K_0402_5% BATT_TEMP PJP1 SUYIN_200275MR007G161ZL VS PC7 0.01U_0402_25V7Z PC8 1000P_0402_50V7K 2 2 B+ PR12 1.5K_1206_5% +3VALWP @ PR176 1K_0402_5% PL2 HCB4532K-800T90_1812 1 P BATT++ G BATT+ BATT+ PR11 1.5K_1206_5% C Compal Electronics, Inc DCIN & DETECTOR & Precharge Document Number Rev 1B EDL71 LA-2351 Wednesday, March 02, 2005 D Sheet 48 of 59 A B C D E Charger Iadp=0~2.9A(65W) CHG_B+ P3 2 PC17 2200P_0402_50V7K 1 PR31 10K_0402_5% ACOFF# CS 22 -INE2 VCC(o) 21 FB2 OUT 20 PC20 0.1U_0603_25V7K VREF VH 19 FB1 PC19 2200P_0402_50V7K 2 17 -INE1 RT +INE1 -INE3 16 10 OUTC1 FB3 15 OUTD CTL 14 12 -INC1 +INC1 13 PL4 16UH_D104C-919AS-160M_3.7A_20% FSTCHG 41 PR38 66.5K_0402_1% PR39 0.02_2512_1% PR42 47K_0402_5% 2 PC27 1500P_0402_50V7K BATT+ BATT+ PD5 EC31QS04 2 11 PC25 0.1U_0603_25V7K 2 PC29 4.7U_1206_25V6K PR41 10K_0402_5% PC31 0.01U_0402_25V7Z VCC LXCHRG PC23 0.1U_0603_25V7K 18 PD4 1SS355_SOD323 PQ9 DTC114EKA_SC59 PC28 4.7U_1206_25V6K PC24 2200P_0402_50V7K 10K PR36 10K_0402_5% 2 PR44 10K_0402_5% MB3887_SSOP24 ACON PR46 49.9K_0603_0.1% D S 3 BATT+ PR177 @ 150K_0603_0.1% IREF=1*Icharge IREF=0~3.3V G PQ36 @RHU002N06_SOT323 PR47 150K_0603_0.1% VS VS 2 P PR49 300K_0603_0.1% + - PQ37 DTC115EKA_SC59 OVP voltage : LI-3S :17.8V BATT-OVP=1.9758V BATT-OVP=0.111*BATT+ @ 41 BATT_OVP G 2 Charge voltage For 4S battery only.PR46=49.9K 4S CC-CV MODE : 16.83V For 3S/4S battery.PR46=75K, PR177=150K,PQ36=2N7002,PR178=100K PC152=0.1U,PQ37=DTC115EKA PR174=100,PR176=1K 4S CC-CV MODE : 16.8V 4S CC-CV MODE : 12.6V 6C/8C# 48 PC152 @ 0.1U_0402_16V8K PU3A LM358A_SO8 PR179 @ 100K_0402_5% 1 PR178 @ 100K_0402_5% 2 PC32 0.01U_0402_25V7Z PR48 845K_0603_1% 2P4S:4300mAH/cell 0.7C=3.0A 10K 23 GND 2 PC22 4700P_0402_50V7K PR37 1K_0402_5% 2 PC26 0.1U_0603_25V7K PR45 22K_0402_5% +INE2 PR43 120K_0402_1% PR40 180K_0402_1% OUTC2 ACOFF PD3 1SS355_SOD323 ACON RHU002N06_SOT323 PQ11 IREF S 1 48 41 G PD6 1SS355_SOD323 D 2 PR35 24.9K_0402_1% PACIN PR34 75K_0402_1% S PQ10 RHU002N06_SOT323 48 41 +INC2 24 -INC2 PR32 100K_0402_1% PC21 0.01U_0402_25V7Z 3 PQ8 DTC115EUA_SC70 PR33 150K_0402_5% 1 D ACOFF# PZD3 RLZ22B_LL34 PU2 2 G VIN PQ7 AO4407_SO8 1 PR29 47K_0402_5% 2 PL3 HCB4532K-800T90_1812 3 1 AO4407_SO8 PQ5 PC16 0.1U_0603_25V7K 2 1 2 PC18 0.1U_0603_25V7K 47K PC14 10U_1206_25V6K PR30 200K_0402_1% 47K PR28 47K_0402_5% PQ6 DTA144EUA_SC70 1 PC13 10U_1206_25V6K 1 PR27 0.02_2512_1% VIN B+ PQ4 AO4407_SO8 P2 PQ3 AO4407_SO8 PR50 143K_0402_1% PC33 0.01U_0402_25V7Z Compal Electronics, Inc Title PROPRIETARY NOTE A B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: C D Charger Document Number Rev 1B EDL71 LA-2351 Sheet Wednesday, March 02, 2005 E 49 of 59 A B C D 1 VIN PD9 1N4148_SOD80 1 PH2 under CPU botten side : CPU thermal protection at 80 degree C Recovery at 44(45) degree C PR63 33_1206_5% PR54 47K_0402_1% VL VS PR64 200_0805_5% PC40 0.22U_1206_25V7K PC39 0.1U_0603_25V7K IN OUT 1 O MAINPWON 8,48,51 LM393M_SO8 VL PR67 300_0402_5% CHGRTC PR68 300_0402_5% 2 - PR62 150K_0402_1% GND PC41 1U_0805_25V4Z PU4A CHGRTCP + PR59 150K_0402_1% PU5 G920AT24U_SOT89 3 1 PC35 1U_0805_16V7K PC36 1000P_0402_50V7K RTCVREF PH2 PR66 22K_0402_5% 10KB_0603_1%_TH11-3H103FT 51ON# PR52 150K_0402_1% PR55 20.5K_0402_1% TM_REF1 43 VL 2 PR65 100K_0402_5% 1 PR57 1.82K_0603_1% VS PC34 2 TP0610K_SOT23 P PQ13 RB751V_SOD323 G 0.1U_0603_25V7K PD10 BATT+ PC42 4.7U_0805_6.3V6K 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR Size B THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Compal Electronics, Inc RTC Battery & OTP Document Number Rev 1B EDL71 LA-2351 Wednesday, March 02, 2005 D Sheet 50 of 59 A B C D E +3.3V/+5V/+12V +3VALWP Choke DCR = 26.5m [ Current limit Threshold Min.=80 mV Mx.=120mV OCP Min.= 80mV/1.27K*(1.27K+1.27K)/26.6=6.038A OCP Max.=120mV/1.27K*(1.27K+1.27K)/26.5=9.056A PC43 10U_1210_25V6K 1 PD12 EC11FS2_SOD106 BST51 SNB FLYBACK PR70 @ 22_1206_5% B++ 28 RUN/ON3 1 PC51 4.7U_1206_25V6K PC50 @2200P_0402_50V7K 2 1 PC54 4.7U_1206_25V6K 1 BST5 PR77 2M_0402_1% DH5 LX5 DL5 2.5VREF PR78 1.54K_0402_1% PC57 0.47U_0603_16V7K PR81 698_0402_1% PR84 0_0402_5% PC61 4.7U_0805_10V4Z +5VALWP MAX1902EAI_SSOP28 GND TIME/ON5 22 18 16 17 19 20 14 13 12 15 11 CSH3 CSL3 FB3 SKIP# SHDN# PC53 47P_0402_50V8J 1 10 23 VL LX3 DL3 12OUT VDD BST5 DH5 LX5 DL5 PGND CSH5 CSL5 FB5 SEQ REF SYNC RST# @ PR82 300K_0402_5% 2 PC58 100P_0402_50V8J 26 24 PR73 0_0402_5% 1 + PC63 100P_0402_50V8J PD17 SKS10-04AT_TSMA 2 VS PC62 150U_D2_6.3VM MAINPWON 8,48,50 PR87 0_0402_5% PR86 10K_0402_1% PR85 10.2K_0402_1% PC60 1000P_0402_50V7K @ PR80 10K_0402_5% DH3 AO4912_SO8 2 PD16 SKUL30-02AT_SMA PR83 3.57K_0402_1% + PD15 SKS10-04AT_TSMA 150U_D2_6.3VM PC59 ACIN BST3 27 S PR72 @ 2.7K_1206_5% 25 V+ PC56 0.47U_0603_16V7K D G G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A 21 PU6 2 PR75 1.27K_0402_1% PR79 619_0402_1% 29,41,48 ACIN PQ16 @ RHU002N06_SOT323 PC52 0.1U_0603_25V7K PC55 47P_0402_50V8J PR76 1M_0402_1% 2 DL3 PC49 4.7U_0805_10V4Z PR190 10_1206_5% PR71 0_0402_5% DH3 LX3 +3VALWP PQ15 VL 2 PR74 1.27K_0402_1% +12VALWP PD14 1SS355_SOD323 AO4912_SO8 PL7 10UH_D104C-919AS-100M_4.5A_20% PD13 DAP202U_SOT323 D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K 1 PC48 4.7U_1206_25V6K 2 @ PC47 2200P_0402_50V7K PQ14 PL6 9U_SDT-1204P-9R0-120_4.5A_20% PC46 0.1U_0603_25V7K VS B++ PC45 0.1U_0603_25V7K BST31 FBM-L18-453215-900LMA90T_1812 PC44 @470P_0805_100V7K PL5 2 B+ 2 PC65 @ 1U_0805_25V4Z 1 PR88 10K_0402_1% PC64 0.47U_0603_16V7K +5VALWP Choke DCR = 40mΩ Current limit Threshold Min.=80 mV Mx.=120mV OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A 4 RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3) L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56) Compal Electronics, Inc Title 3.3V / 5V / 12V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Size B Date: Document Number Rev EDL71 LA-2351 1B Sheet Wednesday, March 02, 2005 E 51 of 59 +1.2VSP TP PC71 2@ 4.7U_1206_25V6K S VS PU3B - 2@ PC75 4700P_0402_25V7K S PQ18 RHU002N06_SOT323 G PR93 0_0402_5% +1.25VSP @ PC73 150U_D2_6.3VM PR96 2@ 5.1K_0402_5% 2@ PQ19 RHU002N06_SOT323 G SUSP 47,54 S C 2 2.5VREF PR191 2@ 0_0402_5% D PC74 4.7U_0805_6.3V6K + C 1 PC76 2@ 68P_0402_50V8K PR94 2@ 200K_0402_1% 1 PC70 2@ 22U_1206_10V6M SUSP 47,54 LM358A_SO8 D PC69 @ 150U_D2_6.3VM PC72 2@ 220P_0603_50V8J PR95 2@ 187K_0402_1% 2 0.1U_0603_25V7K PC68 1 PR90 1K_0402_1% D APL5331KAC-TR_SO8 + + PR92 2@ 0_0402_5% PR91 2@ 5.1K_0402_5% NC 1 NC VOUT VREF +1.2VSP PR89 1K_0402_1% 1 PC67 10U_1206_6.3V7K PC66 1U_0603_16V6K G NC +1.5VSP GND +3VALW VIN VCNTL PU7 D PQ17 2@ SI3456DV-T1_TSOP6 D +2.5VP @ PC195 0.1U_0402_16V7K PL8 FBM-L11-322513-151LMAT_1210 EN SS 13 ISNS 12 2 + @ PC81 PR106 2.74K_0603_1% PC90 0.01U_0402_16V7K PGND VSEN VOUT A PGOOD AGND + PC87 220U_D2_4VM SW @ PC86 330U_V_2.5VM LDRV 10 +2.5VP PR108 1K_0402_1% PR105 0_0402_5% PC85 0.1U_0603_25V7K 1 1.8UH_D104C-919AS-1R8N_9.5A_20% PL11 FPWM 0_0402_5% 39,41,47 SYSON 16 2 PR102 0_0402_5% 1 PR103 AO4912_SO8 PC89 4.7U_0805_6.3V6K 14 ILIM 93.1K_0603_1% B PR104 1.8K_0603_1% HDRV PD18 RB751V_SOD323 15 @ D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K BOOT 1U_0805_25V4Z 11 PQ21 PC88 0.1U_0603_25V7K VCC 1U_0805_25V4Z VIN PU8 PR101 PR99 10_0603_5% PC84 @ B 1 PR98 10_1206_5% PC83 0.1U_0603_25V7K 1 +5VALW PC80 4.7U_1206_25V6K PC79 4.7U_1206_25V6K 2 @ PC78 2200P_0402_50V7K 1 PC77 0.1U_0603_25V7K B+ A Compal Electronics, Inc FAN5234QSCX_QSOP16 Title 1.25VSP/2.5VP/1.2VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size B Date: Document Number Rev 1B EDL71 LA-2351 Sheet Wednesday, March 02, 2005 52 of 59 A B C D 1 11 10 2 PC98 4.7U_1206_25V6K @ + PD21 SKUL30-02AT_SMA PC107 150U_D2_6.3VMV PC106 150U_D2_6.3VMV @ + 499_0402_1% @ 1 VS_ON2 46 PR115 0_0402_5% PR117 10K_0402_1% 13 ILIM2 ILIM1 PR118 49.9K_0402_1% 1 PR119 62K_0603_1% PC109 0.22U_0603_16V7K PR114 DL2.5 PGOOD TON REF SKIP OVP DH2.5 +VCCPP OUT2 FB2 ON2 15 14 12 @ PR198 0_0402_5% 19 18 17 20 16 ON1 PR107 10K_0402_1% GND PL12 1.8UH_D104C-919AS-1R8N_9.5A_20% LX2.5 4.7U_0805_6.3V6K PC108 22 MAX8743EEI_QSOP28 VS_ON1 PU9 FB1 23 46 PR116 0_0402_5% BST2 DH2 LX2 DL2 CS2 Assume that PR107=10K ohm, then 1.5V=1*(1+PR168/PR107), so PR168=5K ohm 21 CS1 OUT1 PR121 100K_0402_1% LX1 DL1 28 PC102 0.1U_0603_25V7K BST2.5A VDD PR120 100K_0402_1% 27 24 UVP DH1 @ 26 V+ BST1 VCC PR168 5.1K_0402_1% 25 AO4912_SO8 PR113 0_0402_5% 2 2 PR112 20_0603_5% G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A 1 MAX1845_VCC 1 @ PQ24 1U_0805_50V4Z PC100 0.1U_0603_25V7K PC99 2 PC105 4.7U_0805_6.3V6K PC103 150U_D2_6.3VMV + PD20 EP10QY03 BST2.5B PR111 0_0402_5% PC101 4.7UH_D104C-919AS-4R7N_5.2A_20% PL9 2 @ 0.1U_0603_25V7K AO4912_SO8 +1.5VSP G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A 2 PQ23 PC94 4.7U_0805_6.3V6K PD19 DAP202U_SOT323 PC97 4.7U_1206_25V6K 1 @ B+ +5VALW PC96 2200P_0402_50V7K FBM-L18-453215-900LMA90T_1812 PL10 PC93 4.7U_1206_25V6K PC92 2200P_0402_50V7K B++++ MAX1845_VCC PR196 33K_0402_1% 1 PR197 11K_0402_1% D PQ41 2N7002_SOT23 G VS_ON2 46 S Compal Electronics, Inc Title +VCCPP & +VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Size B Date: Document Number Rev 1B EDL71 LA-2351 Wednesday, March 02, 2005 D Sheet 53 of 59 A B +3VALW 2@ 5U_TPRH6D38-5R0M-N_2.9A_20% PL18 2@ CM3718_PSOP8 SUSP +1.8VSP + PC147 220U_D2_4VM 2@ +5VALW @ PC150 560P_0603_50V7K 2 PR171 2@ 0_0402_5% 2@ PC148 4.7U_0805_6.3V6K PC149 2@ PR169 220P_0603_50V8J 1K_0402_5% 2 PVIN LX PGND VFB PR170 2@ 100K_0402_5% VIN GND SD VREF 1 2 47,52 D +3VALW PU13 2@ PC146 0.1U_0603_25V7K C 1 PR172 2@ 100K_0402_5% D 2 FB PHASE 2@ AO4912_SO8 PL19 2@ 1.8UH_D104C-919AS-1R8N_9.5A_20% +12VALWP 2 +3VALW +1.5VSP 1 PR187 G PQ40 +2.5VP +2.5V +1.8VSP +VCCP +1.25VSP +1.2VSP VGA_CORE H 1.0V L 1.2V +3VS VGA_CORE for ATI-M24 +1.25VS PR200 2@ 100K_0402_5% PJP10 3MM PJP9 3MM 1 @PC161 0.01U_0402_25V7Z +VGA_CORE_P +VCCPP PJP8 3MM POWER_SEL# 2@ 0_0402_5% PJP7 3MM +1.8VS POWER_SEL 1 PJP6 3MM 2 PJP5 3MM S 2@ RHU002N06_SOT323 PC159 4.7U_0805_6.3V6K 2@ D +1.5VS +VGA_CORE POWER_SEL# +1.2VS PR199 2@ 0_0402_5% S PQ45 2@ 2N7002_SOT23 PC165 2@ 0.1U_0402_16V4Z D G 18 POWER_SEL 1 PR186 2@ 43.2K_0402_1% +3VALWP PJP4 3MM + +12VALW PR185 2@ 34K_0402_1% PJP3 3MM 1 +5VALW 10K_0402_1% 2@ LGATE PR184 GND 2@ APW7057KC-TR_SOP8 PJP2 2MM +VGA_CORE_P +VGA_CORE PC160 2 +5VALWP UGATE PC158 2@ 220U_D2_4VM_R15 G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A 2@ 0.1U_0402_16V7K PJP11 3MM S 2@RHU002N06_SOT323 @ D G PR183 2@ 0_0402_5% PC157 0.1U_0402_16V7K SUSP BOOT 2@ OCSET PQ39 1 VCC 0.1U_0402_16V7K 2@ 1SS355_SOD323 PU14 47,52 PQ38 PD26 2@ 12.7K_0402_1% PC156 2 PR182 2@ 255K_0402_1% PC151 2@ 0.01U_0603_16V7K PR181 PC153 2@ 4.7U_0805_6.3V6K PR180 2@ 2.2_0402_5% PC154 2@ 0.1U_0402_16V7K 2 2.5VREF PC155 2@ 470P_0402_50V7K PR173 2@ 100K_0402_1% 2 SUSP 47,52 PQ35 2@ RHU002N06_SOT323 2 G S Compal Electronics, Inc Title 1.8VSP/VGA_CORE_P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Size B Date: Document Number Rev 1B EDL71 LA-2351 Wednesday, March 02, 2005 D Sheet 54 of 59 CPU_B+ B+ +5VS FB 15 CCV CCI 14 LXS 34 PC127 100U_25V_M PC126 100U_25V_M PC125 2200P_0402_50V7K PC124 0.01U_0402_25V7K D D D D C @ D D D D 2.2_0603_5% 18 SKIP CSN 39 11 GND GNDS 13 MAX1532AETL_TQFN40 PQ31 AO4408_SO8 B PR161 @ 100K_0402_1% PL17 0.56UH_MPC1040LR56 23_21A_20% 2 B PR157 0_0402_5% CPU_B+ PD24 EP10QY03 AO4410_SO8 PQ32 RHU002N06_SOT323 PC137 0.022U_0402_16V7K PC143 0.01U_0402_25V7K PR154 3K_0603_1% @ 909_0402_1% 40 32 CSP DLS SUS PC142 4.7U_1206_25V6K OFS PC141 4.7U_1206_25V6K +5VS PR166 PQ34 HMBT2222A_SOT23 909_0402_1% 1 E G S S S PR204 PR164 10K_0402_1% PQ33 G PR152 470P_0402_50V8J PR162 20K_0402_1% 1 0.47U_0603_16V7K PC135 PC144 27P_0402_50V8J PC139 FB PC133 1000P_0402_50V7K TIME PR148 3K_0603_1% 1 12 PC132 499_0402_1% 16 CPU VCC SENSE PR147 OAIN- ILIM S D 0.001_2512_5% 499_0402_1% SHDN# D + PR140 PR146 @ @ 909_0402_1% 17 PR145 38 OAIN+ PD23 EC31QS04 2 @ PR201 @ PC200 4.7_1206_5% 680P_0603_50V8J PR143 100K_0402_1% CMN S1 S0 G S S S AO4410_SO8 PQ28 37 0.22U_0603_16V7K S CMP 33 C VROK 35 D PSI# 25 DHS PR165 100K_0402_1% 31 G S S S +5VS 29 PGND DLM D5 BSTS G PR160 0_0402_5% 29 PM_DPRSLPVR D4 19 REF S 20 TON PQ30 RHU002N06_SOT323 PR158 PQ29 RHU002N06_SOT323 29 PM_STP_CPU# B D G 27 PC138 100P_0402_50V8J PR156 100K_0402_1% LXM PC136 D3 PR153 200K_0402_1% 10.7K_0402_1% FB 270P_0402_50V7K 21 2 @ PR202 4.7_1206_5% @ PC201 680P_0603_50V8J PR155 78.7K_0603_1% 2 +CPU_CORE PD25 EC31QS04 PC1341 + PL16 0.56UH_MPC1040LR56 23_21A_20% PC140 2200P_0402_50V7K 2 30.1K_0402_1% 28 PR151 DHM D D D D D2 G S S S VR_ON 22 PR136 2.2_0402_5% 2.2_0603_5% PR203 D D D D C VCC 26 PR150 @100K_0402_5% BSTM 9,17,29 VGATE PR149 0_0402_5% D1 0.22U_0603_16V7K CPU_VID5 23 PQ27 AO4408_SO8 2.2_0402_5% CPU_VID4 36 0.22U_0603_16V7K 30 V+ PC131 CPU_VID3 VDD D0 VCC 24 PR159 CPU_VID2 10 VCC 0.01U_0402_25V7Z CPU_VID1 PU12 PR134 0_0402_5% PR135 0_0402_5% PR137 0_0402_5% PR139 0_0402_5% PR141 0_0402_5% PR142 0_0402_5% PR144 0_0402_5% 2 PC128 2.2U_0603_6.3V6K PC130 PC129 1U_0603_16V6K CPU_VID0 PC123 4.7U_1206_25V6K 2 PD22 EP10QY03 PR133 10K_0402_1% PC122 4.7U_1206_25V6K PR132 10_0402_5% +3VS D FBM-L18-453215-900LMA90T_1812 PL15 2 PC145 0.47U_0603_16V7K PR167 909_0402_1% A A Compal Electronics, Inc Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size B Date: Document Number Rev 1B EDL71 LA-2351 Wednesday, March 02, 2005 Sheet 55 of 59 A B C D Version change list (P.I.R List) Item Fixed Issue E Page of Reason for change Rev PG# Modify List B.Ver# Phase 1.Change PR104 from 1K_0603_1% to 1.8K_0603_1% 1 Change DDRII to DDRI Ripple voltage of Change DDRII to DDRI 0.2 54 2.Change PR106 from 2K_0402_5% to 2.74K_0603_1% 0.2 DVT 0.2 DVT 0.2 DVT 3.Change PR101 from 107K_0402_1% to 93.1K_0603_1% +1.2VSP is large Ripple voltage of +VCCPP is large +1.5VP is poor supply by using CM3718 The output voltage is unstable, so increase capacitance to improve it 1.Change PC70 from 4.7U_1206_25V6K to 22U_1206_10V6M 0.2 54 Ripple voltage is over spec 0.2 55 Use MAX1845 to convert 0.2 56 Change PC106 from 150U_D2_6.3VM(45m) to 150U_D2_6.3VMV(15m) 1.Delete PU11 CM3718 +1.5VP 2.Delete PQ26 RHU002N06 3.Delete PL14 5U_TPRH6D38-5R0M 4.Delete PC113 150U_D_6.3V 5.Delete PC115 4.7U_1206_25V6K 6.Delete PC111,PC117PC121,PR123,PR125,PR127, PR129,PR130,PR131 2 1.Delete the PQ22 RHU002N06 2.Delete PR109 100K_0402_1% 3.Delete the PC91 0.01U_0402_25V7Z 0.2 +1.5VP is poor supply by using CM3718 Use MAX1845 to convert 55 +1.5VP 0.2 DVT 4.Change PR168 from 2K_0402_1% to 5.1K_0402_1% 5.Change PC103 from 150U_D2_6.3VM(45m) to 150U_D2_6.3VMV(15m) 6.Change PL9 from 1.8UH_D104C-919AS-1R8N to 4.7UH_D104C-919AS-4R7N 1.Change PR173 from 10K_0402_1% to 100K_0402_1% Change +2.5VSP to +1.8VP Change +2.5VSP to +1.8VP 0.2 56 0.2 DVT Add PR182 255K_0402_1% For UMA platform can no populate +1.2VSP For UMA platform can no populate +1.2VSP 0.2 54 For UMA platform can no populate +1.8VSP For UMA platform can no populate +1.8VSP 0.2 55 No populate PC71,PQ17,PR91,PR92,PC72,PR96,PC76,PC70,PR94, PR95,PC75,PQ19,PR97,PQ20,PR100 and PC82 0.2 DVT No populate PU13,PC146,PR171,PR172,PR173,PR182,PC151,PQ35, PL18,PC148,PR170,PR169,PC149 and PC147 0.2 DVT For charge current accuracy requirement For charge current accuracy requirement 0.2 50 Change PR43 from 120K_0402_5% to 120K_0402_1% 0.2 DVT 10 For charge voltage accuracy requirement For charge voltage accuracy requirement 0.2 50 Change PR46 from 49.9K_0402_1% to 49.9K_0603_0.1% 0.2 DVT 11 Use lower rating capacitors to improve cost down Use lower rating capacitors to improve cost down 0.2 50 1.Change PC42 from 4.7U_1206_25V6K to 4.7U_0805_6.3V6K 0.2 DVT 0.2 DVT 2.Change PC74 from 4.7U_1206_25V6K to 4.7U_0805_6.3V6K 3.Change PC94 from 4.7U_1206_25V6K to 4.7U_0805_6.3V6K 4.Change PC148 from 4.7U_1206_25V6K to 4.7U_1206_6.3V6K without populate 12 For pull high to VGATE For pull high to VGATE 0.2 50 Populate PR133 with 10K_0402_1% 13 14 To avoid inrush current To avoid inrush current 0.2 50 Add PR190 between PD14 pin2 and VS with 10_1206_5% 0.2 DVT To solve the no load PWM waveform issue To solve the no load PWM waveform issue 0.2 53 Change PC86 0.2 DVT 15 To solve the shutdown negtive voltage 0.2 54 Add PQ41(2N7002_SOT23) and PR196(33K_0402_1%) and 0.2 DVT To solve the shutdown negtive voltage issue issue from 220U_D2_4VM to 220U_D2_4V_15m PR197(11K_0402_1%) Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Size Document Number Rev 0.0 EDL71 LA-2351 Date: Wednesday, March 02, 2005 Sheet E 56 of 59 A B C D Version change list (P.I.R List) Item Fixed Issue E Page of Reason for change Rev PG# 0.2 54 0.2 Modify List B.Ver# Phase Change Max1845 to Max8743 and remove PD20 and PD21 0.2 DVT 52 Add Precharge circuit 0.2 DVT 0.2 55 Add PQ45 and PR199 and PR200 and PC165 0.2 DVT 0.3 52 Change PL6 from SH136100020 to SH13690AM00 0.3 PVT 0.3 49 Change its location from PD5 to PD2 0.3 PVT 0.3 52,55 0.3 PVT 1 16 17 To cost down To cost down To solve Max1902 can locked To solve Max1902 can locked as adapter plug in and uproot out the as adapter plug in and electric socket continuous uproot out the electric socket continuous 18 Power select action correct Power select action correct Increase choke rating of Increase choke rating of 5VALWP 19 5VALWP 20 BOM Error of PD2 PD2 shows wrong location PD5 on SAP system, I update it 21 BOM Error of PQ41 and PQ45 SAP system has quantity but shows no location of PQ41 and PQ45 Update the location of PQ41 and delete PQ45 2 22 EMI issue EMI's request 0.3 56 Change PR136 and PR159 from SD028000000 to SB028220B00 23 Production EOL SB906100109(TP0610T) will go EOL 0.3 50 Change SB906100109 to SB906100200 24 Time sequence error Time sequence is error such that B+ can't biuld 0.3 51,52 Change PR52 from SD034470200 to SD028150300 0.3 PVT 0.3 PVT 0.3 PVT Un-populate PC65 Change PR87 from SD028470200 to SD028000000 25 OTP setting adjust Change PR55 from SD034169200 to SD034205200 0.3 Because we change PR52 such that OTP needs to reset 26 PVT Add other circuit of Because we need to populate this circuit such that precharge can precharge enable 0.3 50 0.3 48 Change PR57 from SD014215108 to SD014182102 Add PD1 SC11N4148T8(S DIO 1N4148(SM)) 0.3 PVT Add PR10 SD0111501T6(S RES 1/4W 1.5K +-5% 1206) Add PR11 SD0111501T6(S RES 1/4W 1.5K +-5% 1206) 3 Add PR12 SD0111501T6(S RES 1/4W 1.5K +-5% 1206) Add PR13 SD0111501T6(S RES 1/4W 1.5K +-5% 1206) 27 Un-populate VGA_CORE_P Because EDL71 is Aviso GM plate form, we don't populate PQ45, PR199, 0.3 54 49 Delete PQ45, PR199, PR200, PC165 0.3 PVT 0.3 EVT Add PC146 for1.8VSP of EDL70 0.3 EVT Change PC147 from SG020151300 to SGA20221120 0.3 EVT 0.4 EVT PR200, PC165 28 Adjust CP point Because we need to change CP point to improve CP mode 0.4 29 Add PC146 for EDL70 We need to add PC146 such that Vin can more clear and stable 0.4 54 0.4 54 30 31 To cost down Precharge circuit tolerance To cost down Because the tolerance shuld be 1% but the metirial on BOM is 5% 0.4 54 Change PR35 from SD034226200 to SD034249200 Change PR52 from SD028150300 to SD034150300 adjust so we update it UUT has Zi Zi noice issue Because we have UUT zi zi noice issue, we add two capacitor to solve it 0.4 54 Add PC126 and PC127 with SF10004M008 54 EVT Noise on S3 mode Because we found noise on ceramic capacitor, we increase capacitance to 0.4 54 Change PC43 from SE142475K00 to SE142106M00 54 EVT 32 4 33 decrease this noise Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Size Document Number Rev 0.0 EDL71 LA-2351 Date: Wednesday, March 02, 2005 Sheet E 57 of 59 A B C D Version change list (P.I.R List) Item Fixed Issue E Page of Reason for change Rev PG# Modify List B.Ver# Phase Because the power consumption is too high as S3 mode, we found PU8 Make PU8 can into skip mode as S3 mode 0.4 52 change PU8 from SGA20221150 to SGA20331D20 0.4 EVT Because we found the start up waveform which has some delay such that Make 1.2VSP start up waveform more smooth the waveform does'nt smooth We improve it 0.5 52 Change PC75 from SE074222K00 to SE075472K00 0.4 PVT Because we found the start up waveform which has some delay such that Make 1.8VSP start up waveform more smooth the waveform does'nt smooth We improve it 0.5 54 Change PC151 from SE026223K00 to SE026103K00 0.4 PVT 0.4 PVT 0.4 PVT 0.5 Pre-MP 0.5 Pre-MP 0.5 Pre-MP doesn't into skip mode, we now improve it To improve noise issue when system Because we found that noise occurs when system into S3 mode, into S3 mode so we need to improve and derease it 0.5 51 To meet EMI request 0.5 55 Change PC43 from SE142106M00 to SE065106K00 To meet EMI request Add PR203 and PR204 with SD0130000T4 Change PR115 from SD028200000(S RES 1/16W 200 +-5% 0402) to For EDL72, Transfer ISPD BOM Error BOM error, update to correct value 0.6 53 SD028000000(S RES 1/16W +- 5% 0402) Change PR115 from SD028200000(S RES 1/16W 200 +-5% 0402) to For EDL72, Transfer ISPD BOM Error BOM error, update to correct value 0.6 53 SD028000000(S RES 1/16W +- 5% 0402) Change PC126 from SF06804M000(S ELE CAP 68U 25V M B(6.3*6.0) For EDL72, Transfer ISPD BOM Error 0.6 BOM error, update to correct value 55 CV-GX) to SE10004M008(S ELE CAP 100U 25V M B(6.3*7.7) CV-GX) 2 Change PC127 from SF06804M000(S ELE CAP 68U 25V M B(6.3*6.0) For EDL72, Transfer ISPD BOM Error 0.6 BOM error, update to correct value 55 0.5 Pre-MP 0.5 Pre-MP 0.5 Pre-MP 0.5 Pre-MP 0.5 Pre-MP CV-GX) to SE10004M008(S ELE CAP 100U 25V M B(6.3*7.7) CV-GX) Change PC124 from SE075103K00(S CER CAP 0.01U 25V K X7R) to For EDL70_72, change AL to AP material Change AL material to AP material 0.6 55 SE075103Z00(S CER CAP 0.01U 25V K X7R 0402) Change PC143 from SE075103K00(S CER CAP 0.01U 25V K X7R) to For EDL70_72, change AL to AP material Change AL material to AP material 0.6 55 SE075103Z00(S CER CAP 0.01U 25V K X7R 0402) Change PC66 from SE135105K00(S CER CAP 1U 16V +-10% X5R 0603) For EDL72, change AL to AP material Change AL material to AP material 0.6 52 to SE135105KT0(S CER CAP 1U 16V K X5R 0603 TAIYO) 3 4 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Size Document Number Rev 0.0 EDL71 LA-2351 Date: Wednesday, March 02, 2005 Sheet E 58 of 59 A B C D Version change list (P.I.R List) Item Fixed Issue Page of Reason for change Rev PG# Modify List B.Ver# Phase S4 auto resume Can't auto resume from S4 0.4 30 Change VCCSUS3_3 from +3V to +3VALW 0.5 PVT C615 short C615 short to logic low cause can't boot 0.4 35 Change C613 and C615 to SGN01220100 0.5 PVT speaker generate "bo" niose when system shut down 0.4 45 Change R460 to R461 0.5 PVT bo niose when shut down C904 too close to JP12 C904 too close to JP12 if C904 fail can't repair 0.4 40 JP12 change to DC233104020 0.5 PVT +1.5V rising edge +1.5V ‘s rising edge is not smooth 0.4 30 Add R12 0.5 PVT SW DJ can't play with Hitach HDD Hitachi HDD send IDE_DIOR# in SW DJ S0 mode 0.4 31,46 Add Q97, R1197, R1198 0.5 PVT Modem noise Modem dial tone have noise 0.4 39 Change R518, R521 from SD0130000T4 to SM010012000 0.5 PVT Add D32,D33 0.6 PVT 3 E KB910 damage issue KB910 INVT_PWM pin damage issue 0.5 41 S4 auto resume Can't auto resume from S4 0.5 29,30 Change +3V to +3VALW for SMBUS and LINKALERT#, EC_SMI#, SYS_RESET# PM_BATLOW#, GPI11, ICH_PCIE_WAKE# 1.5V LDO 0.6 PVT 10 Bo noise Bo noise gernerate in SWDJ mode and power up 0.5 45 Del R460 and R461, add D35 and D36 0.6 PVT 11 Backlight issue backlight timing error 0.5 24 Add D34 and R1118 0.6 PVT 12 Sighting Alert Alviso SMVREF Sighting Alert (# 68363) 0.5 No stuff R100 and R101 0.6 PVT 13 CRT ISSUE CRT NOISE issue 12 Change C119 from SE053106Z00 to SE077226M10 0.6 PVT 14 SWDJ issue SWDJ can't play 0.5 46 Add Q98 0.6 PVT 15 USB OC Add USB OC delay circuit 0.5 40 Add R1201,R1202,R1203,R1204,R1205, R1206,C1134,C1135,C1136 0.6 PVT 16 SVIDEO ISSUE SVIDEO out noise issue 0.5 12 Change C92 from SE107475M00 to SE077226M10 0.6 PVT 17 TV TUNNER No sound in IOMP mode 0.5 38 ADD TV_AUDIO_R and TV_AUDIO_L 0.6 PVT 18 Power sequence Power sequence 0.5 47 Add C172 for EDL70 power sequence 0.6 PVT 19 LCD Power sequence for EDL70/72 Power off white screen issue 1.0 24 Add 1@ on R1118 and D34 1.1 PVT 20 ESD Add ESD diode for USB data and EC INVT_PWM pin Add U70, D38, D39 and D40 1.1 PVT 0.5 4 1.0 40, 41 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Size Document Number Rev 0.0 EDL71 LA-2351 Date: Wednesday, March 02, 2005 Sheet E 59 of 59 ... 35 LAN_MIDI1+ LAN_MIDI1- LAN_MDI1+ LAN_MDI1- 35 35 LAN_MIDI2+ LAN_MIDI2- LAN_MDI2+ LAN_MDI2- TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 RJ45_MDI2+ RJ45_MDI2- 35 35 LAN_MIDI3+ LAN_MIDI3- LAN_MDI3+ LAN_MDI3-... LAN_EECLK LAN_EEDI LAN_EEDO D R528 0_1206_5% LAN_MIDI0+ LAN_MIDI0LAN_MIDI1+ LAN_MIDI1- GIGA@ +3VALW EN_WOL# = Low, System can wake on LAN ( keep Low when Power On) ACTIVITY# LAN_LINK100# LAN_LINK10#... +3V_LAN unpop when use 8100C(L) NC/VSS NC/VSS LAN_MIDI2+ LAN_MIDI2LAN_MIDI3+ LAN_MIDI3- VGS(th) = -0.45V IDmax = 2.3A +3V_LAN U32 36 36 36 36 GIGA@ 0_0402_5% R535 11 123 124 +3V_LAN LAN_EECS LAN_EECLK