ACER 7736 GM45 JV71 MV DDR3

5 D JV71-MV DDR3 Madison Block SMSC Mobile CPU Diagram CLK GEN Penryn 1066 MHz 3D3V_AUX_S5 L1 GND L2 TPS51124 S L3 INPUTS S L4 SYSTEM DC/DC 34 VRAM 64MbX16X8 1024M 667/800/1066MHz@1.05V GND L5 BOTTOM L6 PCIex16 1D5V_S3(12A) RT9026 44 DDR_VREF_S3 (1.2A) 20 RT9018 LCD 1D5V_S3 CRT TPS51117 44 1D1V_S0(2A) 18 LVDS, CRT I/F 6,7,8,9,10,11 X4 DMI 400MHz OUTPUTS HDMI VGA Madison / M96 52~57 INTEGRATED GRAHPICS 16,17 D 43 1D05V_S0(9A) 1D5V_S3 DDR Memory I/F 1066 MHz 5V_AUX_S5 TOP DCBATOUT AGTL+ CPU I/F DDR3 OUTPUTS 3D3V_S5(7A) Cantiga 16,17 INPUTS PCB STACKUP 4, DDR3 42 ISL62392 5V_S5(6A) HOST BUS SYSTEM DC/DC DCBATOUT EMC2102 ICS9LPRS365B Project code: 91.4FX01.001 PCB P/N : 48.4FX01.01M REVISION : 09924 -1 19 C-Link0 RTS5159 45 FBVDD(4A) CHARGER MS/MS Pro/xD /MMC/SD CardBus USB DCBATOUT ISL88731A 31 47 INPUTS OUTPUTS DCBATOUT BT+ C C ICH9M PCIe ports LINE IN LAN PCI/PCI BRIDGE TXFM Giga LAN ACPI 2.0 29 BCM5784 SATA CPU DC/DC RJ45 26 25 ISL6266A 26 12 USB 2.0/1.1 ports High Definition Audio AZALIA Codec Serial Peripheral I/F ALC888S 27 RT8202A PCIe Mini Card Wire LAN 33 OP AMP DCBATOUT VGA_CORE 13A ISL6263A 30 LPC BUS LINE OUT SATA 29 RJ11 OUTPUTS GFXCORE MAX9789A MODEM MDC Card 47 INPUTS 12,13,14,15 INT.SPKR 29 VCC_CORE 38A VGA_CORE Matrix Storage Technology(DO) Active Managemnet Technology(DO) 29 1.5W DCBATOUT LPC I/F MIC In B OUTPUTS ETHERNET (10/100/1000MbE) Int MIC 18 41 INPUTS HDD SATA USB Mini USB Blue Tooth 21 SATA 30 ODD SATA 22 23 SPI BIOS KBC Winbond Camera (2MB) 36 WPCE773 35 Finger Printer 37 USB Port 24 Touch Pad 37 46 INPUTS OUTPUTS DCBATOUT VCC_GFXCORE (7A) LPC B DEBUG CONN.36 MEDIA KEY 38 INT KB 35 A A JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title BLOCK DIAGRAM Size A2 Date: Document Number Rev JV71-MV DDR3 Madison Wednesday, October 28, 2009 Sheet of -1 62 A B ICH9M Functional Strap Definitions ICH9 EDS 642879 Rev.1.5 ICH9M Integrated Pull-up and Pull-down Resistors Usage/When Sampled HDA_SDOUT XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) This signal has weak internal pull-down CL_CLK[1:0] PULL-UP 20K CL_DATA[1:0] PULL-UP 20K HDA_SYNC PCIE config1 bit0, Rising Edge of PWROK This signal has a weak internal pull-down Sets bit0 of RPC.PC(Config Registers:Offset 224h) CL_RST0# PULL-UP 20K GNT2#/ GPIO53 PCIE config2 bit2, Rising Edge of PWROK DPRSLPVR/GPIO16 PULL-DOWN 20K ENERGY_DETECT PULL-UP 20K GPIO20 Reserved This signal has a weak internal pull-up Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high HDA_BIT_CLK PULL-DOWN 20K GNT1#/ GPIO51 ESI Strap (Server Only) Rising Edge of PWROK HDA_DOCK_EN#/GPIO33 PULL-UP 20K HDA_RST# PULL-DOWN 20K HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI GPIO49 SATALED# SPKR page 92 D Signal GNT3#/ GPIO55 C Top-Block Swap Override Rising Edge of PWROK Comment ESI compatible mode is for server platforms only This signal should not be pulled low for desttop and mobile Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space) Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down ICH9 EDS 642879 SIGNAL GLAN_DOCK# GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K GPIO[20] PULL-DOWN 20K Integrated TPM Enable, Rising Edge of CLPWROK Sample low: the Integrated TPM will be disabled Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable GPIO[49] PULL-UP 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LAN_RXD[2:0] PULL-UP 20K LDRQ[0] PULL-UP 20K LDRQ[1]/GPIO23 PULL-UP 20K PME# PULL-UP 20K PWRBTN# PULL-UP 20K PCI Express Lane Reversal Rising Edge of PWROK Signal has weak internal pull-up Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) SATALED# PULL-UP 15K No Reboot Rising Edge of PWROK If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature) The status is readable via the NO REBOOT bit SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K SPI_MOSI PULL-DOWN 20K SPI_MISO PULL-UP 20K SPKR PULL-DOWN 20K TACH_[3:0] PULL-UP 20K XOR Chain Entrance Rising Edge of PWROK This signal should not be pull low unless using XOR Chain testing GPIO33/ HDA_DOCK _EN# Flash Descriptor Security Override Strap Rising Edge of PWROK Sampled low:the Flash Descriptor Security will be overridden If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister Pin Name CFG[2:0] CFG[4:3] CFG8 CFG[15:14] CFG[18:17] TP[3] PULL-UP 20K USB[11:0][P,N] PULL-DOWN 15K 0.5 Configuration Strap Description FSB Frequency Select 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved Reserved CFG5 DMI x2 Select CFG6 iTPM Host Interface = DMI x2 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) = Transport Layer Security (TLS) cipher suite with no confidentiality = TLS cipher suite with confidentiality (default) CFG7 Intel Management engine Crypto strap CFG9 PCIE Graphics Lane = Reverse Lanes,15->0,14->1 ect 1= Normal operation(Default):Lane Numbered in order CFG10 PCIE Loopback enable = Enable (Note 3) 1= Disabled (default) PULL-DOWN 20K Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10) GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC TP3 page 218 The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller Boot BIOS Destination Selection 0:1 Rising Edge of PWROK DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK applications and required to be high for mobile applications Montevina Platform Design guide 22339 Rev.1.5 Resistor Type/Value HDA_SYNC E Cantiga chipset and ICH9M I/O controller Hub strapping configuration CFG[13:12] CFG16 CFG19 00 10 01 11 XOR/ALL = = = = Reserve XOR mode Enabled ALLZ mode Enabled (Note 3) Disabled (default) FSB Dynamic ODT = Dynamic ODT Disabled = Dynamic ODT Enabled (Default) DMI Lane Reversal = Normal operation(Default): Lane Numbered in Order = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) CFG20 Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe = Only Digital Display Port or PCIE is operational (Default) =Digital display Port and PCIe are operting simulataneously via the PEG port =No SDVO Card Present (Default) SDVO_CTRLDATA SDVO Present = SDVO Card Present = LFP Disabled (Default) L_DDC_DATA Local Flat Panel (LFP) Present 1= LFP Card Present; PCIE disabled NOTE: All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware This 'Soft-Strap' is activated only after enabling iTPM via CFG6 Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Reference Size A3 Date: Document Number Rev -1 JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet of 62 A B C D E 3D3V_S0 3D3V_S0 1D05V_S0 C418 DY 2 1 2 1 2 2 1 2 1 2 C454 SCD1U16V2ZY-2GP C448 SCD1U16V2ZY-2GP 3D3V_S0 C445 SCD1U16V2ZY-2GP C419 DY SCD1U16V2ZY-2GP C430 SCD1U16V2ZY-2GP C416 SC4D7U6D3V3KX-GP C436 SCD1U16V2ZY-2GP C444 SCD1U16V2ZY-2GP DY C435 SCD1U16V2ZY-2GP C417 SCD1U16V2ZY-2GP C450 DY SC4D7U6D3V3KX-GP DY SCD1U16V2ZY-2GP SC1U16V3ZY-GP SC4D7U6D3V3KX-GP C457 C455 SCD1U16V2ZY-2GP C456 3D3V_VDD48_S0 1 R554 0R0603-PAD 1D05V_S0 3D3V_VDD48_S0 82.30005.891 2nd = 82.30005.951 UMA C452 R254 10KR2J-3-GP PCLKCLK2 CPU_SEL2_R 61 60 CLK_CPU_BCLK CLK_CPU_BCLK# CPU CPUT1_F CPUC1_F 58 57 CLK_MCH_BCLK CLK_MCH_BCLK# NB CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 54 53 CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13 SB DMI 16 46 62 23 45 44 PCI_STOP# CPU_STOP# SRCT7/CR#_F SRCC7/CR#_E 51 50 SRCT6 SRCC6 48 47 CLK_PCIE_PEG 52 CLK_PCIE_PEG# 52 GPU SRCT10 SRCC10 41 42 CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25 LAN SRCT11/CR#_H SRCC11/CR#_G 40 39 SRCT9 SRCC9 37 38 CLK_PCIE_MINI1 32 CLK_PCIE_MINI1# 32 WLAN SRCT4 SRCC4 34 35 CLK_MCH_3GPLL CLK_MCH_3GPLL# NB CLK SRCT3/CR#_C SRCC3/CR#_D 31 32 SRCT2/SATAT SRCC2/SATAC 28 29 CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12 JTAG_TCK 53 SB SATA DREFSSCLK DREFSSCLK# NB DREFCLK DREFCLK# NB modify by RF PCLKCLK5 15,16,17 SMBC_ICH 15,16,17 SMBD_ICH 13 CLK_PW RGD 63 CK_PWRGD/PD# 10 11 12 13 14 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN 3D3V_S0 C451 CPU_SEL2_R CLK48 PCLKCLK4 PCLKCLK5 DY 10KR2J-3-GP 2R249 SC47P50V2JN-3GP 35 PCLK_FW H SRN33J-7-GP SCLK SDATA PCLKCLK0 PCLKCLK1 R255 33R2J-2-GP PCLKCLK2 1PCLKCLK3 TPAD14-GP TP158 PCLKCLK4 PCLKCLK5 DY 4,7 CPU_SEL1 CPU_SEL2_R FSLB/TEST_MODE REF0/FSLC/TEST_SEL 55 NC#55 GND48 GNDPCI GNDREF DY SC33P50V2JN-3GP DY SC33P50V2JN-3GP 64 DY SC33P50V2JN-3GP DY CR#_H CR#_G R694 ATI-ES 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 24 25 DREFSSCLK_1 DREFSSCLK_1# 2 0R2J-2-GP RN76 SRN0J-6-GP SRCT0/DOTT_96 SRCC0/DOTC_96 20 21 DREFCLK_1 DREFCLK_1# RN44 SRN0J-6-GP UMA UMA 3D3V_S0 ICS9LPRS365BKLFT-GP-U 71.09365.A03 EMI capacitor for Antenna team suggestion 2nd = 71.09365.A03 71.08513.003 RN47 SRN10KJ-6-GP DY ICS9LPRS365YGLFT setting table PIN NAME DESCRIPTION RN45 13 25 32 Byte 5, bit = PCI0 enabled (default) 1= CR#_A enabled Byte 5, bit controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair PCI1/CR#_B Byte 5, bit = PCI1 enabled (default) 1= CR#_B enabled Byte 5, bit controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair PCI2/TME = Overclocking of CPU and SRC Allowed = Overclocking of CPU and SRC NOT allowed PCI3 PCI4/27M_SEL = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# PCI_F5/ITP_EN =SRC8/SRC8# = ITP/ITP# SRCT3/CR#_C Byte 5, bit = SRC3 enabled (default) 1= CR#_C enabled Byte 5, bit controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair SATACLKREQ# CLK_MCH_OE# LAN_CLKREQ# W LAN_CLKREQ# PCLKCLK0 PCLKCLK1 CR#_H CR#_G SEL2 SEL1 SEL0 FSC FSB FSA DY B CPU FSB 100M 133M 166M 200M 266M X 533M 667M 800M 1067M SRN470J-3-GP PIN NAME DESCRIPTION SRCC3/CR#_D Byte 5, bit = SRC3 enabled (default) 1= CR#_D enabled Byte 5, bit controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair SRCC7/CR#_E Byte 6, bit = SRC7# enabled (default) 1= CR#_F controls SRC6 SRCT7/CR#_F Byte 6, bit = SRC7 enabled (default) 1= CR#_F controls SRC8 SRCC11/CR#_G Byte 6, bit = SRC11# enabled (default) 1= CR#_G controls SRC9 SRCT11/CR#_H Byte 6, bit = SRC11 enabled (default) 1= CR#_H controls SRC10 0 0 C 0 1 1 0 JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Clock Generator Size Date: A SB 1008 SC33P50V2JN-3GP DY SC33P50V2JN-3GP DY SC33P50V2JN-3GP PCI0/CR#_A NEWCARD 18 15 CLK48_5158E EC46 CLK_ICH14 EC25 PCLK_FW H EC24 PCLK_ICH EC23 PCLK_KBC EC39 CLK48_ICH EC48 USB_48MHZ/FSLA GND CLK_ICH14 CLK48_ICH 34 PCLK_KBC 13 PCLK_ICH 17 65 RN46 13 2K2R2J-2-GP CLK48 33R2J-2-GP 13 PM_STPPCI# 13 PM_STPCPU# SRN10KJ-6-GP 13 R2512 R253 RN48 CPU_SEL2 CLK48_5158E GND GNDSRC GNDSRC GNDSRC GNDCPU GND 4,7 CPU_SEL0 CLK48_5158E CPUT0 CPUC0 X1 X2 SC27P50V2JN-2-GP 4,7 31 3 GEN_XTAL_IN VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO PCLKCLK4 GEN_XTAL_OUT X5 X-14D31818M-35GP 22 30 36 49 59 26 DIS 3D3V_S0 U24 C453 SC33P50V2JN-3GP VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3 CL=20pF±0.2pF R260 10KR2J-3-GP 19 27 43 52 33 56 3D3V_S0 D Document Number Rev JV71-MV DDR3Sheet Madison W ednesday, October 28, 2009 of E -1 62 A C D E H_A#[35 3] H_A#[35 3] H_DINV#[3 0] TPAD14-GP TP97 RSVD_CPU_11 B1 RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 G6 E4 BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#1 H_TRDY# H_HIT# H_HITM# 6 TP28 TP27 TP26 TP32 TP29 TP30 TP34 TP50 TP31 TP49 TP33 TP88 PROCHOT# THRMDA THRMDC THERMTRIP# HCLK BCLK0 BCLK1 CPU1B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_THERMDA TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP H_THERMDC 1D05V_S0 C116 SC2200P50V2KX-2GP DY Close to CPU R89 68R2-GP H_DSTBN#0 H_DSTBP#0 H_DINV#0 R97 2DY 0R2J-2-GP C90 CPU_PROCHOT#_R PM_THRMTRIP-A# 7,12,38 A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# 40 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 SC47P50V2JN-3GP modify by RF DY C7 PM_THRMTRIP# ICH9 and MCH PH @ page48 should connect to without T-ing 1D05V_S0 Layout Note: "CPU_GTLREF0" 0.5" max length KEY_NC 62.10079.001 2nd = 62.10053.401 6 1KR2F-3-GP R312 H_DSTBN#1 H_DSTBP#1 H_DINV#1 CPU_GTLREF0 DY R309 2KR2F-3-GP H_CPURST# EC75 OF SC33P50V2JN-3GP DY C526TPAD14-GP TP87 TPAD14-GP TP25 TPAD14-GP TP180 3,7 3,7 3,7 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# AD26 TEST1 C23 TEST2 D25 RSVD_CPU_12 C24 TEST4 AF26 1RSVD_CPU_13 AF1 1RSVD_CPU_14 A26 B22 B23 C21 CPU_SEL0 CPU_SEL1 CPU_SEL2 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 MISC BSEL0 BSEL1 BSEL2 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R71 R67 R57 R60 27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP 2 2 H_PW RGD 12,50 H_CPUSLP# H_PSI# 40 XDP_TMS R54 54D9R2F-L1-GP XDP_TDI R55 54D9R2F-L1-GP XDP_BPM#5 R46 54D9R2F-L1-GP XDP_TDO R47 H_CPURST# R113 1 DY R119 TEST1 1KR2J-1-GP DY TEST2 R114 1KR2J-1-GP C525 2DY TEST4 SCD1U10V2KX-4GP Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals Layout Note: Comp0, connect with Zo=27.4 ohm, make trace length shorter than 0.5" Comp1, connect with Zo=55 ohm, make trace length shorter than 0.5" 54D9R2F-L1-GP DY 51R2F-2-GP DY 3D3V_S0 XDP_DBRESET# R105 H_DPRSTP# H_DPSLP# H_DPW R# H_PW RGD H_CPUSLP# H_INIT# H_CPURST# 1KR2J-1-GP DY XDP_TCK R32 54D9R2F-L1-GP XDP_TRST# R33 54D9R2F-L1-GP 1 1 1 TP76 TP95 TP114 TP81 TP78 TP92 TP86 TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP Place these TP on button-side, easy to measure JV71-MV DDR3 Madison 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (1 of 2) Date: C D Wistron Corporation Size All place within 2" to CPU B SC100P50V2JN-3GP C102 DY 1D05V_S0 H_DPRSTP# 7,12,40 H_DPSLP# 12 H_DPW R# BGA479-SKT6-GPU7 EMI capacitor A modify by RF H_THERMDA 33 H_THERMDC 33 BGA479-SKT6-GPU7 H_D#[63 0] DY CPU_PROCHOT#_1 D21 A24 B25 DATA GRP2 HIT# HITM# H_LOCK# H_CPURST# 6,50 H_RS#[2 0] H_RS#0 H_RS#1 H_RS#2 H_DSTBP#[3 0] SC47P50V2JN-3GP DATA GRP3 C1 F3 F4 G3 G2 C104 1 RESET# RS0# RS1# RS2# TRDY# 12 H4 H_INIT# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 LOCK# H_BREQ#0 H_IERR# SC1KP50V2KX-1GP STPCLK# LINT0 LINT1 SMI# D20 B3 1 12 12 12 12 F1 H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 BR0# IERR# INIT# H_DSTBN#[3 0] R88 56R2J-4-GP A20M# FERR# IGNNE# DEFER# DRDY# DBSY# H_D#[63 0] Place testpoint on H_IERR# with a GND 0.1" away THERMAL ICH 12 12 12 H_DEFER# H_DRDY# H_DBSY# H_DSTBP#[3 0] 1D05V_S0 H_A20M# H_FERR# H_IGNNE# A6 A5 C4 A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# H5 F21 E1 6 DATA GRP1 H_ADSTB#1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 REQ0# REQ1# REQ2# REQ3# REQ4# ADDR GROUP H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_BNR# H_BPRI# K3 H2 K2 J3 L1 H1 E2 G5 DATA GRP0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 H_REQ#[4 0] A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# RESERVED 6 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 H_DINV#[3 0] H_DSTBN#[3 0] TP74 TPAD14-GP ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 OF CONTROL CPU1A B Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet E of -1 62 A B C 2 2 2 2 2 2 C537 SC10U6D3V5MX-3GP C536 SC10U6D3V5MX-3GP DY C547 SC10U6D3V5MX-3GP C548 SC10U6D3V5MX-3GP C539 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C552 DY 1 2 C57 DY C83 C84 C80 C79 1 C58 2 C75 SCD1U50V3KX-GP GAP-CLOSE-PW R C67 SC4D7U6D3V3KX-GP 1D05V_S0 1D05V_S0 1D05V_S0_CPU layout note: "1D5V_VCCA_S0" as short as possible 1D5V_S0 100R2F-L1-GP-U VCC_SENSE 40 VSS_SENSE 40 R25 C603 FCM1608KF-1-GP L18 68.00217.161 C6062nd = 68.00248.061 SC10U6D3V5MX-3GP 40 H_VID[6 0] VCC_CORE SCD01U16V2KX-3GP 1D5V_VCCA_S0 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 Layout Note: R24 VCCSENSE and VSSSENSE lines should be of equal length 100R2F-L1-GP-U BGA479-SKT6-GPU7 CPU1D DY TPAD14-GP TP23 SCD1U10V2KX-4GP AE7 SC10U6D3V5MX-3GP VSSSENSE C538 DY SCD1U10V2KX-4GP AF7 C553 SC10U6D3V5MX-3GP VCCSENSE DY SCD1U10V2KX-4GP AD6 AF5 AE5 AF4 AE3 AF3 AE2 C52 SC10U6D3V5MX-3GP VID0 VID1 VID2 VID3 VID4 VID5 VID6 DY SCD1U10V2KX-4GP B26 C26 C51 SC10U6D3V5MX-3GP VCCA VCCA SC10U6D3V5MX-3GP G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 C50 DY G2 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP C53 SC10U6D3V5MX-3GP C88 SC10U6D3V5MX-3GP C89 SC10U6D3V5MX-3GP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SCD1U10V2KX-4GP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 C87 SC10U6D3V5MX-3GP OF SCD1U10V2KX-4GP C55 SCD1U10V2KX-4GP C85 SCD1U10V2KX-4GP CPU1C C56 SCD1U10V2KX-4GP SCD1U10V2KX-4GP VCC_CORE A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 C86 VCC_CORE E VCC_CORE VCC_CORE D Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line A4 A8 A11 A14 A16 A19 A23 TP_AF2_CPU AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 OF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 TP_AE26_CPU TP_A2_CPU A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 TP_A25_CPU AF25 TP174 TPAD14-GP TP98 TPAD14-GP TP181 TPAD14-GP BGA479-SKT6-GPU7 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (2 of 2) Size Date: A B C D Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet E of -1 62 1 OF 10 NB1A H_A#[35 3] H_D#[63 0] H_D#[63 0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 1D05V_S0 H_SWING routing Trace width and Spacing use 10 / 20 mil D R381 221R2F-2-GP H_SWING Resistors and Capacitors close MCH 500 mil ( MAX ) R382 100R2F-L1-GP-U 2 C619 SCD1U10V2KX-4GP H_SW ING C H_RCOMP routing Trace width and Spacing use 10 / 20 mil R380 H_RCOMP 24D9R2F-L-GP Place them near to the chip ( < 0.5") B H_CPURST# EC76 F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 SC33P50V2JN-3GP H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 HOST 1D05V_S0 H_SW ING H_RCOMP R370 1KR2F-3-GP 4,50 H_CPURST# H_CPUSLP# H_AVREF C614 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 J8 L3 Y13 Y1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 L10 M7 AA5 AE6 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_SWING H_RCOMP H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_CPURST# H_CPUSLP# H_RS#_0 H_RS#_1 H_RS#_2 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 H_AVREF H_DVREF H_A#[35 3] D H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPW R# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DSTBN#[3 0] H_DSTBP#[3 0] C H_DINV#[3 0] H_DSTBN#[3 0] H_DSTBP#[3 0] H_REQ#[4 0] H_RS#[2 0] B 4 CANTIGA-GM-GP-U-NF 71.CNTIG.00U 2 C12 E11 A11 B11 SCD1U16V2ZY-2GP R389 2KR2F-3-GP C5 E3 A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H_DINV#[3 0] DY EMI capacitor H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 JV71-MV DDR3 Madison A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Date: Document Number Cantiga (1 of 6) JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet Rev -1 of 62 1D05V_S0 OF 10 NB1B RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# CLK DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 16 16 17 17 BC28 AY28 AY36 BB36 M_CKE0 M_CKE1 M_CKE2 M_CKE3 16 16 17 17 BA17 AY16 AV16 AR13 M_CS0# M_CS1# M_CS2# M_CS3# 16 16 17 17 BD17 AY17 BF15 AY13 M_ODT0 M_ODT1 M_ODT2 M_ODT3 16 16 17 17 L_BKLTCTL GMCH_BL_ON 18 CLK_DDC_EDID 18 DAT_DDC_EDID LCTLA_CLK L32 G32 M32 LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID M33 K33 J33 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK GMCH_LCDVDD_ON M29 LIBG C44 L_LVBG B43 LVDS_VREF E37 E38 C41 GMCH_TXACLKC40 GMCH_TXACLK+ B37 GMCH_TXBCLKA37 GMCH_TXBCLK+ 18 GMCH_LCDVDD_ON 18 18 18 18 SM_PWROK 38 BG22 BH21 M_RCOMPP M_RCOMPN BF28 BH28 SM_RCOMP_VOH SM_RCOMP_VOL AV42 AR36 BF17 BC36 DDR2 : connect to GND SM_REXT R4441 499R2F-2-GP DDR3_DRAMRST# DDR3_DRAMRST# DDR_VREF_S3_1 0.75V B38 A38 E41 F41 16,17 DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# F43 E43 L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK TPAD14-GP TP189 R183 0R0402-PAD CLK_MCH_3GPLL CLK_MCH_3GPLL# C335 3 18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2- H47 E46 G40 A40 18 GMCH_TXAOUT0+ 18 GMCH_TXAOUT1+ 18 GMCH_TXAOUT2+ H48 D45 F40 B40 18 GMCH_TXBOUT018 GMCH_TXBOUT118 GMCH_TXBOUT2- A41 H38 G37 J37 18 GMCH_TXBOUT0+ 18 GMCH_TXBOUT1+ 18 GMCH_TXBOUT2+ B42 G38 F37 K37 TV_DACA TV_DACB TV_DACC LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 F25 H25 K25 TVA_DAC TVB_DAC TVC_DAC H24 M_RCOMPN CFG20 R556 DY 2K21R2F-GP CFG9 DY 2K21R2F-GP CFG16 R442 80D6R2F-L-GP PWROK 100R2J-2-GP R203 R192 0R0402-PAD 13,40 PM_DPRSLPVR R195 0R0402-PAD B PWROK EC77 PM_DPRSLPVR_MCH SC33P50V2JN-3GP DY EMI capacitor DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AD35 AE44 AF46 AH43 19 13 13 13 13 GMCH_BLUE 19 GMCH_GREEN 19 DMI_RXP0 13 DMI_RXP1 13 DMI_RXP2 13 DMI_RXP3 13 GFX_VR_EN C34 G28 GMCH_RED GMCH_RED GMCH_DDCCLK GMCH_DDCDATA R189 GMCH_HS 0R0402-PAD R188 2GMCH_VS 0R0402-PAD 19 GMCH_DDCCLK 19 GMCH_DDCDATA 19 GMCH_HSYNC 19 GMCH_VSYNC B33 B32 G33 F33 E33 E28 GMCH_GREEN CRT_BLUE 45 CRT_RED CRT_IRTN H32 J32 J29 E29 L29 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC CRT_IREF UMA R161 1K02R2F-1-GP GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF TSATN# B12 B28 B30 B29 C29 A28 CRT_IREF routing Trace width use 20 mil R201 1KR2F-3-GP CL_CLK0 13 CL_DATA0 13 PWROK 13,33 CL_RST#0 13 MCH_CLVREF C288 GMCH_HDMI_CLK 20 GMCH_HDMI_DATA 20 CLK_MCH_OE# MCH_ICH_SYNC# 13 MCH_TSATN# HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PEG_TXN0_L PEG_TXN1_L PEG_TXN2_L PEG_TXN3_L PEG_TXN4_L PEG_TXN5_L PEG_TXN6_L PEG_TXN7_L PEG_TXN8_L PEG_TXN9_L PEG_TXN10_L PEG_TXN11_L PEG_TXN12_L PEG_TXN13_L PEG_TXN14_L PEG_TXN15_L DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 C220 C648 C654 C228 C233 C658 C237 C239 C265 C264 C269 C660 C671 C666 C680 C679 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PEG_TXP0_L PEG_TXP1_L PEG_TXP2_L PEG_TXP3_L PEG_TXP4_L PEG_TXP5_L PEG_TXP6_L PEG_TXP7_L PEG_TXP8_L PEG_TXP9_L PEG_TXP10_L PEG_TXP11_L PEG_TXP12_L PEG_TXP13_L PEG_TXP14_L PEG_TXP15_L DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 C213 C647 C651 C222 C229 C663 C234 C245 C259 C253 C266 C657 C667 C664 C672 C686 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 UMA UMA C600 C605 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN0_L_1 PEG_TXP0_L_1 UMA PEG_TXN1_L PEG_TXP1_L UMA UMA C596 C598 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN1_L_1 PEG_TXP1_L_1 UMA PEG_TXN2_L PEG_TXP2_L UMA UMA C589 C592 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN2_L_1 PEG_TXP2_L_1 UMA R200 499R2F-2-GP PEG_TXN3_L PEG_TXP3_L UMA UMA C568 C561 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN3_L_1 PEG_TXP3_L_1 UMA FOR Cantiga:500 ohm Teenah: 392 ohm R555 PEG_RXP3 2UMA HDMI_DETECT#_L UMA ACZ_SDIN3 ACZ_SDIN3 ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R ACZ_BIT_CLK 12 ACZ_SYNC_R 12 ACZ_RST#_R 12 ACZ_SDATAOUT_R GMCH_RED GMCH_GREEN GMCH_BLUE 12 1 1KR2F-3-GP EC79 SCD01U16V2KX-3GP 2 C756 SC2D2U6D3V3MX-1-GP ACZ_RST#_R SC12P50V2JN-3GP HDA_BCLK SC12P50V2JN-3GP DY DY ACZ_BIT_CLK SC12P50V2JN-3GP C757 1 PM_EXTTS#0 PM_EXTTS#1 SRN10KJ-5-GP RN35 C RN82 SRN0J-10-GP-U HDMI_DATA2- 20,53 HDMI_DATA2+ 20,53 RN83 SRN0J-10-GP-U HDMI_DATA1- 20,53 HDMI_DATA1+ 20,53 RN84 SRN0J-10-GP-U HDMI_DATA0- 20,53 HDMI_DATA0+ 20,53 SRN0J-10-GP-U RN85 HDMI_CLK- 20,53 HDMI_CLK+ 20,53 2UMA HDMI_DETECT# B 20 0R2J-2-GP RN32 GMCH_BL_ON GMCH_LCDVDD_ON 2 UMA LIBG R384 TV_DACC TV_DACB TV_DACA CRT_IREF R162 0R2J-2-GP RN33 GMCH_VS GMCH_HS SC2D2U6D3V3MX-1-GP R178 100KR2F-L1-GP A DIS FOR UMA,change to 75 ohm (66.75036.08L) 2K37R2F-GP DIS C760 layout take note UMA SRN100KJ-6-GP SRN0J-7-GP SCD01U16V2KX-3GP FOR Discrete change RN to ohm (66.R0036.A8L) SRN0J-10-GP-U Remove RN88 & RN89 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cantiga (2 of 6) Size SRN10KJ-5-GP Document Number Rev JV71-MV DDR3 Madison Date: UMA 52 RN31 R61 FOR UMA,change to 150 ohm (66.15156.08L) SM_RCOMP_VOL R446 1KR2F-3-GP GFXVR_EN 45 EC78 C759 EC21 1 SM_RCOMP_VOH R441 3K01R2F-3-GP MCH_TSATN# DY LCTLA_CLK LCTLB_DATA PEG_TXP[15 0] SRN0J-7-GP 1D5V_S3 R445 DY 52 RN30 UMA GFXVR_EN PEG_TXN[15 0] 12 SRN33J-4-GP A 52 33R2J-2-GP 1D05V_S0 R387 56R2J-4-GP PEG_RXP[15 0] R419 HDA_BCLK HDA_SYNC HDA_RST# HDA_SDO 71.CNTIG.00U 3D3V_S0 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 D PEG_TXN0_L PEG_TXP0_L RN36 CANTIGA-GM-GP-U-NF RN34 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 0R2J-2-GP HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC 52 71.CNTIG.00U for HDMI port C DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# PEG_RXN[15 0] PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 CANTIGA-GM-GP-U-NF GFXVR_EN N28 M28 G36 E36 K36 CLK_MCH_OE# H36 modify by RF DY H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm 1D05V_S0 AH37 AH36 AN36 AJ35 AH34 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 CRT_GREEN J28 G29 GFX_VID[4 0] GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 GMCH_BLUE NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47 NC 4,12,38 PM_THRMTRIP-A# BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 MISC DY HDA C324 SC100P50V2JN-3GP ME PLT_RST1# PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR PM_EXTTS#0 PM_EXTTS#1 PM 13,33 13,25,31,32,34,35,52 R29 B7 N33 P32 AT40 RSTIN# AT11 NB_THERMTRIP# T20 PM_DPRSLPVR_MCH R32 13 PM_SYNC# 4,12,40 H_DPRSTP# 16,17 PM_EXTTS#0 R385 AE35 AE43 AE46 AH42 CFG20 TV_DCONSEL_0 TV_DCONSEL_1 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 Close to GMCH as 500 mils SC47P50V2JN-3GP 1 4K02R2F-GP C31 E32 DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13 DY CFG16 R193 M_RCOMPP TV_RTN PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 49D9R2F-GP C270 2 3D3V_S0 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AE40 AE38 AE48 AH40 13 13 13 13 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 VGA R443 80D6R2F-L-GP CFG CFG9 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 SCD1U10V2KX-4GP 1D5V_S3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 DMI C T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 CPU_SEL0 CPU_SEL1 CPU_SEL2 GRAPHICS VID 3,4 3,4 3,4 AE41 AE37 AE47 AH39 TV DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 PEG_CMP T37 T36 PEG_COMPI PEG_COMPO L_CTRL_DATA L_DDC_CLK L_DDC_DATA GRAPHICS BG23 BF23 BH18 BF18 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 AR24 AR21 AU24 AV20 18 34 PCI-EXPRESS RESERVED#AY21 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 16 16 17 17 LVDS AY21 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 RESERVED#B31 RESERVED#B2 RESERVED#M1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 AP24 AT21 AV24 AU20 B31 B2 M1 RSVD D SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SCD1U10V2KX-4GP DDR CLK/ CONTROL/COMPENSATION RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24 R196 OF 10 NB1C M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 Wednesday, October 28, 2009 Sheet -1 of 62 B SA_RAS# SA_CAS# SA_WE# BB20 BD20 AY20 M_A_RAS# 16 M_A_CAS# 16 M_A_W E# 16 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_DQS[7 0] M_A_DQS#[7 0] M_A_A[14 0] M_A_DM[7 0] 16 M_A_DQS[7 0] 16 M_A_DQS#[7 0] 16 M_A_A[14 0] 16 M_B_DQ[63 0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 OF 10 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 M_B_BS#0 17 M_B_BS#1 17 M_B_BS#2 17 M_B_RAS# 17 M_B_CAS# 17 M_B_W E# 17 D M_B_DM[7 0] B M_A_BS#0 16 M_A_BS#1 16 M_A_BS#2 16 MEMORY BD21 BG18 AT25 SYSTEM A NB1E 17 M_B_DQ[63 0] SA_BS_0 SA_BS_1 SA_BS_2 M_A_DM[7 0] MEMORY SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SYSTEM C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 DDR D M_A_DQ[63 0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 OF 10 NB1D 16 M_A_DQ[63 0] DDR CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF 71.CNTIG.00U 71.CNTIG.00U SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 M_B_DM[7 0] 17 M_B_DQS[7 0] M_B_DQS[7 0] 17 M_B_DQS#[7 0] M_B_DQS#[7 0] 17 M_B_A[14 0] C M_B_A[14 0] 17 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cantiga (3 of 6) Size Date: Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet of -1 62 2 DY C278 UMA 2 1 UMA C279 Coupling CAP T32 Coupling CAP VCC 1 2 ST330U2D5VBM-GP 2 2 C SC1U10V3KX-3GP C340 SC1U10V3KX-3GP C320 C298 C329 SCD22U10V2KX-1GP C347 SCD22U10V2KX-1GP 71.CNTIG.00U C290 SCD1U10V2KX-4GP 1 Place on the Edge AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23 VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF CANTIGA-GM-GP-U-NF C350 SCD1U10V2KX-4GP VCC SM LF VCC GFX AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH C348 SC4D7U6D3V3KX-GP VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF C308 SC4D7U6D3V3KX-GP 80.3371V.12L C323 SC4D7U6D3V3KX-GP C349 TC22 DY SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP DY C359 1D5V_S3 C367 1D05V_S0 VCC NCTF Place on the Edge VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC D VCC CORE AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC POWER 2 1 2 1 2 UMA C271 1 1 2 1 2 1 2 2 DY C286 SCD47U6D3V2KX-GP VCC GFX NCTF UMA C275 C289 C284 SCD1U10V2KX-4GP UMA C285 C612 SCD1U10V2KX-4GP UMA C302 SCD1U10V2KX-4GP DY C282 SCD1U10V2KX-4GP UMA C276 SC1U10V3ZY-6GP DY C273 SC4D7U6D3V3KX-GP UMA C277 SC4D7U6D3V3KX-GP C292 SC4D7U6D3V3KX-GP TC18 SC10U6D3V5MX-3GP VCC SM C280 SCD1U10V2KX-4GP SCD22U10V2KX-1GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP VCC_GFXCORE C361 VCC_AXG_SENSE VSS_AXG_SENSE 71.CNTIG.00U C281 AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 FOR VCC SM CANTIGA-GM-GP-U-NF U60(ISL6263ACRZ-T-GP) place near Cantiga C249 DY SCD1U10V2KX-4GP AJ14 AH14 C274 DY SC4D7U6D3V3KX-GP VCC_AXG_SENSE VSS_AXG_SENSE C287 Coupling CAP 370 mils from the Edge SCD47U16V3ZY-3GP 45 VCC_AXG_SENSE 45 VSS_AXG_SENSE C291 DIS SC4D7U6D3V3KX-GP C VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG R439 0R5J-6-GP DY OF 10 NB1F FOR VCC CORE DIS SC4D7U6D3V3KX-GP Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 0R5J-6-GP SC4D7U6D3V3KX-GP VCC_GFXCORE 1D05V_S0 R438 SC4D7U6D3V3KX-GP VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 ST220U2D5VBM-2GP BA36 BB24 BD16 BB21 AW16 AW13 AT13 VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM POWER NB1G AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 D B VCC_GFXCORE OF 10 1D5V_S3 B place near Cantiga A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cantiga (4 of 6) Size Date: Document Number Rev JV71-MV DDR3 Madison Wednesday, October 28, 2009 Sheet of -1 62 C263 SCD1U10V2KX-4GP C621 SCD1U10V2KX-4GP 2 B 2 DY 1D05V_S0 C722 DY UMA 2 C732 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DY Cantiga (5 of 6) Size Date: C268 SCD47U6D3V2KX-GP 1 DY 2 1 C675 R396 0R0603-PAD R398 0R2J-2-GP SC4D7U6D3V3KX-GP UMA R167 0R2J-2-GP C620 SCD47U6D3V2KX-GP VTTLF1 VTTLF2 VTTLF3 C650 SCD47U6D3V2KX-GP A8 L1 AB2 C676 SCD47U6D3V2KX-GP VTTLF LVDS VTTLF VTTLF VTTLF 2 2 DMI DY VCCD_LVDS VCCD_LVDS 71.CNTIG.00U SB 1202 C186 C670 SC4D7U6D3V3KX-GP 2 AXF SM CK HV PEG A CK TV D TV/CRT C739 456mA CANTIGA-GM-GP-U-NF 2 HDA 2 C175 SC4D7U6D3V3KX-GP VCCD_PEG_PLL AH48 AF48 AH47 AG47 C283 A PEG A SM 2 1 UMA AA47 VCC_DMI VCC_DMI VCC_DMI VCC_DMI 1D05V_S0 1782mA C712 2 1 C662 SC2D2U6D3V3MX-1-GP CRT A LVDS 2 1 2 1 2 2 2 2 1 2 2 UMA VCCD_HPLL UMA 1D8V_NB_S0 119mA SC10U6D3V5MX-3GP SCD1U10V2KX-4GP DIS C235 VCCD_QDAC M38 L37 1D8V_SUS_DLVDS 60.3mA L28 AF1 V48 U48 V47 U47 U46 DY SC10U6D3V5MX-3GP R159 VCCD_TVDAC VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG 3D3V_HV_S0 106mA C758 SCD1U10V2KX-4GP C690 SCD1U10V2KX-4GP 1D05V_RUN_PEGPLL 50mA R153 0R0603-PAD 0R2J-2-GP 157.2mA M25 C35 B35 A35 C751 SCD1U10V2KX-4GP C678 1D5VRUN_QDAC K47 VCC_HV VCC_HV VCC_HV C UMA 1D5V_S3 SC10U6D3V5MX-3GP 1D5VRUN_TVDAC VCC_TX_LVDS 1D8V_TXLVDS_S0 UMA R448 0R0603-PAD SC10U6D3V5MX-3GP R383 DY 1D8V_NB_S0 C188 SCD1U10V2KX-4GP SCD01U16V2KX-3GP VCC_HDA VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK BF21 BH20 BG20 BF20 C877 SC1U10V2ZY-GP A32 200mA B22 B21 A21 SC1U10V3KX-3GP C634 VCCA_TV_DAC VCCA_TV_DAC VCC_AXF VCC_AXF VCC_AXF SC4D7U6D3V3KX-GP C715 C174 DY SC1U10V2ZY-GP DY C272 SC4D7U6D3V3KX-GP VCC_HDA 0R2J-2-GP 58.7mA SCD1U10V2KX-4GP SCD01U16V2KX-3GP DY UMA C251 SC4D7U6D3V3KX-GP R375 0R0603-PAD SCD1U10V2KX-4GP SCD1U10V2KX-4GP 1D5VRUN_TVDAC C247 C616 SC1KP50V2KX-1GP C635 C691 SCD1U10V2KX-4GP 1D5VRUN_QDAC PBY160808T-181Y-GP C876 74.G1117.B3C UMA SCD1U10V2KX-4GP C750 B24 A24 3D3V_S0 1D8V_NB_S0 G1117-18T63UF-GP SC4D7U6D3V3KX-GP 3D3V_S0_DAC_1 1D5V_S0 C243 322mA POWER SC4D7U6D3V3KX-GP VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VIN VOUT GND 1D05V_S0 SC1U10V3KX-3GP SC1U10V3KX-3GP C305 AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 I=1A U66 1D5V_SUS_SM_CK SCD1U10V2KX-4GP R386 0R2J-2-GP DY 1D05V_SUS_MCH_PLL2 UMA VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM R377 0R0603-PAD 1D5V_S0 180ohm 100MHz C293 3D3V_S0_DAC C205 2nd = 68.00214.101 SC1U10V3KX-3GP DY C313 SC2D2U6D3V3MX-1-GP DY C295 SC4D7U6D3V3KX-GP 139.2mA C697 SCD1U10V2KX-4GP UMA UMA AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 83.BAT54.D81 2nd = 83.BAT54.X81 1D05V_SM_CK C294 SC4D7U6D3V3KX-GP 220ohm 100MHz C309 R202 0R0603-PAD 24mA 1D05V_RUN_PEGPLL FCM1608CF-221T02-GP DY VCCA_PEG_PLL 3D3V_HV_S0 R376 0R0603-PAD R106 10R2J-2-GP BAT54-5-GP 1D05V_S0 C692 SCD1U10V2KX-4GP L20 2nd = 68.00119.111 50mAAA48 C306 C752 VCCA_PEG_BG 1D05V_RUN_PEGPLL SC4D7U6D3V3KX-GP DY C754 SC4D7U6D3V3KX-GP C753 SC4D7U6D3V3KX-GP C755 SC4D7U6D3V3KX-GP 1D05V_S0 68.00217.521 AD48 C704 SCD1U10V2KX-4GP 1D05V_SM SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC10U6D3V5MX-3GP DY 2nd = 68.00248.061 VCCA_PEG_BG 1D05V_HV_S0 2 VSSA_LVDS J47 3D3V_S0 1 VCCA_LVDS 13.2mA D VCCA_MPLL J48 VCCA_HPLL D5 AE1 852mA 1D05V_S0 AD1 M_VCCA_MPLL U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 M_VCCA_HPLL VTT VCCA_DPLLB VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT C267 SC4D7U6D3V3KX-GP 1 L48 PLL M_VCCA_DPLLB 1D05V_S0 M_VCCA_MPLL C694 68.00206.041 VCCA_DPLLA DY R447 0R0603-PAD C687 FCM1608KF-1-GP L21 A 2 UMA M_VCCA_HPLL 68.00217.161 L6 VCCA_DAC_BG VSSA_DAC_BG F47 R421 0R0603-PAD R400 0R2J-2-GP 24mA R156 0R0603-PAD A25 B25 M_VCCA_DPLLA DY C644 2nd = 68.00248.061 M_VCCA_DAC_BG R168 0R2J-2-GP C636 SC27P50V2JN-2-GP 1D05V_SUS_MCH_PLL2 FCM1608KF-1-GP L22 B VCCA_CRT_DAC VCCA_CRT_DAC 1D5V_S0 1 DY 68.00217.161 DY B27 A26 M_VCCA_DPLLB C642 120ohm 100MHz R379 0R2J-2-GP 1D8V_TXLVDS_S0 DY 480mA R430 0R0603-PAD UMA OF 10 NB1H 1 UMA R390 0R2J-2-GP DY 2 C624 SCD1U10V2KX-4GP SC10U6D3V5MX-3GP C SCD1U10V2KX-4GP SC10U6D3V5MX-3GP 65mA R399 0R0603-PAD 1D05V_S0 M_VCCA_DPLLA C622 C617 65mA UMA 2 1D05V_S0 R371 0R0603-PAD C207 UMA 1 R374 0R0603-PADC625 5mA 2nd = 74.09198.Q7F 3D3V_S0_DAC DY SCD01U16V2KX-3GP 74.09091.J3F UMA SCD1U10V2KX-4GP BC1 UMA C141 NC#4 UMA 3D3V_CRTDAC_S0 SCD1U10V2KX-4GP SCD01U16V2KX-3GP VOUT G9091-330T11U-GP BC2 C250 SC4D7U6D3V3KX-GP 73mA R378 0R0603-PAD C206 SC1U16V3ZY-GP SC1U16V3ZY-GP D VIN GND EN 1D05V_S0 3D3V_S0_DAC SC22U6D3V5MX-2GP 3 3D3V_S0_DAC Imax = 300 mA UMA U13 5V_S0 Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 10 of -1 62 DCBATOUT G218 DCBATOUT_8202_VGA GAP-CLOSE-PW R-3-GP G219 TC17 R426 10R2F-L-GP DIS 1 2 2 GAP-CLOSE-PW R-3-GP G224 GAP-CLOSE-PW R-3-GP G225 1 TC15 GAP-CLOSE-PW R-3-GP DIS DIS TC14 84.07672.037 DIS Panasonic 330uF,2V,9mohm Iripple=3A C RT8202_DL_VGA 79.33719.L01 2nd = 77.C3371.051 74.08202.A73 SB1019 65 C708 GND GND PGND RT8202APQW -GP DIS 6K34R3F-GP 17 2 Madison-Park 10KR2J-3-GP 84.07672.037 DIS VGA_CORE VOUT RT8202_LX_VGA U40 1 NC#5 NC#14 65 RT8202_OC_VGA_L RT8202_FB_VGA U17 FDMS7672-GP 10 OC FB EN/DEM DIS FDMS7672-GP VDD RT8202_BST_VGA_L RT8202_DH_VGA 1R3F-GP RT8202_LX_VGA DIS RT8202_DL_VGA R406 C649 SE330U2VDM-L-GP 13 12 11 S S S G 14 R902 16KR3F-GP R866 3D3V_VGA BOOT UGATE PHASE LGATE GAP-CLOSE-PW R-3-GP G223 DIS SCD1U25V3KX-GP S S S G M96 15 2 RT8202_EN_VGA TON PGOOD RT8202_LX_VGA D GAP-CLOSE-PW R-3-GP G222 VGA_CORE SE330U2VDM-L-GP R416 10KR2F-2-GP PM_SLP_S3# 16 R412 C665 L19 IND-D36UH-9-GP SCD1U10V2KX-4GP 13,27,33,34,38,43,45,51 RT8202_DH_VGA C668 2RT8202_LX_VGA DIS SB 1019 D D D D RT8202_PGOOD_VGA DIS C U45 VDDP DIS 0R0402-PAD-1-GP Mag 0.56uH DCR=1.6~1.8mohm Irating=25A,Isat=40A D D D D C710 SC100P50V2JN-3GP 2 2 51 VGACORE_PW ROK 84.08692.037 C652 SCD1U50V3KX-GP C685 SC1U10V3KX-4GP R420 C655 DIS SC10U25V6KX-1GP 5V_S5 DIS C696 SC1KP50V2KX-1GP U41 FDMS8692-GP DIS SC10U25V6KX-1GP RT8202_TON_VGA DIS 65 DIS SC10U25V6KX-1GP C711 SC1U10V3KX-4GP DIS S S S G R422 10KR2F-2-GP DIS CH521S-30-GP-U1 DIS D D D D R418 1MR2F-GP DCBATOUT_8202_VGA 83.00521.01F 2nd = 83.R2003.F8F RT8202_BST_VGA 3D3V_S0 DIS 2 RT8202_VDD_VGA D25 Id=23A Qg=7.2nC, Rdson=11.1~13.9mohm 5V_S5 DIS GAP-CLOSE-PW R-3-GP G221 ST15U25VDM-1-GP D DCBATOUT_8202_VGA 1 5V_S5 GAP-CLOSE-PW R-3-GP G220 Iomax=22A OCP>33A Id=15A Qg=14~19nC, Rdson=4.9~6.8mohm 79.33719.L01 2nd = 77.C3371.051 Vout=0.75*(1+Rh/Rl) 1 Designator C1148 SCD1U10V2KX-4GP R428 For M96-M2 For Madison 73.2k 64.30025.6DL R429 49K9R2F-L-GP For PARK B 30k RT8202_FB_VGA DY DIS B JV71-MV8 ENG 1002 R425 10KR2F-2-GP DIS C709 SC47P50V2JN-3GP 49.9K 64.73225.6DL 64.49925.6DL R428 73K2R2F-GP DY DIS 3D3V_VGA 3D3V_S5 R697 100KR2J-1-GP NV_VID0_D NV_VID1_D R703 100KR2J-1-GP 2N7002-11-GP DIS NV_VID0 B E 2ND = 84.27002.N31 DY 2 NV_VID0_R Q42 84.27002.W31 C740 SCD1U10V2KX-4GP SB 1019 G PW RCNTL_1 53 DIS 2 2ND = 84.27002.N31 DIS R435 10KR2F-2-GP DY MMBT2222A-3-GP S S 84.27002.W31 Q27 C DY NV_VID1 G D D DIS DY Q26 2N7002-11-GP R427 75KR2F-GP JV71-MV8 ENG 1002 2 DIS RT8202_FB_VGA R436 10KR2F-2-GP PW RCNTL_0 53 C741 SCD1U10V2KX-4GP DIS JV71-MV DDR3 Madison A JV71-MV8 ENG 1002 M96 Pro ALTV0 Vout 1.15V 0.9V Madison Pro ALTV0 Vout 1.00V 0.9V PARK XT ALTV0 Vout 1.05V 0.9V Wistron Corporation JV71-MV8 ENG 1002 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Date: A RT8202A_VGA CORE Document Number JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 48 Rev -1 of 62 5V_S0 EC127 EC128 EC116 EC115 EC114 EC113 2 2 EC129 DY DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP DY DY D EC96 SCD1U50V3KX-GP DY EC95 2 EC94 SCD1U50V3KX-GP DY DY 1 SCD1U25V2ZY-1GP 1 2 DY EC93 SCD1U50V3KX-GP DY DY SCD1U50V3KX-GP DY EC92 SCD1U50V3KX-GP SCD1U50V3KX-GP DY EC91 EC90 SCD1U50V3KX-GP DY EC89 SCD1U50V3KX-GP 1 DY SCD1U50V3KX-GP SCD1U50V3KX-GP DY EC88 EC87 SCD1U50V3KX-GP 1 SCD1U50V3KX-GP EC86 SB 0520 EC85 EC112 DY SCD1U25V2ZY-1GP DY DCBATOUT EC111 EC67 2 EC65 SCD1U50V3KX-GP 0622 1 DY -1 SCD1U50V3KX-GP DY EC64 SCD1U50V3KX-GP EC63 SCD1U50V3KX-GP DY D 1 EC62 SCD1U50V3KX-GP EC61 SCD1U50V3KX-GP 2 1D05V_S0 DCBATOUT VGA_CORE EC102 EC103 DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP DY 2 DIS DY 34.4C322.001 34.49U26.001 34.49U26.001 1 34.49U26.001 34.49U26.001 H57 STF256R89H178-GP 1 H50 DIS JV71-MV DDR3 Madison SPRING_GND2 SPRING-12-GP-U SPRING_GND3 SPRING-12-GP-U SPRING_GND4 SPRING-12-GP-U 1 SPRING_GND10 SPRING-7-GP H46 STF237R113H111-GP DIS SPRING_GND11 SPRING-7-GP STF237R113H111-GP STF237R125H42-GP DIS STF237R113H111-GP H47 STF237R113H111-GP STF237R125H42-GP 1 H49 H45 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Date: B H48 JV71-MV8 1005 SPRING_GND18 SPRING-43-GP-U TOP 34.41Y19.001 34.4C322.001 34.43E28.001 SPRING_GND19 SPRING-9-GP HOLE355X355R111-S1-GP H59 STF237R113H111-GP 1 STF237R125H42-GP H88 SPRING_GND12 SPRING-7-GP HOLE355X355R111-S1-GP H27 H62 34.15J03.001 HOLE355X355R111-S1-GP 1 HOLE355X355R111-S1-GP 1 HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP H26 34.43E28.001 34.15J03.001 1 H25 SPRING_GND13 SPRING-7-GP SPRING_GND1 SPRING-56-GP HOLE355X355R111-S1-GP H24 HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP H35 H10 34.43E28.001 H58 HOLE H7 HOLE355X355R111-S1-GP H6 HOLE355X355R111-S1-GP 1 SPRING_GND9 SPRING-56-GP 1 H19 1 SPRING_GND8 SPRING-43-GP-U A HOLE355X355R111-S1-GP H11 HOLE355X355R111-S1-GP H29 H5 HOLE355X355R111-S1-GP H4 HOLE355X355R111-S1-GP B SPRING_GND17 SPRING-16-GP 1 H9 H2 HOLE H3 SPRING_GND20 SPRING-9-GP MDC VGA STF237R113H111-GP NB SPRING_GND6 SPRING-16-GP SPRING_GND5 SPRING-16-GP MINICARD CPU C DIS 34.41Y19.001 DY SCD1U25V2ZY-1GP DY SCD1U25V2ZY-1GP DY DIS EC101 DIS EC100 EC99 EC98 EC97 EC110 EC120 2 SCD1U25V2ZY-1GP DY 2 DY EC119 EC122 SCD1U25V2ZY-1GP DY EC121 SCD1U25V2ZY-1GP DY EC124 SCD1U25V2ZY-1GP 2 EC123 SCD1U25V2ZY-1GP DY EC126 SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP EC125 DIS EC108 SCD1U25V2ZY-1GP 5V_S5 EC107 SCD1U25V2ZY-1GP DDR_VREF_S3 EC106 SCD1U25V2ZY-1GP 1D5V_S3 3D3V_S0 EC105 SCD1U25V2ZY-1GP 0622 SCD1U25V2ZY-1GP -1 C EC104 2 PD 1019 EMI/Spring/Boss JV71-MV DDR3 Madison Document Number W ednesday, October 28, 2009 Sheet 49 of Rev -1 62 A B C D E Check test point 3D3V_S0 TP214 AFTE14P-GP 3D3V_AUX_S5 TP213 AFTE14P-GP 3D3V_S5 TP210 AFTE14P-GP 5V_S5 TP209 AFTE14P-GP TP142 AFTE14P-GP TP161 AFTE14P-GP TP160 AFTE14P-GP TP112 AFTE14P-GP 4 13,34 PM_PW RBTN# 4,12 H_PW RGD 34,41 S5_ENABLE 4,6 H_CPURST# Test Point放 放放Dimm Door打 打打打打打打 3 2 JV71-MV DDR3 Madison 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title AFTE_TP Size A3 Date: A B C D Document Number Rev -1 JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet E 50 of 62 AO4468, SO-8 Id=11.6A, Qg=9~12nC Rdson=17.4~22m ohm DIS 1D5V_VGA DIS AO4468-GP 84.04468.037 DIS C885 SCD1U16V2KX-3GP C884 SC10U6D3V3MX-GP U69 S S S G DIS D D D D D RUN_POWER_ON TC33 ST150U6D3VBM-1-GP 1D5V_S3 1D5V_VGA 2 77.C1571.09L 2ND = 80.15715.12L D RUNON_R_1 Q38 S R16 G 84.S0610.B31 2ND = 84.00610.C31 1 R758 330KR2J-L1-GP DIS R864 DIS_EN_1D5_RUN M96 0R2J-2-GP 1V_VGA_PWRGD SA0928 D 2 DIS SCD22U25V3KX-GP R757 100KR2J-1-GP DIS C296 DY DIS_EN_1D5_RUN_R 330KR2J-L1-GP 13,27,33,34,38,43,45,48 PM_SLP_S3# 0R2J-2-GP NDS0610-NL-GP DIS R756 DIS RUNON_R D R759 Q39 2N7002-11-GP DGPU_PWROK_R 84.27002.W31 2ND = 84.27002.N31 G S 0R2J-2-GP Madison-Park DIS C886 CO-LAYOUT SCD1U10V2KX-4GP DY C C APL5930 for 1V_VGA 1D5V_S3 5V_S5 1 C1151 C1150 SC10U10V5KX-2GP DIS R883 2K2R2J-2-GP DIS C1149 SC1U16V3KX-2GP 1V_VGA Iomax=2.5A Vo(cal.) = 1.013964 V DIS SC10U10V5KX-2GP 3D3V_S0 Designator DIS 1V_VGA_PWRGD 22.6k R887 20.5k 84.5k 1V_VGA_PWR 1V_VGA C1155 9025_FB DY DIS R887 84K5R2F-GP DIS C1154 G226 GAP-CLOSE-PWR G227 GAP-CLOSE-PWR G228 GAP-CLOSE-PWR G229 B GAP-CLOSE-PWR DIS SCD1U25V3ZY-1GP DIS C1153 C1152 1 DIS DIS 1 DIS APL5930KAI-TRG-GP VGACORE_PWROK_EN 0R2J-2-GP B R885 22K6R2F-1-GP SC10U10V5KX-2GP R886 SC10U10V5KX-2GP 0R2J-2-GP 48 VGACORE_PWROK VIN#5 VOUT#4 VOUT#3 FB GND VCNTL POK EN VIN#9 SC100P50V2JN-3GP DY 2 R884 1 For Madison 7.87k Vo=0.8*(1+(R1/R2)) U80 13,27,33,34,38,43,45,48 PM_SLP_S3# For M96-M2 R885 1001 modify R890 3D3V_S0 10KR2F-2-GP 3D3V_S0 8015B_PWRGD U81 RT8015BGQW-GP DY Iomax=2A 1D8V_PWR R894 8015B_COMP_1 20KR2F-L-GP SC330P50V2KX-3GP DIS R893 16KR2F-GP C1161 1 C1160 C1162 DIS GAP-CLOSE-PWR-3-GP G154 DIS DIS 8015B_FB R892 820KR2F-GP DIS DIS C1163 11 74.08015.A43 DIS R891 20KR2F-L-GP 8015B_RT SC22U6D3V5MX-2GP SHDN/RT DIS COMP GND 1 LX#3 FB 1D8V_VGA G153 IND-3D3UH-57GP SC22U6D3V5MX-2GP 10 PGOOD 8015B_LX34 SC100P50V2JN-3GP 8015B_COMP 8015B_FB LX#4 L60 C1159 SC10U10V5KX-LGP VDD 68.3R310.20A PGND DIS PVDD GND C1158 SC10U10V5KX-LGP DIS GAP-CLOSE-PWR-3-GP DIS C1164 A A SCD1U25V2KX-GP C1165 SCD1U10V2KX-5GP Vo=0.8*(1+(R1/R2)) DY JV71-MV DDR3 Madison DIS 1 R895 1V_VGA_PWRGD_R 0R0402-PAD Wistron Corporation Q41 AO7401-GP DY S 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C D Title ATI POWER G 1V_VGA_PWRGD Size Document Number Custom Rev JV71-MV DDR3 Madison Date: Wednesday, October 28, 2009 Sheet 51 of -1 62 PEG_TXP[15 0] PEG_TXN[15 0] 1 OF VGA1A PEG_TXP[15 0] PEG_RXP[15 0] PEG_TXN[15 0] PEG_RXN[15 0] PEG_TXP0 PEG_TXN0 AA38 Y37 PCIE_RX0P PCIE_RX0N PCIE_TX0P PCIE_TX0N PEG_RXP0_1 PEG_RXN0_1 Y33 Y32 C901 SCD1U16V2KX-3GP C902 SCD1U16V2KX-3GP DIS PEG_TXP1 PEG_TXN1 Y35 W36 D PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N PEG_RXP1_1 PEG_RXN1_1 W33 W32 C903 SCD1U16V2KX-3GP C904 SCD1U16V2KX-3GP DIS PEG_TXP2 PEG_TXN2 W38 V37 PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N U33 U32 PEG_RXP2_1 PEG_RXN2_1 C905 PEG_TXP3 PEG_TXN3 V35 U36 PCIE_RX3P PCIE_RX3N PCIE_TX3P PCIE_TX3N U30 U29 PEG_RXP3_1 PEG_RXN3_1 C908 SCD1U16V2KX-3GP C907 SCD1U16V2KX-3GP SCD1U16V2KX-3GP C906 SCD1U16V2KX-3GP DIS DIS PEG_TXP4 PEG_TXN4 U38 T37 PCIE_RX4P PCIE_RX4N PCIE_TX4P PCIE_TX4N PEG_RXP4_1 PEG_RXN4_1 T33 T32 C910 SCD1U16V2KX-3GP C909 SCD1U16V2KX-3GP DIS T35 R36 PCIE_RX5P PCIE_RX5N PEG_TXP6 PEG_TXN6 R38 P37 PCIE_RX6P PCIE_RX6N PEG_TXP7 PEG_TXN7 P35 N36 PCIE_RX7P PCIE_RX7N PEG_TXP8 PEG_TXN8 N38 M37 PCIE_RX8P PCIE_RX8N PEG_TXP9 PEG_TXN9 M35 L36 PCIE_RX9P PCIE_RX9N PEG_TXP10 PEG_TXN10 L38 K37 PCIE_RX10P PCIE_RX10N PEG_TXP11 PEG_TXN11 K35 J36 PCIE_RX11P PCIE_RX11N PEG_TXP12 PEG_TXN12 J38 H37 PCIE_RX12P PCIE_RX12N PEG_TXP13 PEG_TXN13 H35 G36 PCIE_RX13P PCIE_RX13N PEG_TXP14 PEG_TXN14 G38 F37 PEG_TXP15 PEG_TXN15 F35 E37 PCI EXPRESS INTERFACE PEG_TXP5 PEG_TXN5 PCIE_TX5P PCIE_TX5N PEG_RXP5_1 PEG_RXN5_1 T30 T29 C911 SCD1U16V2KX-3GP C912 SCD1U16V2KX-3GP DIS PCIE_TX6P PCIE_TX6N P33 P32 PEG_RXP6_1 PEG_RXN6_1 C914 SCD1U16V2KX-3GP C913 SCD1U16V2KX-3GP PCIE_TX7P PCIE_TX7N P30 P29 PEG_RXP7_1 PEG_RXN7_1 C915 SCD1U16V2KX-3GP C916 SCD1U16V2KX-3GP PCIE_TX8P PCIE_TX8N N33 N32 PEG_RXP8_1 PEG_RXN8_1 C918 SCD1U16V2KX-3GP C917 SCD1U16V2KX-3GP PCIE_TX9P PCIE_TX9N N30 N29 PEG_RXP9_1 PEG_RXN9_1 C919 PCIE_TX10P PCIE_TX10N L33 L32 PEG_RXP10_1 PEG_RXN10_1 C922 PCIE_TX11P PCIE_TX11N L30 L29 PEG_RXP11_1 PEG_RXN11_1 C923 SCD1U16V2KX-3GP C924 SCD1U16V2KX-3GP PCIE_TX12P PCIE_TX12N K33 K32 PEG_RXP12_1 PEG_RXN12_1 C926 SCD1U16V2KX-3GP C925 SCD1U16V2KX-3GP PCIE_TX13P PCIE_TX13N J33 J32 PEG_RXP13_1 PEG_RXN13_1 C927 SCD1U16V2KX-3GP C928 SCD1U16V2KX-3GP PCIE_RX14P PCIE_RX14N PCIE_TX14P PCIE_TX14N K30 K29 PEG_RXP14_1 PEG_RXN14_1 C930 SCD1U16V2KX-3GP C929 SCD1U16V2KX-3GP PCIE_RX15P PCIE_RX15N PCIE_TX15P PCIE_TX15N H33 H32 PEG_RXP15_1 PEG_RXN15_1 C931 SCD1U16V2KX-3GP C932 SCD1U16V2KX-3GP C DIS DIS DIS SCD1U16V2KX-3GP C920 SCD1U16V2KX-3GP DIS SCD1U16V2KX-3GP C921 SCD1U16V2KX-3GP DIS DIS DIS DIS DIS DIS B PEG_RXP[15 0] PEG_RXN[15 0] PEG_RXP0 PEG_RXN0 DIS PEG_RXP1 PEG_RXN1 D DIS PEG_RXP2 PEG_RXN2 DIS PEG_RXP3 PEG_RXN3 DIS PEG_RXP4 PEG_RXN4 DIS PEG_RXP5 PEG_RXN5 DIS PEG_RXP6 PEG_RXN6 DIS PEG_RXP7 PEG_RXN7 DIS PEG_RXP8 PEG_RXN8 C DIS PEG_RXP9 PEG_RXN9 DIS PEG_RXP10 PEG_RXN10 DIS PEG_RXP11 PEG_RXN11 DIS PEG_RXP12 PEG_RXN12 DIS PEG_RXP13 PEG_RXN13 DIS PEG_RXP14 PEG_RXN14 DIS PEG_RXP15 PEG_RXN15 DIS B CLOCK AB35 AA36 CLK_PCIE_PEG CLK_PCIE_PEG# PCIE_REFCLKP PCIE_REFCLKN 1V_VGA DIS CALIBRATION CO-LAYOUT PLT_RST1# PLT_RST1# R771 0R2J-2-GP NC#AJ21 NC#AK21 PWRGOOD PLT_RST1#_M92_1 PCIE_CALRP Y30 PCIE_CALRN Y29 1K27R2F-L-GP 2 R770 2KR2F-3-GP Madison-Park DIS 10KR2J-3-GP 7,13,25,31,32,34,35 AJ21 AK21 AH16 R769 R768 AA30 PERST# DIS C933 SC22P50V2JN-4GP MADISON-PRO-GP DIS 71.MDSON.M01 DIS JV71-MV DDR3 Madison A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Madison ( of ) PCIE Size A3 Date: Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 52 -1 of 62 DIS TX2P_DPA0P TX2M_DPA0N TXCBP_DPB3P TXCBM_DPB3N TX3P_DPB2P TX3M_DPB2N DPB TX4P_DPB1P TX4M_DPB1N TX5P_DPB0P TX5M_DPB0N TXCCP_DPC3P TXCCM_DPC3N TX0P_DPC2P TX0M_DPC2N DPC TX1P_DPC1P TX1M_DPC1N TX2P_DPC0P TX2M_DPC0N TXCDP_DPD3P TXCDM_DPD3N TX3P_DPD2P TX3M_DPD2N DPD TX4P_DPD1P TX4M_DPD1N I2C AK24 TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N AU20 AT19 TXOUT_L3P TXOUT_L3N AT21 AR20 AU22 AV21 MADISON-PRO-GP CRT_BLUE AT23 AR22 R2 R2# G2 G2# B2 B2# C Y COMP H2SYNC V2SYNC DY TP260 VGA_XO_IN AW34 TP265 VGA_XO_IN2 AW35 DPLL_VDDC XTALIN XTALOUT AUX1P AUX1N PLL/CLOCK DDC2CLK DDC2DATA XO_IN AUX2P AUX2N XO_IN2 For Thermal sensor AF29 AG29 FAN_PWM AK32 DPLUS DMINUS DDCCLK_AUX4P DDCDATA_AUX4N THERMAL DDCCLK_AUX5P DDCDATA_AUX5N DPE_VDD18 TS_FDO AL31 R792 1MR2J-1-GP DIS CRT_BLUE 19 TSVDD TSVSS DDCCLK_AUX7P DDCDATA_AUX7N 5mA MADISON-PRO-GP DIS AC36 AC38 CRT_HSYNC CRT_VSYNC SC10P50V2JN-4GP SB 1022 82.30034.461 2ND = 82.30034.701 AVSSQ 19,56 19,56 DAC1_VDD1DI 1D8V_VGA 50mA C942 SCD1U16V2KX-3GP R785 DAC1_AVDD AVSSQ DIS DIS AC30 AC31 AD30 AD31 DAC2_A2VDD AF30 AF31 3D3V_VGA 130mA C949 SCD1U16V2KX-3GP AC32 AD32 AF32 R787 C946 DIS C950 DIS C948 DIS AVSSQ BLM15BD121SS1D-GP DIS 68.00084.F81 2ND = 68.00217.701 1D8V_VGA C954 C955 DIS BLM15BD121SS1D-GP DIS 68.00084.F81 2ND = 68.00217.701 B DAC2_VDD2DI DAC2_A2VDDQ DAC2_A2VDD AD33 DAC2_A2VDDQ 1.5mA C956 SCD1U16V2KX-3GP 1D8V_VGA L40 BLM15BD121SS1D-GP DIS DIS AF33 DIS 3D3V_VGA 68.00084.F81 2ND = 68.00217.701 R790 715R2F-GP AM26 AN26 CRT_DDCCLK 19 CRT_DDCDATA 19 C1063 SCD1U16V2KX-3GP DIS AM27 AL27 U67 AM19 AL19 ATI_HDMI_CLK ATI_HDMI_DAT 20 20 R582 R581 33,34 SMBC_Therm 33,34 SMBD_Therm AN20 AM20 DIS DIS AL30 AM30 0R2J-2-GP 0R2J-2-GP KBC_THERM_G781_CLK KBC_THERM_G781_DAT G781_ALERT# SMBCLK VCC SMBDATA DXP ALERT# DXN GND THERM# GPU_DPLUS GPU_DMINUS GPU_THERM# G781P8F-GP DIS AL29 AM29 C1064 SC2200P50V2KX-2GP DIS 3D3V_VGA 3D3V_VGA AN21 AM21 AJ30 AJ31 DIS Q40 MMBT3904-4-GP AK30 AK29 B HPD1 DIS ATI_HDMI_DETECT 20 R585 2K2R2F-GP R586 2K2R2F-GP DIS DIS A 84.T3904.C11 2ND = 84.03904.L06 JV71-MV DDR3 Madison R793 10KR2J-3-GP DIS Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DIS SC10P50V2JN-4GP Title SB 1022 Date: L39 Size A2 C947 DIS 45mA 0R0402-PAD DIS AG33 AA29 DIS DAC1_VDD1DI AD29 AC29 AG31 AG32 C945 1D8V_VGA L38 70mA 0R0402-PAD DAC2_VDD2DI AVSSQ DAC1_AVDD 2 XTAL-27MHZ-58-GP 0R2J-2-GP DIS AC33 AC34 R782 499R2F-2-GP DIS C960 DIS SA0915 AD34 AE34 71.MDSON.M01 19 R784 AB34 RSET VGA_XO_IN2 0R2J-2-GP C959 C DIS X6 SA0915 DDC6CLK DDC6DATA TS_A AJ32 AJ33 DIS RN90 SRN150F-1-GP VGA_XO_IN 0R2J-2-GP AN36 AP37 CRT_GREEN AF37 AE38 E TP247 DDC1CLK DDC1DATA DDCCLK_AUX3P DDCDATA_AUX3N GPU_DPLUS GPU_DMINUS lower even R2SET AV33 AU34 GPU_TXAOUT2+ 18 GPU_TXAOUT2- 18 71.MDSON.M01 CRT_RED 19 AE36 AD35 DPLL_PVDD DPLL_PVSS DDC/AUX VGA_XTALIN VGA_XTALOUT GPU_TXAOUT1+ 18 GPU_TXAOUT1- 18 AP35 AR35 CRT_GREEN AD39 AD37 DPLL_PVDD AM32 AN32 GPU_TXAOUT0+ 18 GPU_TXAOUT0- 18 AR37 AU39 VREFG 75mA GPU_TXACLK+ 18 GPU_TXACLK- 18 AW37 AU35 VDD1DI VSS1DI A2VDD DPLL_VDDC For Madison 10K DIS AT17 AR16 AP34 AR34 For M96-M2 R11 AVDD AVSSQ A2VDDQ AH13 AN31 DIS RSET HPD1 125mA R10 HSYNC VSYNC A2VSSQ C958 SCD1U16V2KX-3GP DIS DIS A B B# 1 R789 249R2F-GP R899 G G# = 0.6V) VGA_VREFG Designator TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT DAC1 GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCS# GPIO_23_CLKREQ# JTAG_TRST# JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 DAC2 GENERICF GENERICG VDD2DI VSS2DI VREFG VOLTAGE DIVIDER IS (VREFG = VDDR4,5(1.8V) / AU16 AV15 DIS TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N 1 HPD1 R788 499R2F-2-GP TXCLK_LP_DPE3P TXCLK_LN_DPE3N AT15 AR14 SC10U6D3V3MX-GP B 1D8V_VGA AU14 AV13 SCD1U16V2KX-3GP SB 1008 VGA_CLKREQ JTAG_TRST# JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE GENERICF GENERICG upper odd AF35 AG36 SCD1U16V2KX-3GP ATI-ES Back Bias (body bias) which minimizes power consumption in battery modes PD = Disable PU = Enable 1 1 1 1 TP239 TP240 TP241 TP242 TP244 TP243 TP245 TP246 R696 10KR2J-3-GP 3D3V_VGA M96 TP236 JTAG_TCK D 18 LVTMDP R899 10KR2J-3-GP TP264 ATI-ES GPU_TXBOUT2+ 18 GPU_TXBOUT2- 18 18 BLON_IN 34 ATI_LCDVDD_ON R693 10KR2J-3-GP TXOUT_U3P TXOUT_U3N AT33 AU32 GPU_TXBOUT1+ 18 GPU_TXBOUT1- 18 AG38 AH37 ATI_BRIGHTNESS GPIO_VGA_21 56 GPIO_VGA_22 AR32 AT31 AH35 AJ36 TP234 GPIO_VGA_21 TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N GPU_TXBOUT0+ 18 GPU_TXBOUT0- 18 48 PWRCNTL_1 TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N AV31 AU30 GPU_TXBCLK+ 18 GPU_TXBCLK- 18 AJ38 AK37 TP232 AR30 AT29 AK35 AL36 THERMTRIP_VGA TP233 TXCLK_UP_DPF3P TXCLK_UN_DPF3N TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N SC10U6D3V3MX-GP OSC_SPREAD Thermal_int GPIO_VGA_18 DIS GPIO_VGA_14 HDMI_DATA2+ 7,20 HDMI_DATA2- 7,20 10R2J-2-GP SC1U6D3V2KX-GP TP261 TP231 PWRCNTL_0 RN94 SRN0J-10-GP-U SCD1U16V2KX-3GP 48 HDMI_DATA1+ 7,20 HDMI_DATA1- 7,20 SCD1U16V2KX-3GP R898 10KR2J-3-GP RN93 SRN0J-10-GP-U 56 GPIO_VGA_11 56 GPIO_VGA_12 56 GPIO_VGA_13 DIS1 HDMI_DATA0+ 7,20 HDMI_DATA0- 7,20 56 GPIO_VGA_08 56 GPIO_VGA_09 HDMI_TX2P HDMI_TX2M DIS R561 AK27 AJ27 DY AT27 AR26 VARY_BL DIGON Thermal_int GPIO_VGA_07_BLON GPIO_VGA_06 GPIO_VGA_07_BLON TP230 DIS1 RN92 SRN0J-10-GP-U BLON_IN HDMI_TX1P HDMI_TX1M R783 0R2J-2-GP 34 AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24 GPIO_VGA_03 GPIO_VGA_04 1 TP228 TP229 56 GPIO_VGA_05 AU26 AV25 LVDS CONTROL DIS DIS1 HDMI_CLK+ 7,20 HDMI_CLK- 7,20 CRT_RED R R# GENERAL PURPOSE I/O R781 10KR2J-3-GP HDMI_TX0P HDMI_TX0M RN91 SRN0J-10-GP-U SCL SDA 3D3V_VGA 56 GPIO_VGA_00 56 GPIO_VGA_01 56 GPIO_VGA_02 AT25 AR24 AK26 AJ26 18 LCD_EDID_CLK 18 LCD_EDID_DAT TX5P_DPD0P TX5M_DPD0N DIS1 HYNIX-SAMSUNG-AMD HYNIX-SAMSUNG-AMD It's strap for GDDR3-136ball Need to Clarify DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 HDMI_TXCAP HDMI_TXCAM 2 1 2 R780 1 DY 2 1 2 R775 10KR2J-3-GP AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 AU24 AV23 C 1 2 DY 10KR2J-3-GP HYNIX (800MHz) (800MHz) DPA TX1P_DPA1P TX1M_DPA1N R778 SAMSUNG DVPDATA [3:0] 0100 1GB DDR3 Hynix-H5TQ1G63BFR-12C 1000 1GB DDR3 Samsung-K4W1G1646E-HC12 1100 AMD R774 10KR2J-3-GP 10KR2J-3-GP R779 10KR2J-3-GP DVPDATA [3:2:1:0] for VRAM type selection H/W strap Should provide VRAM Table for VBios request R777 10KR2J-3-GP HYNIX-AMD MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3 10KR2J-3-GP DIS SCD1U16V2KX-3GP DIS C941 R773 10KR2J-3-GP SAMSUNG-AMD C939 SC1U10V2KX-1GP SC10U6D3V3MX-GP DIS 68.00084.F81 2ND = 68.00217.701 TX0P_DPA2P TX0M_DPA2N MUTI GFX 1D8V_VGA 1D8V_VGA 1D8V_VGA 1D8V_VGA R776 C940 default brightness OF VGA1G TXCAP_DPA3P TXCAM_DPA3N BLM15BD121SS1D-GP DIS OF VGA1B DIS DPLL_VDDC L37 C C936 2 SC10U6D3V3MX-GP DIS SCD1U16V2KX-3GP C935 SC1U10V2KX-1GP C934 68.00084.F81 DIS 2ND = 68.00217.701 D 2 BLM15BD121SS1D-GP 1D8V_VGA 1V_VGA DPLL_PVDD L36 Madison ( of ) IO JV71-MV DDR3 Madison Document Number Wednesday, October 28, 2009 Sheet 53 of Rev -1 62 1D8V_VGA 400mA AH29 M96 MADISON-PRO-GP BLM15BD121SS1D-GP 2 1 1 2 1 2 2 2 1 2 2 C1027 DIS C1026 DIS C1025 DIS C1024 DY 2 1 DIS C1028 DY C1029 C1036 2 DIS DIS C1035 DIS C1034 1 AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13 C1037 B VGA_CORE 4A DIS C1042 C1043 2 DIS DIS C1041 DIS C1040 C1039 DIS C1038 DIS 1 FB_GND R862 0R2J-2-GP 2 1 2 DIS ISOLATED CORE I/O 2 1 2 1 2 1 2 1 2 1 FB_GND FB_VDDCI C1023 VGA_CORE 2 SC1U6D3V2KX-GP 2 1 2 2 2 1 2 1 2 1 2 2 2 1 1 2 2 1 2 1 1 2 2 TP254 FB_VDDC DIS SC2D2U6D3V2MX-GP AG28 DIS C1010 SC1U6D3V2KX-GP C1022 SC10U6D3V3MX-GP AF28 FB_VDDCI DIS C1009 SC1U6D3V2KX-GP DIS SC2D2U6D3V2MX-GP C1021 SC1U6D3V2KX-GP FB_VDDC DIS C1008 SC1U6D3V2KX-GP DIS SC1U6D3V2KX-GP TP253 L55 C1020 SC1U6D3V2KX-GP TP252 TPAD14-GP TPAD14-GP VGA_CORE DIS SCD1U16V2KX-3GP TPAD14-GP DIS C1007 C SCD1U16V2KX-3GP CO-LAYOUT DIS C1006 SC2D2U6D3V2MX-GP VOLTAGE SENESE DIS C1005 SC1U6D3V2KX-GP CO-LAYOUT VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI DIS C1004 SCD1U16V2KX-3GP SPVSS SC10U6D3V3MX-GP SPV10 AN10 SC10U6D3V3MX-GP SPV18 AN9 SPV10 DIS C1003 SC2D2U6D3V2MX-GP C951 68.00084.F81 DIS 2ND = 68.00217.701 SCD1U16V2KX-3GP DIS DY C1002 VGA_CORE VGA_CORE PCIE_PVDD BLM15BD121SS1D-GP C992 SC10U6D3V3MX-GP SPV18 MPV18 MPV18 DIS C1001 SC10U6D3V3MX-GP H7 H8 AM10 40mA DIS C1000 SC10U6D3V3MX-GP MPV18 PCIE_PVDD DIS C999 SC10U6D3V3MX-GP AB37 PCIE_PVDD DIS C998 SC1U6D3V2KX-GP PLL M96 DIS C991 SC1U6D3V2KX-GP R896 0R2J-2-GP M96 DIS C997 SC2D2U6D3V2MX-GP 68.00084.F81 = 68.00217.611 NC_VDDRHB NC_VSSRHB C974 SC1U6D3V2KX-GP NC_VDDRHA NC_VSSRHA D DIS SC1U6D3V2KX-GP V12 U12 DIS C996 SC2D2U6D3V2MX-GP VDDRHB VSSRHB C973 SC1U6D3V2KX-GP BLM15BD121SS1D-GP C1061 SC1U6D3V2KX-GP R897 0R2J-2-GP 2ND M20 M21 DIS SC1U6D3V2KX-GP M96 C1062 VDDRHA VSSRHA M96 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 68.00084.F81 2ND = 68.00217.611 L57 1D5V_VGA C990 SC2D2U6D3V2MX-GP M96 VRAM-CLK DIS SC1U6D3V2KX-GP M96 C972 SC1U6D3V2KX-GP L56 BLM15BD121SS1D-GP DIS SC2D2U6D3V2MX-GP 1D5V_VGA DIS C1033 VDDR4 VDDR4 VDDR4 VDDR4 C971 SC1U6D3V2KX-GP AD12 AF11 AF12 AG11 L47 VDDR4 VDDR4 VDDR4 VDDR4 DIS SC2D2U6D3V2MX-GP SC1U6D3V2KX-GP C982 19A SC2D2U6D3V2MX-GP AF13 AF15 AG13 AG15 C1019 M96 VDDR3 VDDR3 VDDR3 VDDR3 C989 SC1U6D3V2KX-GP I/O AF23 AF24 AG23 AG24 DIS SB1026 1D8V_VGA VDD_CT VDD_CT VDD_CT VDD_CT DIS SC1U6D3V2KX-GP AF26 AF27 AG26 AG27 AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 DIS SC1U6D3V2KX-GP DIS C1032 LEVEL TRANSLATION DIS C1015 POWER DIS C1031 C1018 DIS C1014 C988 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP DIS C1030 DIS SC1U6D3V2KX-GP 1D8V_VGA B VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC/BIF_VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC/BIF_VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC CORE DIS SC1U6D3V2KX-GP C995 DIS C981 1100mA G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28 SC1U6D3V2KX-GP DY PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC DIS C980 1V_VGA SC1U6D3V2KX-GP C994 PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR SC1U6D3V2KX-GP DIS DIS C970 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 SC1U6D3V2KX-GP C978 DIS C969 SCD1U16V2KX-3GP DY C986 SC1U6D3V2KX-GP DIS C968 DIS SCD1U16V2KX-3GP C1017 DIS C1013 SC1U6D3V2KX-GP DIS SC1U6D3V2KX-GP SC10U6D3V3MX-GP DIS C1012 SC1U6D3V2KX-GP 60mA C1016 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 68.00084.F81 2ND = 68.00217.701 DIS C1011 SC1U6D3V2KX-GP SC10U6D3V3MX-GP DIS DIS C977 C985 VDD_CT BLM15BD121SS1D-GP 3D3V_VGA DIS DIS SCD1U16V2KX-3GP C976 C984 SCD1U16V2KX-3GP DIS DIS C967 SCD1U16V2KX-3GP C975 DIS SC1U6D3V2KX-GP DIS C987 SC1U6D3V2KX-GP DIS C983 SC1U6D3V2KX-GP DIS C966 DY 17mA L41 C C964 SC1U6D3V2KX-GP SC10U6D3V3MX-GP 1D8V_VGA DY SC1U6D3V2KX-GP DIS C965 SC1U6D3V2KX-GP C993 C963 SC1U6D3V2KX-GP SC1U6D3V2KX-GP DIS DIS SC1U6D3V2KX-GP C962 AA31 AA32 AA33 AA34 V28 W29 W30 Y31 DY SC1U6D3V2KX-GP DY D C979 SC1U6D3V2KX-GP PCIE AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7 DIS C961 SCD1U16V2KX-3GP MEM I/O 1 DY OF VGA1E 1D5V_VGA DIS M96 71.MDSON.M01 68.00084.F81 2ND = 68.00217.701 SPV18 L43 Madison-Park50mA Madison-Park 1 C1053 C1052 Madison-Park C1051 Madison-Park Madison-Park Madison-Park Madison-Park 1 Madison-Park C1050 C1054 SCD1U16V2KX-3GP 68.00084.F81 2ND = 68.00217.701 SC1U6D3V2KX-GP C1049 SC1U6D3V2KX-GP C1048 SC10U6D3V3MX-GP C1047 SC1U6D3V2KX-GP 68.00084.F81 2ND = 68.00217.701 SC1U6D3V2KX-GP SCD1U16V2KX-3GP DIS C1046 SCD1U16V2KX-3GP DIS C1045 SC1U6D3V2KX-GP SC10U6D3V3MX-GP A DIS C1044 SC10U6D3V3MX-GP Madison-Park MPV18 L44 150mA Madison-Park BLM15BD121SS1D-GP BLM15BD121SS1D-GP 68.00084.F81 2ND = 68.00217.701 1D8V_VGA BLM15BD121SS1D-GP 2 1D8V_VGA SPV10 100mA L42 Madison-Park 1V_VGA A JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A2 Date: Madison ( of ) POWER Rev -1 JV71-MV DDR3 Madison Document Number Wednesday, October 28, 2009 Sheet 54 of 62 OF VGA1F D 110mA AN17 AP16 AP17 AW14 AW16 DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR 130mA 0R2J-2-GP AP22 AP23 DPD_VDD18 DPD_VDD18 DPB_VDD18 DPB_VDD18 DPD_VDD10 AP14 AP15 DPD_VDD10 DPD_VDD10 DPB_VDD10 DPB_VDD10 DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR 110mA DPB_VDD10 Madison-Park AN29 AP29 AP30 AW30 AW32 200mA DPE_VDD10 AL33 AM33 120mA DPB_PVDD DPB_PVSS DPE_VSSR DPE_VSSR DPE_VSSR DPE_VSSR DPC_PVDD DPC_PVSS DPA_PVDD AV29 AR28 DPB_PVDD 20mA AU18 AV17 DPC_PVDD 20mA 1 68.00084.F81 2ND = 68.00217.701 1D8V_VGA R799 0R0603-PAD DPD_PVDD DPD_PVSS MADISON-PRO-GP DIS 68.00084.F81 2ND = 68.00217.701 C1166 BLM15BD121SS1D-GP C1168 2 Madison-Park C1167 1D8V_VGA L61 DIS 20mA 1D8V_VGA L54 BLM15BD121SS1D-GP C1084 C1083 SC10U6D3V3MX-GP DPEF_CALR C1082 SC1U6D3V2KX-GP R858 0R2J-2-GP AM39 R802 150R2F-1-GP SCD1U16V2KX-3GP DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR DIS DPF_PVDD SC10U6D3V3MX-GP DIS AL38 AM35 DIS 20mA DPF_PVDD DPF_PVSS AF39 AH39 AK39 AL34 AM34 AM37 AN38 120mA DPF_VDD10 DPF_VDD10 1D8V_VGA R801 0R0603-PAD Madison-Park AK33 AK34 DPD_PVDD 20mA DPE_PVDD DPE_PVSS DPF_VDD10 20mA DPE_PVDD DPF_VDD18 DPF_VDD18 Madison-Park AF34 AG34 AV19 AR18 DPF_VDD18 R800 0R0603-PAD DPD_PVDD 200mA 1DPF_PVSS DIS SC1U6D3V2KX-GP C1072 1D8V_VGA AN34 AP39 AR39 AU37 C1078 C1071 BLM15BD121SS1D-GP DPE_VDD10 DPE_VDD10 C1070 20mA AU28 AV27 DPA_PVDD DPA_PVSS 1D8V_VGA L50 DIS DP PLL POWER DPE_VDD18 DPE_VDD18 DIS 150R2F-1-GP DP E/F POWER AH34 AJ34 2 1 2 150R2F-1-GP DIS SCD1U16V2KX-3GP AW28 R798 Madison-Park 1 2 2 DPAB_CALR SC10U6D3V3MX-GP DPCD_CALR SC1U6D3V2KX-GP 1 R796 0R0603-PAD 110mA DIS AW18 DPE_VDD18 C1081 SCD1U16V2KX-3GP SC1U6D3V2KX-GP SC10U6D3V3MX-GP C1079 DIS C1080 C1069 R797 DIS SC1U6D3V2KX-GP DIS 1D8V_VGA R861 0R2J-2-GP SCD1U16V2KX-3GP DIS C1077 DIS 68.00214.091 2ND = 68.00206.341 DIS SCD1U16V2KX-3GP L53 HCB1608KF-1-GP SC10U6D3V3MX-GP 1V_VGA DIS C1075 SCD1U16V2KX-3GP DIS DIS C1074 SC1U6D3V2KX-GP SC10U6D3V3MX-GP L52 BLM15BD121SS1D-GP C1076 DIS C1068 SC1U6D3V2KX-GP DIS C1073 68.00214.091 2ND = 68.00206.341 B DIS SCD1U16V2KX-3GP SC10U6D3V3MX-GP C1067 L51 68.00084.F81 2ND = 68.00217.701 DIS 2 HCB1608KF-1-GP 1D8V_VGA 68.00214.091 2ND = 68.00206.341 130mA AN33 AP33 DIS 68.00084.F81 2ND = 68.00217.701 DIS DIS DPE_VDD18 L49 BLM15BD121SS1D-GP 1V_VGA C1060 PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS 1V_VGA AN19 AP18 AP19 AW20 AW22 DIS HCB1608KF-1-GP DPB_VDD18 AP25 AP26 1V_VGA R795 0R0603-PAD 1D8V_VGA C1057 1V_VGA L46 DIS Madison-Park C DPD_VDD18 C1056 68.00084.F81 2ND = 68.00217.701 DIS R859 DIS 110mA AN27 AP27 AP28 AW24 AW26 Madison-Park 1D8V_VGA DIS DPA_VDD10 AP31 AP32 AP13 AT13 DPC_VDD10 R794 0R0603-PAD Madison-Park SC10U6D3V3MX-GP DPA_VDD10 DPA_VDD10 1V_VGA SC1U6D3V2KX-GP DPC_VDD10 DPC_VDD10 AN24 AP24 SCD1U16V2KX-3GP DPA_VDD18 DPA_VDD18 DP A/B POWER DPC_VDD18 DPC_VDD18 Madison-Park DPC_VDD18 AP20 AP21 0R2J-2-GP 1D8V_VGA L45 BLM15BD121SS1D-GP C1055 SC10U6D3V3MX-GP DP C/D POWER R860 C1059 SC1U6D3V2KX-GP 130mA OF VGA1H C1058 SCD1U16V2KX-3GP 130mA 1D8V_VGA Madison-Park Madison-Park Madison-Park DPA_VDD18 AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39 DIS 68.00084.F81 2ND = 68.00217.701 71.MDSON.M01 CO-LAYOUT F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND MADISON-PRO-GP A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/PX_EN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS_MECH VSS_MECH VSS_MECH D A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13 A39 AW1 AW39 C B VSS_MECH1 VSS_MECH2 VSS_MECH3 1 TP255 TPAD14-GP TP256 TPAD14-GP TP257 TPAD14-GP DIS A 71.MDSON.M01 JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Madison ( of ) DP POWER Size A2 Date: Document Number Rev -1 JV71-MV DDR3 Madison Wednesday, October 28, 2009 Sheet 55 of 62 1D5V_VGA 243R2F-2-GP 243R2F-2-GP 243R2F-2-GP Park-M96 Madison Madison MBM_CALRN0 L27 2 R809 MBM_CALRN1 N12 R810 MBM_CALRN2AG12 R812 MBM_CALRP1 M12 2 R813 MBM_CALRP0 M27 R814 MBM_CALRP2AH12 R816 CSA1#_0 CSA1#_1 MVREFDA MVREFSA CKEA0 CKEA1 MEM_CALRN0 MEM_CALRN1 MEM_CALRN2 WEA0# WEA1# MEM_CALRP1 MEM_CALRP0 MEM_CALRP2 MAA0_8 MAA1_8 CLKA1 CLKA1# K23 K19 RASA0# RASA1# K20 K17 CASA0# CASA1# K24 K27 CSA0#_0 M13 K16 CSA1#_0 K21 J20 57 57 CLKA1 CLKA1# 58 58 RASA0# RASA1# 57 58 CASA0# CASA1# 57 58 CSA0#_0 57 CSA1#_0 58 MVREF TO PWR 40.2R 40.2R 40.2R MVREF TO GND 100R 100R 100R 57,58 1D5V_VGA DIS 1D5V_VGA CKEA0 CKEA1 K26 L15 WEA0# WEA1# H23 J19 MAA13_R R856 CKEA0 CKEA1 57 58 WEA0# WEA1# 57 58 R804 40D2R2F-GP DIS R807 100R2F-L1-GP-U R808 40D2R2F-GP MAA13 57,58 0R2J-2-GP Madison R817 100R2F-L1-GP-U C1090 3D3V_VGA DIS DIS Y12 AA12 DDBIB0_0/QSB_0#/WDQSB_0 DDBIB0_1/QSB_1#/WDQSB_1 DDBIB0_2/QSB_2#/WDQSB_2 DDBIB0_3/QSB_3#/WDQSB_3 DDBIB1_0/QSB_4#/WDQSB_4 DDBIB1_1/QSB_5#/WDQSB_5 DDBIB1_2/QSB_6#/WDQSB_6 DDBIB1_3/QSB_7#/WDQSB_7 ADBIB0/ODTB0 ADBIB1/ODTB1 CLKB0 CLKB0# CLKB1 CLKB1# RASB0# RASB1# CASB0# CASB1# CSB0#_0 CSB0#_1 CSB1#_0 CSB1#_1 CKEB0 CKEB1 MVREFDB MVREFSB WEB0# WEB1# TESTEN R815 ATI-MP-M96 AD28 TESTEN CLKTESTA AK10 CLKTESTB AL10 10KR2F-2-GP R615 R616 M96 4K7R2F-GP DIS MVREFDB MVREFSB 4K7R2F-GP MADISON-PRO-GP R900 ATI-ES 1KR2J-1-GP CO-LAYOUT Madison: MEM_CALRP[0,2] signals are used Park: MEM_CALRP1 and MEM_CALRN1 are used C1087 DIS DIS SCD1U16V2KX-3GP 243R2F-2-GP 243R2F-2-GP 243R2F-2-GP Madison Park1 Madison CSA0#_0 CSA0#_1 J14 H14 CLKA0 CLKA0# DDR3 MAB0_8 MAB1_8 CLKTESTA CLKTESTB DRAM_RST# DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 F6 K3 P3 V5 AB5 AH1 AJ9 AM5 RDQSB0 RDQSB1 RDQSB2 RDQSB3 RDQSB4 RDQSB5 RDQSB6 RDQSB7 G7 K1 P1 W4 AC4 AH3 AJ8 AM3 WDQSB0 WDQSB1 WDQSB2 WDQSB3 WDQSB4 WDQSB5 WDQSB6 WDQSB7 T7 W7 ODTB0 ODTB1 L9 L8 CLKB0 CLKB0# AD8 AD7 CLKB1 CLKB1# T10 Y10 RASB0# RASB1# W10 AA10 CASB0# CASB1# P10 L10 CSB0#_0 AD10 AC10 CSB1#_0 U10 AA11 CKEB0 CKEB1 N10 AB11 WEB0# WEB1# T8 W8 MAB13_R MADISON-PRO-GP DIS 3D3V_VGA H2SYNC, GENERICC, GPIO2, GPIO21 DIS 53 GPIO_VGA_00 X GPIO1 (Internal PD) RESERVED BIF_VGA_DIS RESERVED BIOS_ROM_EN GPIO8 GPIO9 GPIO21 GPIO22_ROMCSB Transmitter De-emphasis Enable 0= Tx de-emphasis disabled 1= Tx de-emphasis enabled X If BIOS_ROM_EN (GPIO22) = Size of the primary GPIO[13,12,11] Manufacturer memory apertures 53 GPIO_VGA_01 R821 53 GPIO_VGA_02 R822 53 GPIO_VGA_05 R823 DIS RESERVED VGA ENABLED 0 RESERVED V 128MB 256MB 64MB 32MB 512MB 1GB 2GB 4GB x000 x001 x010 x x x x x ST Microelectronics 0100 0101 0101 0101 0101 53 GPIO_VGA_08 53 GPIO_VGA_09 Chingis (formerly PMC) Pm25LV512A Pm25LV010A 0100 0101 53 GPIO_VGA_11 53 GPIO_VGA_22 ENABLE EXTERNAL BIOS ROM M25P05A M25P10A M25P20 M25P40 M25P80 59 60 WEB0# WEB1# 59 60 C MAB13 59,60 0R2J-2-GP 2 VRAM_RST Madison-Park C1091 57,58,59,60 C81 M96 B 10KR2J-3-GP Madison-Park Part Number GPIO[13,12,11] 60 CKEB0 CKEB1 59,60 10KR2J-3-GP DIS If BIOS_ROM_EN (GPIO22) = TX_DEEMPH_EN R820 59 CSB1#_0 WDQSB[0 7] SC1KP50V2KX-1GP (Internal PD) Tansmitter Power Savings Enable 0= 50% Tx output swing 1= Full Tx output swing CSB0#_0 SC68P50V2JN-1GP GPIO0 59 60 Madison-Park TX_PWRS_ENB HW STRAP PIN ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET 10KR2F-2-GP PCIE FULL TX OUTPUT SWING B need check M9x schematic AMD RESERVED CONFIGURATION STRAPS RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE 59 60 CASB0# CASB1# Madison-Park R819 4K7R2J-2-GP DESCRIPTION 60 60 RASB0# RASB1# 59,60 M96 M96 PIN CLKB1 CLKB1# RDQSB[0 7] R863 0R2J-2-GP R818 680R2F-GP 71.MDSON.M01 R82 STRAPS 59 59 59,60 R81 4K7R2J-2-GP SB 1008 71.MDSON.M01 59 60 CLKB0 CLKB0# DQMB#[0 7] Madison-Park M96 M96 ODTB0 ODTB1 R857 1D5V_VGA AH11 D 59,60 59,60 59,60 1 C1089 L18 L20 CASA0# CASA1# CLKA0 CLKA0# 57 58 2 DIS 2 DIS C1088 SCD1U16V2KX-3GP R811 100R2F-L1-GP-U SCD01U16V2KX-3GP DIS MVREFDA MVREFSA RASA0# RASA1# H27 G27 WDQSA[0 7] ODTA0 ODTA1 1.8/1.5V 1.5V H3 H1 T3 T5 AE4 AF5 AK6 AK5 2 R806 40D2R2F-GP DIS CLKA1 CLKA1# ODTA0 ODTA1 GDDR3 1.5V BB2 BB0 BB1 DIS DIS C1086 SCD1U16V2KX-3GP DIS SCD01U16V2KX-3GP R805 100R2F-L1-GP-U 1D5V_VGA C1085 C DIS CLKA0 CLKA0# J21 G19 GDDR5 MVREF 59,60 SB 0812 BB2 BB0 BB1 R803 40D2R2F-GP ADBIA0/ODTA0 ADBIA1/ODTA1 DIVIDER RESISTORS MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 1 1D5V_VGA 57,58 WCKB0_0/DQMB_0 WCKB0#_0/DQMB_1 WCKB0_1/DQMB_2 WCKB0#_1/DQMB_3 WCKB1_0/DQMB_4 WCKB1#_0/DQMB_5 WCKB1_1/DQMB_6 WCKB1#_1/DQMB_7 GDDR5/DDR2/GDDR3 EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7 MAB[0 12] P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9 100R RDQSA[0 7] MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1 GDDR5 100R WDQSA0 WDQSA1 WDQSA2 WDQSA3 WDQSA4 WDQSA5 WDQSA6 WDQSA7 DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63 100R A34 E30 E26 C20 C16 C12 J11 F8 For SSTL-1.8/SSTL-2/DDR1/GDDR1: 0.5 * VDDR1 For DDR3/GDDR3/GDDR4/GDDR5: 0.7 * VDDR1 C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 MVREF TO GND DDBIA0_0/QSA_0#/WDQSA_0 DDBIA0_1/QSA_1#/WDQSA_1 DDBIA0_2/QSA_2#/WDQSA_2 DDBIA0_3/QSA_3#/WDQSA_3 DDBIA1_0/QSA_4#/WDQSA_4 DDBIA1_1/QSA_5#/WDQSA_5 DDBIA1_2/QSA_6#/WDQSA_6 DDBIA1_3/QSA_7#/WDQSA_7 40 40.2R For Madison 100 40.2R For M96-M2 R804/R808 1.8/1.5V 1.5V 40.2R 57,58 1.5V MVREF TO PWR Designator DQMA#[0 7] MVREF RDQSA0 RDQSA1 RDQSA2 RDQSA3 RDQSA4 RDQSA5 RDQSA6 RDQSA7 DDR3 C34 D29 D25 E20 E16 E12 J10 D7 GDDR3 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 GDDR5 A32 C32 D23 E22 C14 A14 E10 D9 MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 57,58 57,58 57,58 DIVIDER RESISTORS BA2 BA0 BA1 OF DDR2 GDDR5/GDDR3 DDR3 VGA1D DDR2 GDDR3/GDDR5 DDR3 For SSTL-1.8/SSTL-2/DDR1/GDDR1: 0.5 * VDDR1 For DDR3/GDDR3/GDDR4/GDDR5: 0.7 * VDDR1 BA2 BA0 BA1 59,60 MDB[0 63] 40 57,58 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 For Madison 100 WCKA0_0/DQMA_0 WCKA0#_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0#_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1#_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1#_1/DQMA_7 GDDR5/DDR2/GDDR3 EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7 MAA[0 12] G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17 For M96-M2 R803/R806 MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0 MAA1_7/MAA_A15_BA1 Designator DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63 GDDR5 D C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5 SCD1U16V2KX-3GP MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 MEMORY INTERFACE A 57,58 MDA[0 63] 3 OF DDR2 GDDR5/GDDR3 DDR3 MEMORY INTERFACE B VGA1C DDR2 GDDR3/GDDR5 DDR3 10KR2J-3-GP 10KR2J-3-GP DY R824 R825 R826 R827 R828 10KR2J-3-GP R829 10KR2J-3-GP DY DIS 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP DY 10KR2J-3-GP SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT VIP_DEVICE_STRAP_ENA GPIO[13,12,11] (Internal PD) A X X X if BIOS_ROM_EN=1,then Config[3:0] defines the ROM type if BIOS_ROM_EN=0,then Config[3:0] defines the primary memory apeture size 19,53 CRT_VSYNC RSVD V2SYNC RSVD H2SYNC AUD[1] AUD[0] VGA_HSYNC VGA_VSYNC (Internal PD) 19,53 CRT_HSYNC AUD[1:0] 00:No audio function 01:Audio for DisplayPort and HDMI ( if adapter is detected) 10:Audio for DisplayPort only 11:Audio for both DisplayPort and HDMI 53 GPIO_VGA_12 53 GPIO_VGA_13 DIS DIS R830 R831 10KR2J-3-GP DY 10KR2J-3-GP DY A X X JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Madison ( of ) MEMORY/ST Size A2 Date: Document Number Rev JV71-MV DDR3 Madison Wednesday, October 28, 2009 Sheet 56 -1 of 62 DDR3 1 2 2 2 Madison-M96 DIS C DIS C1172 C1171 2 Madison-M96 C1066 Madison-M96 2 Madison-M96 Madison-M96 C1173 Madison-M96 1 Madison-M96 2 2 Madison-M96 2 Madison-M96 2 Madison-M96 Madison-M96 2 2 2 Madison-M96 DIS C1111 C1118 Madison-M96 72.41164.H0U C1117 C1169 Madison-M96 Madison-M96 72.41164.H0U C1122 Madison-M96 Madison-M96 DIS C1121 Madison-M96 K4W 1G1646E-HC12-GP 1 Madison-M96 K4W 1G1646E-HC12-GP DIS C1120 WE# CAS# RAS# C1119 DIS C1110 SCD1U10V2KX-5GP L3 K3 J3 G1 F9 E8 E2 D8 D1 B9 B1 G9 C1116 DIS C1109 SC1U6D3V2KX-GP W EA0# CASA0# RASA0# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DIS C1115 C1108 DIS SC10U6D3V3MX-GP DMU DML DIS C1114 DIS C1107 DIS C1101 SCD1U10V2KX-5GP CKE D3 E7 C1113 DIS C1106 C1100 SC1U6D3V2KX-GP W EA0# CASA0# RASA0# K9 DQMA#0 DQMA#1 C1112 DIS C1105 SC10U6D3V3MX-GP 56 56 56 CK CK# 56,58,59,60 C1104 SCD1U10V2KX-5GP DQMA#0 DQMA#1 J7 K7 CKEA0 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VRAM_RST C1103 SC10U6D3V3MX-GP 56 56 CLKA0 CLKA0# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C1102 DIS SC1U6D3V2KX-GP CKEA0 BA0 BA1 BA2 T7 L9 L1 J9 J1 56 C1099 SCD1U10V2KX-5GP 56 CLKA0 CLKA0# M2 N8 M3 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 CSA0#_0 SCD1U10V2KX-5GP 56 56 BA0 BA1 BA2 CSA0#_0 56 SC1U6D3V2KX-GP 56,58 56,58 56,58 BA0 BA1 BA2 L2 T2 56 56 ODTA0 SC10U6D3V3MX-GP G1 F9 E8 E2 D8 D1 B9 B1 G9 MAA13 CS# RESET# RDQSA1 W DQSA1 SCD1U10V2KX-5GP VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ CKE 56,58 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 ODTA0 SCD1U10V2KX-5GP J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 56,58,59,60 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 K1 C1098 SC1U6D3V2KX-GP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VRAM_RST MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 ODT DIS SC1U6D3V2KX-GP B T7 L9 L1 J9 J1 56 RDQSA1 W DQSA1 DIS C1097 SCD1U10V2KX-5GP WE# CAS# RAS# NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 CSA0#_0 F3 G3 56 56 C1096 SCD1U10V2KX-5GP L3 K3 J3 CSA0#_0 Madison-M96 DQSL DQSL# RDQSA0 W DQSA0 C1095 SC1U6D3V2KX-GP W EA0# CASA0# RASA0# L2 T2 56 RDQSA0 W DQSA0 C1094 SC1U6D3V2KX-GP DMU DML CS# RESET# ODTA0 1MAA_ZQ1 243R2F-2-GP C7 B7 C1093 SCD1U10V2KX-5GP W EA0# CASA0# RASA0# D3 E7 ODTA0 DQSU DQSU# C1092 SC1U6D3V2KX-GP 56 56 56 K9 DQMA#3 DQMA#2 K1 56 56 VREFDQ VREFCA ZQ 2.16A 1D5V_VGA MDA0~7 SC1U6D3V2KX-GP DQMA#3 DQMA#2 CK CK# ODT RDQSA2 W DQSA2 H1 M8 L8 MDA4 MDA0 MDA7 MDA3 MDA5 MDA1 MDA6 MDA2 SC1U6D3V2KX-GP 56 56 J7 K7 CKEA0 RDQSA2 W DQSA2 MAA_VREF12 R833 D7 C3 C8 C2 A7 A2 B8 A3 SCD1U10V2KX-5GP CKEA0 CLKA0 CLKA0# F3 G3 56 56 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 SCD1U10V2KX-5GP 56 BA0 BA1 BA2 DQSL DQSL# RDQSA3 W DQSA3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ D SCD1U10V2KX-5GP CLKA0 CLKA0# M2 N8 M3 RDQSA3 W DQSA3 A8 A1 C1 C9 D2 E9 F1 H9 H2 MDA8~15 SCD1U10V2KX-5GP 56 56 BA0 BA1 BA2 BA0 BA1 BA2 C7 B7 MDA24~31 MDA11 MDA14 MDA8 MDA12 MDA9 MDA13 MDA10 MDA15 SCD1U10V2KX-5GP 56,58 56,58 56,58 MAA13 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 DQSU DQSU# 1D5V_VGA E3 F7 F2 F8 H3 H8 G2 H7 SCD1U10V2KX-5GP 56,58 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 MDA27 MDA28 MDA30 MDA24 MDA25 MDA31 MDA26 MDA29 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 SCD1U10V2KX-5GP C MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 D7 C3 C8 C2 A7 A2 B8 A3 VDD VDD VDD VDD VDD VDD VDD VDD VDD SC1U6D3V2KX-GP Madison-M96 VREFDQ VREFCA ZQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 MDA16~23 K8 K2 N1 R9 B2 D9 G7 R1 N9 SC1U6D3V2KX-GP MAA_ZQ0 243R2F-2-GP H1 M8 L8 MDA19 MDA18 MDA23 MDA22 MDA16 MDA20 MDA21 MDA17 SC1U6D3V2KX-GP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 SC1U6D3V2KX-GP MAA_VREF12 R832 A8 A1 C1 C9 D2 E9 F1 H9 H2 FBRAM2 1D5V_VGA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 Madison-M96 1D5V_VGA VDD VDD VDD VDD VDD VDD VDD VDD VDD K8 K2 N1 R9 B2 D9 G7 R1 N9 D SB 0818 FBRAM1 1D5V_VGA DIS B CLKA0# R836 1K05R2F-GP MAA_VREF12 Madison-M96 R837 1K05R2F-GP Madison-M96 Madison-M96 C1124 SCD01U50V2KX-1GP C1123 SCD01U50V2KX-1GP Madison-M96 2 56,58 RDQSA[0 7] 56R2F-1-GP 56R2F-1-GP HYUNIX 1ST=72.51G63.C0U SAMSUNG 2ND=72.41164.H0U AMD 3RD=VR.1GB0T.002 56,58 DQMA#[0 7] 1D5V_VGA Madison-M96 Madison-M96 R835 1 CLKA0 R834 56,58 W DQSA[0 7] A 56,58 A JV71-MV DDR3 Madison MAA[0 12] MAA[0 12] Wistron Corporation MDA[0 63] 56,58 MDA[0 63] 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM( of ) Size A3 Date: Document Number Rev -1 JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 57 of 62 DDR3 R839 H1 M8 L8 1MAA_ZQ2 Madison-M96 C 56,57 243R2F-2-GP MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA13 56,57 56,57 56,57 BA0 BA1 BA2 56 CKEA1 56 56 DQMA#4 DQMA#5 56 56 56 W EA1# CASA1# RASA1# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 M2 N8 M3 BA0 BA1 BA2 CLKA1 CLKA1# J7 K7 CK CK# CKEA1 K9 CKE DQMA#4 DQMA#5 D3 E7 DMU DML W EA1# CASA1# RASA1# L3 K3 J3 WE# CAS# RAS# DQSU DQSU# C7 B7 DQSL DQSL# F3 G3 ODT K1 CS# RESET# L2 T2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ RDQSA4 W DQSA4 RDQSA5 W DQSA5 ODTA1 CSA1#_0 MDA32~39 RDQSA4 W DQSA4 56 56 RDQSA5 W DQSA5 56 56 ODTA1 56 CSA1#_0 56 VRAM_RST 56,57,59,60 G1 F9 E8 E2 D8 D1 B9 B1 G9 MAA_VREF34 R838 1MAA_ZQ3 243R2F-2-GP Madison-M96 56,57 MAA13 56,57 56,57 56,57 BA0 BA1 BA2 56 56 CLKA1 CLKA1# 56 CKEA1 56 56 DQMA#7 DQMA#6 56 56 56 W EA1# CASA1# RASA1# A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BA0 BA1 BA2 M2 N8 M3 BA0 BA1 BA2 CLKA1 CLKA1# J7 K7 CK CK# CKEA1 K9 CKE DQMA#7 DQMA#6 D3 E7 DMU DML W EA1# CASA1# RASA1# L3 K3 J3 WE# CAS# RAS# MDA55 MDA51 MDA53 MDA48 MDA52 MDA50 MDA54 MDA49 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA61 MDA62 MDA58 MDA56 MDA60 MDA59 MDA57 MDA63 DQSU DQSU# C7 B7 RDQSA7 W DQSA7 DQSL DQSL# F3 G3 RDQSA6 W DQSA6 ODT K1 ODTA1 CS# RESET# L2 T2 CSA1#_0 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 MDA48~55 D MDA56~63 56 56 RDQSA6 W DQSA6 56 56 ODTA1 56 CSA1#_0 56 VRAM_RST 56,57,59,60 C CLKA1# CLKA1 R840 Madison-M96 Madison-M96 K4W 1G1646E-HC12-GP B RDQSA7 W DQSA7 R841 56R2F-1-GP CLKA1 CLKA1# N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 MDA36 MDA35 MDA39 MDA33 MDA37 MDA32 MDA38 MDA34 E3 F7 F2 F8 H3 H8 G2 H7 56R2F-1-GP 56 56 BA0 BA1 BA2 VREFDQ VREFCA ZQ D7 C3 C8 C2 A7 A2 B8 A3 1D5V_VGA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 MAA_VREF34 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 MDA40~47 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 E3 F7 F2 F8 H3 H8 G2 H7 Madison-M96 1D5V_VGA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 K8 K2 N1 R9 B2 D9 G7 R1 N9 D VDD VDD VDD VDD VDD VDD VDD VDD VDD MDA43 MDA44 MDA42 MDA46 MDA40 MDA47 MDA41 MDA45 K8 K2 N1 R9 B2 D9 G7 R1 N9 FBRAM4 1D5V_VGA FBRAM3 1D5V_VGA K4W 1G1646E-HC12-GP C1125 SCD01U50V2KX-1GP B Madison-M96 Madison-M96 72.41164.H0U 72.41164.H0U 1D5V_VGA R842 1K05R2F-GP 1 MAA_VREF34 R843 1K05R2F-GP Madison-M96 Madison-M96 C1126 SCD01U50V2KX-1GP 56,57 RDQSA[0 7] HYUNIX 1ST=72.51G63.C0U SAMSUNG 2ND=72.41164.H0U AMD 3RD=VR.1GB0T.002 56,57 DQMA#[0 7] Madison-M96 56,57 W DQSA[0 7] 56,57 MAA[0 12] MAA[0 12] A A JV71-MV DDR3 Madison 56,57 MDA[0 63] MDA[0 63] Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM( fo ) Size A3 Date: Document Number Rev -1 JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 58 of 62 DDR3 DIS C 56,60 MAB13 56,60 56,60 56,60 BB0 BB1 BB2 56 CKEB0 56 56 DQMB#3 DQMB#2 56 56 56 W EB0# CASB0# RASB0# MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BB0 BB1 BB2 M2 N8 M3 BA0 BA1 BA2 CLKB0 CLKB0# J7 K7 CK CK# CKEB0 K9 CKE DQMB#3 DQMB#2 D3 E7 DMU DML W EB0# CASB0# RASB0# L3 K3 J3 WE# CAS# RAS# B MDB30 MDB27 MDB25 MDB28 MDB24 MDB31 MDB29 MDB26 DQSU DQSU# C7 B7 1D5V_VGA MDA24~31 RDQSB3 W DQSB3 DQSL DQSL# F3 G3 RDQSB2 W DQSB2 ODT K1 ODTB0 CS# RESET# L2 T2 CSB0#_0 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 RDQSB3 W DQSB3 56 56 RDQSB2 W DQSB2 56 56 ODTB0 56 CSB0#_0 56 VRAM_RST MAB_VREF12 R845 1MAB_ZQ1 243R2F-2-GP DIS 56,57,58,60 56,60 MAB13 56,60 56,60 56,60 BB0 BB1 BB2 56 56 CLKB0 CLKB0# 56 CKEB0 56 56 DQMB#0 DQMB#1 56 56 56 W EB0# CASB0# RASB0# A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BB0 BB1 BB2 M2 N8 M3 BA0 BA1 BA2 CLKB0 CLKB0# J7 K7 CK CK# CKEB0 K9 CKE DQMB#0 DQMB#1 D3 E7 DMU DML W EB0# CASB0# RASB0# L3 K3 J3 WE# CAS# RAS# DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDB11 MDB14 MDB8 MDB10 MDB15 MDB13 MDB9 MDB12 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB4 MDB3 MDB7 MDB0 MDB5 MDB1 MDB6 MDB2 DQSU DQSU# C7 B7 RDQSB0 W DQSB0 DQSL DQSL# F3 G3 RDQSB1 W DQSB1 ODT K1 ODTB0 CS# RESET# L2 T2 CSB0#_0 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP 72.41164.H0U 72.41164.H0U DIS DIS MDA8~15 D MDA0~7 RDQSB0 W DQSB0 56 56 RDQSB1 W DQSB1 56 56 ODTB0 56 CSB0#_0 56 VRAM_RST 56,57,58,60 C CLKB0# CLKB0 R846 DIS R847 56R2F-1-GP CLKB0 CLKB0# VREFDQ VREFCA ZQ D7 C3 C8 C2 A7 A2 B8 A3 VDD VDD VDD VDD VDD VDD VDD VDD VDD 56R2F-1-GP 56 56 H1 M8 L8 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 MDA16~23 K8 K2 N1 R9 B2 D9 G7 R1 N9 R844 1MAB_ZQ0 243R2F-2-GP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ MDB21 MDB20 MDB22 MDB16 MDB19 MDB17 MDB23 MDB18 DIS MAB_VREF12 A8 A1 C1 C9 D2 E9 F1 H9 H2 E3 F7 F2 F8 H3 H8 G2 H7 1D5V_VGA FBRAM6 1D5V_VGA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 D VDD VDD VDD VDD VDD VDD VDD VDD VDD K8 K2 N1 R9 B2 D9 G7 R1 N9 FBRAM5 1D5V_VGA C1127 SCD01U50V2KX-1GP B DIS 1D5V_VGA R848 1K05R2F-GP HYUNIX 1ST=72.51G63.C0U SAMSUNG 2ND=72.41164.H0U AMD 3RD=VR.1GB0T.002 DIS R849 1K05R2F-GP 56,60 RDQSB[0 7] MAB_VREF12 56,60 DQMB#[0 7] DIS 56,60 MAB[0 12] DIS 56,60 W DQSB[0 7] C1128 SCD01U50V2KX-1GP MAB[0 12] JV71-MV DDR3 Madison A A MDB[0 63] 56,60 MDB[0 63] Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM( of ) Size A3 Date: Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 59 -1 of 62 DDR3 MAB_VREF34 R850 1MAB_ZQ2 243R2F-2-GP DIS C 56,59 MAB13 56,59 56,59 56,59 BB0 BB1 BB2 56 56 CLKB1 CLKB1# 56 CKEB1 W EB1# CASB1# RASB1# VREFDQ VREFCA ZQ MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BB0 BB1 BB2 M2 N8 M3 BA0 BA1 BA2 CLKB1 CLKB1# J7 K7 CK CK# CKEB1 K9 DQMB#4 DQMB#5 D3 E7 DMU DML W EB1# CASB1# RASB1# L3 K3 J3 WE# CAS# RAS# D7 C3 C8 C2 A7 A2 B8 A3 MDB37 MDB35 MDB34 MDB39 MDB38 MDB32 MDB36 MDB33 DQSU DQSU# C7 B7 MDA32~39 RDQSB4 W DQSB4 DQSL DQSL# F3 G3 RDQSB5 W DQSB5 ODT K1 ODTB1 CS# RESET# L2 T2 CSB1#_0 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 CKE 1D5V_VGA RDQSB4 W DQSB4 56 56 MAB_VREF34 R851 RDQSB5 W DQSB5 56 56 ODTB1 56 CSB1#_0 56 VRAM_RST 56,57,58,59 1MAB_ZQ3 243R2F-2-GP DIS 56,59 MAB13 56,59 56,59 56,59 BB0 BB1 BB2 56 56 CLKB1 CLKB1# 56 CKEB1 56 56 DQMB#7 DQMB#6 56 56 56 W EB1# CASB1# RASB1# VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7 BB0 BB1 BB2 M2 N8 M3 BA0 BA1 BA2 CLKB1 CLKB1# J7 K7 CK CK# CKEB1 K9 CKE DQMB#7 DQMB#6 D3 E7 DMU DML W EB1# CASB1# RASB1# L3 K3 J3 WE# CAS# RAS# DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDB52 MDB50 MDB48 MDB49 MDB53 MDB54 MDB51 MDB55 MDA48~55 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB61 MDB59 MDB63 MDB56 MDB60 MDB58 MDB62 MDB57 MDA56~63 DQSU DQSU# C7 B7 RDQSB7 W DQSB7 DQSL DQSL# F3 G3 RDQSB6 W DQSB6 ODT K1 ODTB1 CS# RESET# L2 T2 CSB1#_0 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 D RDQSB7 W DQSB7 56 56 RDQSB6 W DQSB6 56 56 ODTB1 56 CSB1#_0 56 VRAM_RST 56,57,58,59 C CLKB1# CLKB1 R852 DIS R853 DIS 56 56 56 H1 M8 L8 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 MDA40~47 K8 K2 N1 R9 B2 D9 G7 R1 N9 56R2F-1-GP DQMB#4 DQMB#5 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ MDB42 MDB41 MDB46 MDB43 MDB44 MDB40 MDB47 MDB45 56R2F-1-GP 56 56 A8 A1 C1 C9 D2 E9 F1 H9 H2 E3 F7 F2 F8 H3 H8 G2 H7 1D5V_VGA FBRAM8 1D5V_VGA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 D VDD VDD VDD VDD VDD VDD VDD VDD VDD K8 K2 N1 R9 B2 D9 G7 R1 N9 FBRAM7 1D5V_VGA K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP 72.41164.H0U 72.41164.H0U DIS DIS B B C1129 SCD01U50V2KX-1GP DIS 1D5V_VGA R854 1K05R2F-GP HYUNIX 1ST=72.51G63.C0U SAMSUNG 2ND=72.41164.H0U AMD 3RD=VR.1GB0T.002 DIS MAB_VREF34 56,59 DQMB#[0 7] R855 1K05R2F-GP 56,59 RDQSB[0 7] DIS 56,59 MAB[0 12] DIS 56,59 W DQSB[0 7] C1130 SCD01U50V2KX-1GP MAB[0 12] JV71-MV DDR3 Madison A A MDB[0 63] 56,59 MDB[0 63] Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM( of ) Size A3 Date: Document Number Rev JV71-MV DDR3 Madison W ednesday, October 28, 2009 Sheet 60 of -1 62 SA SB SC -1 D D C C B B A A JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title HISTORY Size A2 Date: Document Number Rev -1 JV71-MV DDR3 Madison Wednesday, October 28, 2009 Sheet 61 of 62 Group Name D SKU A SKU B SKU C SKU D DY,ZZ,65 X X X X GFX X X X O NOGFX X X X X DIS O O O X M96 O X X X Madison X O X X Madison-M96 O O X X Madison-Park X O O X Park X X O X Park-M96 O X O X UMA X X X O Hynix X O O X Hynix-AMD X O O X Hynix-Samsung-AMD O O O X Samsung O X X X Samsung-AMD O X X X ATI-ES X O O X ATI-MP-M96 O X X X C Part Name SKU A PM45 M96 Samsung SKU B PM45 Madison Hynix SKU C PM45 Park Hynix SKU D GM45 UMA KI.G4501.002 KI.G4501.002 KI.G4501.002 KI.G4501.001 LAB-Stage BOM temporary change list SKU-A,B Delete R428 64.15035.6DL Delete Q27 NB NB1 84.27002.W31 SB SB1 KI.80101.030 KI.80101.030 KI.80101.030 KI.80101.030 Delete R436 63.10334.1DL VGA VGA1 71.M96M2.M03 71.MDSON.M01 71.0PARK.M04 X Delete C741 78.10423.5FL VRAM FBRAM1~4 VR.1GB0B.006 VR.1GB0G.004 X X Change R429 from 64.75025.6DL to 64.49925.6DL VRAM FBRAM5~8 VR.1GB0B.006 VR.1GB0G.004 VR.1GB0G.004 X R885 64.78715.6DL X X X R887 64.20525.6DL X X X VGA_CORE R428 64.30025.6DL 64.73225.6DL 64.49925.6DL X RGB X X X 78.6R874.1FL D SKU-C Delete R428 64.15035.6DL 1v_VGA/1.1v_VGA C165,151,108 Delete Q27 84.27002.W31 Delete R436 63.10334.1DL Delete C741 78.10423.5FL Change R429 from 64.75025.6DL to 64.37425.6DL TVDAC RN31 X X X 66.75036.08L CRT RN30 X X X 66.15156.08L SKU-B change for Power-Team 2nd source Change U73 from 84.08692.037 to 84.01426.037 TRANSFORMER XF1~2 68.HD081.30B 68.HD081.30B 68.HD081.30B 68.HD081.30B Change U75 from 84.07672.037 to 84.01712.037 MVREFDA R803 64.10005.6DL X X X Change U76 from 84.07672.037 to 84.01712.037 MVREFSA R806 64.10005.6DL X X X MVREFDB R804 64.10005.6DL X X X MVREFSB R808 64.10005.6DL X X X DCIN1 22.10037.I21 22.10037.I21 X X 65.4FXZZ.024 65.4FXZZ.024 65.4FXZZ.024 65.4FXZZ.032 Change U17 from 84.07672.037 to 84.01712.037 65.4FXZZ.026 65.4FXZZ.026 65.4FXZZ.026 65.4FXZZ.026 Change U40 from 84.07672.037 to 84.01712.037 Change U77 from 84.08692.037 to 84.01426.037 C Change U79 from 84.07672.037 to 84.01712.037 65 Main 65 2nd 90W/65W 65.4FXZZ.024 65.4FXZZ.025 65BOM 65.4FXZZ.026 65.4FXZZ.027 65.4FXZZ.028 65.4FXZZ.029 65.4FXZZ.032 65.4FXZZ.033 Change U41 from 84.08692.037 to 84.01426.037 65.4FXZZ.028 Change TC35 from 79.33719.L01 to 77.C3371.051 Change TC36 from 79.33719.L01 to 77.C3371.051 Change TC38 from 79.33719.L01 to 77.C3371.051 SKU E SKU F SKU G DY,ZZ,65 X X X GFX X X X NOGFX X X X DIS O O O M96 O X X Madison X O X Madison-M96 O O X Madison-Park X O O Park X X O Park-M96 O X O UMA X X X Hynix O X X Hynix-AMD O X X Hynix-Samsung-AMD O O O Samsung X O O Samsung-AMD X O O ATI-ES X O O ATI-MP-M96 O X X Group Name B A SKU F PM45 Madison Samsung SKU G PM45 Park Samsung Change TC14 from 79.33719.L01 to 77.C3371.051 Part Name SKU E PM45 M96 Hynix NB NB1 KI.G4501.002 KI.G4501.002 KI.G4501.002 Change L58 from 68.R5610.10P to 68.R5610.10D SB SB1 KI.80101.030 KI.80101.030 KI.80101.030 Change L59 from 68.1R01B.10J to 68.1R01A.20A VGA VGA1 71.M96M2.M03 71.MDSON.M01 71.0PARK.M04 VRAM FBRAM1~4 VR.1GB0G.004 VR.1GB0B.006 X VRAM FBRAM5~8 VR.1GB0G.004 VR.1GB0B.006 VR.1GB0B.006 R885 64.78715.6DL X X R887 64.20525.6DL X X VGA_CORE R428 64.30025.6DL 64.73225.6DL 64.49925.6DL TVDAC RN31 X X X CRT RN30 X X X TRANSFORMER XF1~2 68.HD081.30B 68.HD081.30B 68.HD081.30B MVREFDA R803 64.10005.6DL X X MVREFSA R806 64.10005.6DL X X MVREFDB R804 64.10005.6DL X X MVREFSB R808 64.10005.6DL X X 90W/65W DCIN1 22.10037.I21 22.10037.I21 X 65.4FXZZ.024 65.4FXZZ.024 65.4FXZZ.024 65.4FXZZ.026 65.4FXZZ.026 65.4FXZZ.026 Change TC15 from 79.33719.L01 to 77.C3371.051 Change L19 from 68.R5610.10P to 68.R5610.10D B 1v_VGA/1.1v_VGA 65BOM A JV71-MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title HISTORY Size A2 Date: Document Number Rev -1 JV71-MV DDR3 Madison Thursday, November 05, 2009 Sheet 62 of 62 ... DY Q26 2N7002-11-GP R427 75KR2F-GP JV71- MV8 ENG 1002 2 DIS RT8202_FB_VGA R436 10KR2F-2-GP PW RCNTL_0 53 C741 SCD1U10V2KX-4GP DIS JV71- MV DDR3 Madison A JV71- MV8 ENG 1002 M96 Pro ALTV0 Vout 1.15V... H_A#_35 JV71- MV DDR3 Madison A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Date: Document Number Cantiga (1 of 6) JV71- MV DDR3 Madison... 71.ICH9M.00U A A JV71- MV DDR3 Madison Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Document Number ICH9-M (2 of 4) Rev -1 JV71- MV DDR3 Madison