Soc Encounter P1

NCTU NCTUNCTU NCTU- -- -EE ICLAB II EE ICLAB II EE ICLAB II EE ICLAB II – –– – Dec. Dec.Dec. Dec. 2005 20052005 2005 NCTU NCTUNCTU NCTU- -- -EE ICLAB II EE ICLAB II EE ICLAB II EE ICLAB II – –– – Dec. Dec.Dec. Dec. 2005 20052005 2005 Cell CellCell Cell- -- -based APR Design Flow based APR Design Flowbased APR Design Flow based APR Design Flow Cell CellCell Cell Cell CellCell Cell - -- - - -- - based APR Design Flow based APR Design Flowbased APR Design Flow based APR Design Flow based APR Design Flow based APR Design Flowbased APR Design Flow based APR Design Flow Chen Chen Chih Chih - - Lung Lung email : email : lung@si2lab.org lung@si2lab.org pg. 2 (61) Cell-based Design Flow pg. 3 (61) Cell-based Design Tools  System Architecture – C/C++ – System C – Matlab – …  RTL – Verilog-XL – NC-Verilog – NC-VHDL – Debussy – …  Synthesis – RTL Compiler – Design Vision – BuildGates – Verplex – PrimePower – …  Physical Design – Apollo – Silicon Ensemble – SoC Encounter – Magma – … pg. 4 (61) Traditional APR Flow  Synthesis  Floorplanning  Power planning  Optimization  Routing  RC extraction  Timing check pg. 5 (61) Wiring Problem  Wiring delay dominates overall delay  New problems due to large wire resistance – Timing closure – Signal Integrity closure (crosstalk, …) – Power closure (IR drop, …)                     pg. 6 (61) SoC Encounter  SoC Encounter – It is a hierarchical physical implementation environment – Comprised of the following tools • First Encounter – virtual prototyping, placement, clock tree insertion, GDSII generation • NanoRoute – signal integrity (SI) and timing aware routing • CeltIC – sign-off quality SI analysis • Physically Knowledgeable Synthesis (PKS) – complex optimizations which require logic restructuring • Fire&Ice QX – sign-off quality parasitic extraction • VoltageStorm – IR drop analysis pg. 7 (61) SoC Encounter Design Flow !  " #   $   "     ! %&' (( ) *    "+  ,% -$( pg. 8 (61) Getting Started  Data preparation – Library files • Technology information and Physical libraries – umc18_5lm.lef – umc18io3v5v_5lm.lef – umc18_5lm_antenna.lef – ram’s.vclef • Timing libraries – slow.lib – fast.lib – umc18io3v5v_fast.lib – umc18io3v5v_slow.lib – ram’s timing libraries • CeltIC libraries – umc18.cdB – Timing constraints • To generate timing constraint files from Design Vision, add the script write_sdc sdc_filename • Ex: write_sdc CHIP.sdc pg. 9 (61) Getting Started (cont.)  Data preparation (cont.) – Design Netlist • Add IO cells – Refer to IO cell library datasheet, type the following command at UNIX prompt – Add IO pads, core power pads, IO power pads, and corner pads to synthesized design netlist » PVDDC & PVSSC for core power pads » PVDDR & PVSSR for IO power pads » PCORNER for corners pads » P24C for output pads » P4C for input pads acroread /RAID2/Manager/lib.18/doc/umc18io3v5v.pdf & Note: how to decide the number of power pads will be discussed in power planning pg. 10 (61) Getting Started (cont.) – Design Netlist (cont.) • Uniquify design netlist – The Verilog design netlist must be unique for running Clock Tree Synthesis (CTS), Scan Reorder, and In-Placement Optimization(IPO) – To ensure that the names of all instantiated cells are unique, type uniquifyNetlist –top TopModuleName Uniquified_Netlist Design_Netlist at the UNIX prompt – Ex: uniquifyNetlist –top CHIP CHIP_unique.v CHIP_syn.v [...]... An example of IO pad location file pg 12 (61) Getting Started (cont.) Starting an Encounter session – To start an Encounter session, type encounter Note: 1 Do not use background execution!! 2 Log file name: encounter. log# 3 Command file name: command.log# pg 13 (61) Import Design Import design – Import design files into Encounter environment – Complete the following entries and click OK • In Design tab . pg. 6 (61) SoC Encounter  SoC Encounter – It is a hierarchical physical implementation environment – Comprised of the following tools • First Encounter. Starting an Encounter session – To start an Encounter session, type encounter Note: 1. Do not use background execution!! 2. Log file name: encounter. log#