Tài liệu Soc Encounter P2 pdf

pg. 31 (61) Power Planning (cont.)  Result of power planning pg. 32 (61) Standard Cell Placement  Set placement blockage – – Choose M2, M3. Then there will be no cell placed under strip – Specify placement blockage for macros pg. 33 (61) Standard Cell Placement (cont.)  Place standard cells – – Choose Timing Driven – Choose Save New Netlist to a specified filename – Tips • You may restart from this step by freeing design and reloading the saved netlist into Encounter • Free Design: type the command freeDesign in the command line • Restore Design: pg. 34 (61) Standard Cell Placement (cont.)  Result of standard cell placement pg. 35 (61) Pre-CTS Optimization  Pre-CTS timing analysis – timeDesign command • It will run trial route, RC extraction, timing analysis, and generates detailed timing reports • Type the following command in the command line timeDesign –preCTS • The generated timing reports are saved in ./timingReports/ , including “_preCTS.cap”, “_preCTS.fanout”, “_preCTS.tran”, and “_preCTS_all.tarpt” • If the timing is met, pre-CTS optimization can be skipped – Reports • Congestion distribution • Timing Summary pg. 36 (61) Pre-CTS Optimization (cont.)  Pre-CTS optimization – optDesign command • It will repair – Setup slack, Setup times – Design rule violations (DRVs), Remaining DRVs • To optimize timing placed design for the first time with ideal clocks optDesign –preCTS • To further optimize a design after above command execution optDesign –preCTS –incr pg. 37 (61) Clock Tree Synthesis  Clock Tree Synthesis (CTS) – The goal of clock tree synthesis includes • Creating clock tree spec file • Building a buffer distribution network • Routing clock nets using CTS-NanoRoute – In automatic CTS mode, Encounter will do the following things • Build the clock buffer tree according to the clock tree specification file • Balance the clock phase delay with appropriately sized, inserted clock buffers pg. 38 (61) Clock Tree Synthesis (cont.)  Clock Tree Synthesis (CTS) (cont.) – Creating clock tree specification file (.ctstch) • Syntax for automatic CTS 400psBufMaxTran 400psSinkMaxTran NONoGating CLKBUFX1 CLKBUFX2 … CLKINVX1 CLKINVX2 … Buffer 400psMaxSkew 0nsMinDelay 10nsMaxDelay clkAutoCTSRootPin YESPostOpt ExampleParameter pg. 39 (61) Clock Tree Synthesis (cont.)  Clock Tree Synthesis (CTS) (cont.) – Example of clock tree specification file (.ctstch) pg. 40 (61) Clock Tree Synthesis (cont.)  Specify clock tree – Assign clock tree specification file – – Complete the form and click OK  Synthesize clock tree – Create clock tree – – Complete the form and click OK CHIP.ctstchClock Tree File Fill InField Ϭ Handle Clock Crossover and Reconvergence Clock Tree Synthesis Fill InField . restart from this step by freeing design and reloading the saved netlist into Encounter • Free Design: type the command freeDesign in the command line • Restore. distribution network • Routing clock nets using CTS-NanoRoute – In automatic CTS mode, Encounter will do the following things • Build the clock buffer tree according