| Tài liệu tham khảo |
Loại |
Chi tiết |
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Sách, tạp chí |
| Tiêu đề: |
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability,” "IEEE Int. Conf. on Comput.-Aided Design |
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| [3] K. Ishibashi và K. Osada, Low Power and Reliable SRAM Memory Cell and Array Design , Springer Series in Advanced Microelectronics, 2011 |
Sách, tạp chí |
| Tiêu đề: |
Low Power and Reliable SRAM Memory Cell and Array Design |
|
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Sách, tạp chí |
| Tiêu đề: |
“Analyzing static and dynamic write margin for nanometer SRAMs,” Int. Symp. Low Power Electronics Design |
|
| [5] N. Gierczynski et al, “A new combined methodology for write-margin extraction of advanced SRAM,” IEEE Int. Conf. on Microelectronic Test Structures, tr. 97–100, 2007 |
Sách, tạp chí |
| Tiêu đề: |
A new combined methodology for write-margin extraction of advanced SRAM,” "IEEE Int. Conf. on Microelectronic Test Structures |
|
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Sách, tạp chí |
| Tiêu đề: |
Collection of charge on junction nodes from ion tracks”, "IEEE Trans. "Nucl. Sci |
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Sách, tạp chí |
| Tiêu đề: |
Novel 7T SRAM cell for low power cache design,” "IEEE Int. Con. on SOC |
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Sách, tạp chí |
| Tiêu đề: |
An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches”, "IEEE J. Solid-State Circuits |
|
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Sách, tạp chí |
| Tiêu đề: |
Characterization of a novelnine-transistor SRAM cell”, "IEEE Trans. "Very Large Scale Integrated (VLSI) Syst |
|
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Sách, tạp chí |
| Tiêu đề: |
A 256-kb 65-nm sub-threshold SRAM design for ultra-low voltage operation”, "IEEE J. Solid-State Circuits |
|
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Sách, tạp chí |
| Tiêu đề: |
Upset Hardened Memory Design for Submicron CMOS Technology,” "IEEE Trans. Nuclear Science |
|
| [12] Stanley Schuster, “Multiple Word/Bitline Redundancy for Semiconductor Memories,” IEEE J. of Solid State Circuits, tập SC-13, số 5, tr. 698-703, 1978 |
Sách, tạp chí |
| Tiêu đề: |
Multiple Word/Bitline Redundancy for Semiconductor Memories,” "IEEE J. of Solid State Circuits |
|
| [13] T. Mano, M. Wada, N. Ieda và M. Tanimoto, “A Redundancy Circuit for a Fault-Tolerant 256K MOS RAM,” IEEE J. of Solid State Circuits, tập SC-17, số 4, tr. 726-731, 1982 |
Sách, tạp chí |
| Tiêu đề: |
A Redundancy Circuit for a Fault-Tolerant 256K MOS RAM,” "IEEE J. of Solid State Circuits |
|
| [14] Jeanne P. Bickford, Raymond Rosner, Erik Hedberg, Joseph W. Yoder và Thomas S. Barnett, “SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off,”IEEE/SEMI Advanced Semiconductor Manufacturing Conf. (ASMC), tr. 387 – 392, 2008 |
Sách, tạp chí |
| Tiêu đề: |
SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off,” "IEEE/SEMI Advanced Semiconductor Manufacturing Conf. (ASMC) |
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| [15] Michael Wieckowski và Martin Margala, “A 32KB SRAM Cache Using Current Mode Operation and Asynchronous Wave-Pipelined Decoders,” IEEE Int. Conf. on SOC, tr. 251- 254, 2004 |
Sách, tạp chí |
| Tiêu đề: |
A 32KB SRAM Cache Using Current Mode Operation and Asynchronous Wave-Pipelined Decoders,” "IEEE Int. Conf. on SOC |
|
| [16] Koji Nii, et al., “A 90-nm Low-Power 32-KB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications,” IEEE J. of Solid-State Circuits, tập 39, số 4, tr. 684-693, 2004 |
Sách, tạp chí |
| Tiêu đề: |
A 90-nm Low-Power 32-KB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications,” "IEEE J. of Solid-State Circuits |
|
| [17] Nan-Chun Lien, et al., “A 40 nm 512 Kb Cross-Point 8T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist,”IEEE Trans. on Circuits and Systems, tập 61, số 12, tr. 3416-3425, 2014 |
Sách, tạp chí |
| Tiêu đề: |
A 40 nm 512 Kb Cross-Point 8T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist,” "IEEE Trans. on Circuits and Systems |
|
| [18] Igor Arsovski, Reid Wistort, “Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories,” Custom Intergrated Circuits Conf., tr. 453-456, 2006 |
Sách, tạp chí |
| Tiêu đề: |
Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories,” "Custom Intergrated Circuits Conf |
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| [1] ITRS: International technology road map for semiconductors, test and test equipments. http://public.itrs.net/ (2012) |
Link |
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