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FPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM3 Version Pong P. Chu Cleveland State University WILEY A JOHN WILEY SONS, INC., PUBLICATION This Page Intentionally Left BlankFPGA PROTOTYPING BY VERILOG EXAMPLES This Page Intentionally Left BlankFPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM3 Version Pong P. Chu Cleveland State University WILEY A JOHN WILEY SONS, INC., PUBLICATION Copyright O 2008 by John Wiley Sons, Inc. All rights reserved. Published by John Wiley Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate percopy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 7508400, fax (978) 7504470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley Sons, Inc., 1 l 1 River Sheet, Hoboken, NJ 07030, (201) 748601 1, fax (201) 748 6008, or online at http:1lwww.wiley.co1ngolpermission. Limit of LiabilitylDisclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 7622974, outside the United States at (3 17) 572 3993 or fax (3 17) 5724002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic format. For information about Wiley products, visit our web site at www.wiley.com. Library of Congress CataloginginPublication Data: Chu, Pong P., 1959 FPGA prototyping by Verilog examples 1 Pong P. Chu. p. cm. Includes index. ISBN 9780470185322 (cloth) 1. Field programmable gate arraysDesign and construction. 2. Prototypes, Engineering. 3.Verilog (Computer hardware description language) I. Title. TK7895.G36C484 2008 6 2 1 . 3 9 5 4 ~ 2 2 2008003732 Printed in the United States of America
FPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM-3Version Pong P Chu Cleveland State University WILEY A JOHN WILEY & SONS, INC., PUBLICATION This Page Intentionally Left Blank FPGA PROTOTYPING BY VERILOG EXAMPLES This Page Intentionally Left Blank FPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM-3Version Pong P Chu Cleveland State University WILEY A JOHN WILEY & SONS, INC., PUBLICATION Copyright O 2008 by John Wiley & Sons, Inc All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 1l River Sheet, Hoboken, NJ 07030, (201) 748-601 1, fax (201) 7486008, or online at http:1lwww.wiley.co1n/golpermission Limit of LiabilitylDisclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose No warranty may be created or extended by sales representatives or written sales materials The advice and strategies contained herein may not be suitable for your situation You should consult with a professional where appropriate Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (3 17) 5723993 or fax (3 17) 572-4002 Wiley also publishes its books in a variety of electronic formats Some content that appears in print may not be available in electronic format For information about Wiley products, visit our web site at www.wiley.com Library of Congress Cataloging-in-Publication Data: Chu, Pong P., 1959FPGA prototyping by Verilog examples Pong P Chu p cm Includes index ISBN 978-0-470-18532-2 (cloth) Field programmable gate arrays-Design and construction Prototypes, Engineering 3.Verilog (Computer hardware description language) I Title TK7895.G36C484 2008 621.39'54~22 2008003732 Printed in the United States of America In memory of myfathel; Chia Chi Chu This Page Intentionally Left Blank CONTENTS xxi Preface xxvii Acknowledgments PART I BASIC DIGITAL CIRCUITS Gate-level combinational circuit 1.1 1.2 1.3 Introduction General description Basic lexical elements and data types 1.3.1 Lexical elements 1.4 Data types 1.4.1 Four-value system 1.4.2 Data type groups 1.4.3 Number representation 1.4.4 Operators 1.5 Program skeleton 1.5.1 Port declaration S Program body 1.5.3 Signal declaration 1.5.4 Another example 1.6 Structural description 1.7 Testbench 1 3 4 5 7 12 vii 474 SAMPLE VERILOG TEMPLATES always @ ( p o s e d g e c l k , posedge r e s e t ) if (reset) q - r e g " LOC = "G13" , " s s e g < > " LOC = " N " ; " s s e g < > " LOC = " P " ; " s s e g < > " LOC = " R " ; " s s e g < l > " LOC = " F " ; " s s e g < O > " LOC = " N " ; # # # # # # # # decimul segment segment segment segment segment segment segment point a b c d e f g # d i s c r e t e LEDs NET NET NET NET NET NET NET NET "led" "led" "led" "led" "led" "led" "led" "led" LOC LOC LOC LOC LOC LOC LOC LOC = "K12"; = "P14"; = "L12"; = "N14"; = "P13"; = "N12"; = '1P12"; = "P11": # VGA o u t p u t s NET NET NET NET NET "rgb" "rgb" "rgb" "vsync" "hsync" LOC LOC LOC LOC LOC = "R12" = "T12" I DRIVE=8 I DRIVE=8 I " T " I DRIVE=8 I "R9" I DRIVE=8 I = "R11" = = I DRIVE=8 I SLEW=FAST; SLEW=FAST; SLEW=FAST; SLEW=FAST; SLEW=FAST; # PS2 port NET "ps2c" LOC="M1GW NET "ps2d1'LOC="M15" I IOSTANDARD=LVCMOS33 I DRIVE=8 ISLEW=SLOW: I IOSTANDARD=LVCMOS33 I DRIVE=8 ISLEW=SLOW; # two SRAM chips shared 18-bit memory a d d r e s s NET "ad" LOC="L3" I IOSTANDARD NET "ad" LOC="KS1' I IOSTANDARD NET "ad" LOC="K3" I IOSTANDARD NET "ad" LOC="J3" I IOSTANDARD NET "adI1 LOC="J4" I IOSTANDARD NET "ad" LOC="H4" I IOSTANDARD NET "ad" LOC="H3" I IOSTANDARD NET "ad" LOC="GS" I IOSTANDARD NET "ad" LOC="E4" I IOSTANDARD NET "ad" LOC="E3" I IOSTANDARD NET "ad" LOC="F4" I IOSTANDARD NET "ad" LOC="F3" I IOSTANDARD NET "ad" LOC="G4" I IOSTANDARD NET "ad" LOC="L4" I IOSTANDARD LOC="M3" I IOSTANDARD NET "ad" NET "adI1 LOC="M4" I IOSTANDARD NET "ad" LOC="N3" I IOSTANDARD NET "ad" LOC="LSM I IOSTANDARD # IOI shared oe, we NET "oe-n" LOC="K4" I IOSTANDARD NET " we-n" LOC="G3" IOSTANDARD = LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST: LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; LVCMOS33 I SLEW=FAST; = = LVCMOS33 LVCMOS33 = = = = = = = = = = = = = = = = = # sram chip data, ce, ub, lb NET "dio-a" LOC="RIN I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="PIM I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="L2" I IOSTANDARD=LVCMOS33 NET "dio-a It LOC="J2" I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="Hll' I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="F2" I IOSTANDARD=LVCMOS33 NET "dio-a " LOC="P8" I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="D3" I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="B1" I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="C1" I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="C2" I IOSTANDARD=LVCMOS33 NET " dio-a " LOC="RS1' I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="TSN I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="RGM I IOSTANDARD=LVCMOS33 NET "dio-a" LOC="T8" I IOSTANDARD=LVCMOS33 NET " dio-a " LOC="N7" I IOSTANDARD=LVCMOS33 NET "ce-a-nu LOC="P7" I IOSTANDARD=LVCMOS33 NET "ub-a-n" LOC="T4" I IOSTANDARD=LVCMOS33 # I SLEW=FAST; I SLEW=FAST; 53 BOARD CONSTRAINT FILE (S3.UCF) NET "lb-a-n" LOC="P6" I IOSTANDARD=LVCMOS33 I SLEW=FAST; sram chip data, ce, ub, lb NET "dio-bI1 LOC="N1" I IOSTANDARD=LVCMOS33 NET " dio-b " LOC="M1" I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="K2" I IOSTANDARD=LVCMOS33 NET "dio-b " LOC="C3" I IOSTANDARD=LVCMOS33 NET "die-b " LOC="F5" I IOSTANDARD=LVCMOS33 NET " dio-b " LOC="GI " I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="E2" I IOSTANDARD=LVCMOS33 NET " dio-b " LOC="D2" I IOSTANDARD=LVCMOS33 NET " dio-b < > " LOC='Dll' I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="Ell' I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="G2" I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="Jl" I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="Kl" I IOSTANDARD=LVCMOS33 NET "dio-b" LOC="M2" I IOSTANDARD=LVCMOS33 NET "dio-b " LOC="N2" I IOSTANDARD=LVCMOS33 NET "die-b" LOC="P2" I IOSTANDARD=LVCMOS33 NET "ce-b-n" LOC="N5" I IOSTANDARD=LVCMOS33 NET "ub-b-n" LOC="R4" I IOSTANDARD=LVCMOS33 NET " lb-b-n" LOC="P5" I IOSTANDARD=LVCMOS33 # # Timing constraint of S3 50-MHz onboard # name of the clock signal is clk NET "clk" TNM-NET TIMESPEC "TS-clk" = = oscillator "clk"; PERIOD "clk" 40 ns HIGH 50 %; 483 This Page Intentionally Left Blank REFERENCES P J Ashenden, The Designer's Guide to VHDL, 2nd ed., Morgan Kaufmann, 200 J Axelson, Serial Port Complete, 2nd ed., Lakeview Research, 2007 L Bening and H D Foster, Principles of Ver~jiableRTL Design, 2nd ed., Springer-Verlag, 2001 J Bergeron, Writing Testbenches: Functional VeriJication of HDL Models, Springer-Verlag, 2003 K Chapman, "Creating Embedded Microcontrollers," TechXcIusives at http://ww~.~ilinx.~~m A Chapweske, "PSI2 MouseIKeyboard Protocol," http://www.computer-engineering.org A Chapweske, "PSI2 Keyboard Interface," http://www.computer-engineering.org A Chapweske "PSI2 Mouse Interface," http://www.computer-engineering.org P P Chu, RTL Hardware Design Using VHDL: Codingfor Eflciency, Portability, andScalability, Wiley-IEEE Press, 2006 10 M D Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, 2003 1I M D Ciletti, Starter's Guide to Verilog 2001, Prentice Hall, 2003 12 C E Cummings, ""full_case parallel-case", the Evil Twins of Verilog Synthesis," SNUG (Synopsys Users Group Conference), Boston, 1999 13 C E Cummings, "Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!" SNUG (Svnops-vsUsers Group Conference), San Jose, 2000 14 C E Cummings, "Coding and Scripting Techniques for FSM Designs with Synthesis-Optimized, Glitch-Free Outputs," SNUG (Synopsys Users Group Conference), Boston, 2000 15 C E Cummings "New Verilog-2001 Techniques for Creating Parameterized Models (or Down With 'define and Death of a defparam!)," International HDL Conference, 2002 16 D D Gajski, Principles ofDigita1 Design, Prentice Hall, 1997 FPGA Prototyping by Verilog Examples By Pong P Chu Copyright @ 2008 John Wiley & Sons, Inc 17 J Hamblen et al., RapidPrototyping ofDigital Svstems: Quartus8 II Edition, Springer, 2005 18 IEEE, IEEE Standardfor Verilog Hardware Description Language (IEEE Std 1364-2001), Institute of Electrical and Electronics Engineers, 2001 19 IEEE, IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-2001), Institute o f Electrical and Electronics Engineers, 2001 20 M Keating and P Bricaud, Methodology Manualfor System-on-a-Chip Designs, 3rd ed., SpringerVerlag, 2002 C M Maxfield The Design Warrior's Guide to FPGAs, Newnes, 2004 22 Mentor Graphics, ModelSim Tutorial, Mentor Graphics Corporation 23 S Palnitkar, Verilog HDL, 2nd ed., Prentice Hall, 2003 24 D A Patterson and J L Hennessy, Computer Organization andDesign: The Hardware/Sof~are Interface, 3rd ed., Morgan Kaufmann, 2004 25 J M Rabaey, Digital Integrated Circuits, 2nd ed., Prentice Hall, 2002 26 S Sutherland, "What's New in the IEEE 1364 Verilog-2001 Standard," International HDL Conference, 2000 27 J F Wakerly Digital Design: Principles and Practices, Prentice Hall, 2002 28 W Wolf, FPGA-Based System Design, Prentice Hall, 2004 29 Xilinx, DS099 Spartan-3 FPGA Family: Complete Data Sheet, Xilinx, Inc 30 Xilinx, ISE 8.li Quick Start Tutorial, Xilinx, Inc Xilinx, ISE In-Depth Tutorial, Xilinx, Inc 32 Xilinx, PicoBlaze 8-Bit Embedded Microcontroller User Guide, Xilinx, Inc 33 Xilinx, Spartan-3 Starter Kit Board User Guide, Xilinx, Inc 34 Xilinx, XAPP462 Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs, Xilinx, Inc 35 Xilinx, XAPP463 Using Block RAM in Spartan-3 Generation FPGAs, Xilinx, Inc 36 Xilinx, XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3 Generatiori FPGAs, Xilinx, Inc 37 Xilinx XST User Guide v8.li, Xilinx, Inc INDEX always block, 48, 194 ASCII code, 230,246 ASM chart, 120 ASMD chart, 140 assignment blocking, 49, 175 continuous, nonblocking, 49, 176 barrel shifter, 73 BCD, 160 binary decoder, 53-54 bit-length adjustment, 45 CLB, 17 comments, connection by name, 10 connection by ordered list, 10 constant, 64 constraint file, 26 Core Generator, 299 counter, 93, 107 D FF, 83 data type, net group, reg, signed, 190 variable, 49 variable group, wire, x value, 47 z value, 46 DCM, 293 DDR register, 294 debouncing circuit, 130, 144 delay control, 196 development flow, 19 division circuit, 157 edge detector, 125 event control, 197 FIFO buffer, 110,223 flag FF, 221 floating-point adder, 75 FSM, 86, 119 FSMD, 86, 139,372 function, 191 system, 198 user defined, 202 hold time, 84 HyperTerminal, 229,246, 260 identifier, initial block, 194 instantiation, instruction memory, 372 instruction ROM, 376,4 1 instruction set, 377 interrupt, 389,453 IOB, 293 KCPSM3,376,380,390,393,407 localparam, 64 logic cell, 15 logic synthesis, 20 LUT, 16,297 macro cells, 17 maximal operating frequency, 85 Mealy output 120 memory controller, 269, 274,298 Moore output, 120 multiplexer, 59 number, sized, unsized, operator, 39 arithmetic, 41 bitwise, 42 concatenation, 43 conditional 44 logical, 43 precedence, 44 reduction, 42 relational, 42 shift, 41 pad delay, 288 parameter, 65 PBlazeIDE 380,390,407 placement and routing, 20 port declaration, primitive, 10 priority encoder, 52, 54 priority routing network 57 procedural statement, 194 case 54 full, 56 parallel, 57 casex, 56 casez, 56 for, 194 forever, 195 if, 51 repeat, 195 wait, 197 while 195 program counter, 372 PS2 keyboard, 240 mouse, 252 receiver, 236 transmitter, 253 RAM block, 298, 332, 342 distributed, 297 dual-port, 303, 332, 348 single-port, 300 static, 269-270 register, 84, 89 register file, 90, l I, 276 register transfer operation, 139 regular sequential circuit, 86 ROM, 305,325 font, 342 RS-232,215 sensitivity list, 48 setup time, 84 shift register, 91 sign-magnitude adder, signal declaration, slice, 17 state diagram, 120 static timing analysis, 20 synchronous design methodology, 83 technology mapping, 20 testbench, 12, 32, 96,204 tri-state buffer, 46, 274 UART, 5,434 ucf file, 26 user defined primitive, I I VGA mode, 12 video memory, 332 video synchronization, 12 .. .FPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM-3Version Pong P Chu Cleveland State University WILEY A JOHN WILEY & SONS, INC., PUBLICATION This Page Intentionally Left Blank FPGA PROTOTYPING. .. This Page Intentionally Left Blank FPGA PROTOTYPING BY VERILOG EXAMPLES This Page Intentionally Left Blank FPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM-3Version Pong P Chu Cleveland... P., 195 9FPGA prototyping by Verilog examples Pong P Chu p cm Includes index ISBN 978-0-470-18532-2 (cloth) Field programmable gate arrays-Design and construction Prototypes, Engineering 3.Verilog