Part 1 book “Digital systems - principles and applications” has contents: introductory concepts, number systems and codes, describing logic circuits, combinational logic circuits, flip-flops and related devices, digital arithmetic - operations and circuits, counters and registers.
www.downloadslide.net www.downloadslide.net TWELFTH EDITION GLOBAL EDITION Digital Systems Principles and Applications Neal S Widmer Purdue University Gregory L Moss Purdue University Ronald J Tocci Monroe Community College Harlow, England • London • New York • Boston • San Francisco • Toronto • Sydney • Dubai • Singapore • Hong Kong Tokyo • Seoul • Taipei • New Delhi • Cape Town • Sao Paulo • Mexico City • Madrid • Amsterdam • Munich • Paris • Milan www.downloadslide.net Editor-in-Chief: Andrew Gilfillan Product Manager: Anthony Webster Program Manager: Holly Shufeldt Project Manager: Rex Davidson Editorial Assistant: Nancy Kesterson Team Lead Project Manager: Bryan Pirrmann Team Lead Program Manager: Laura Weaver Project Manager, Global Edition: Sudipto Roy Senior Acquisitions Editor, Global Edition: Sandhya Ghoshal Senior Project Editor, Global Edition: Daniel Luiz Project Editor, Global Edition: Rahul Arora Manager, Media Production, Global Edition: M Vikram Kumar Manufacturing Controller, Production, Global Edition: Angela Hawksbee Director of Marketing: David Gesell Senior Product Marketing Manager: Darcy Betts Field Marketing Manager: Thomas Hayward Procurement Specialist: Deidra M Skahill Creative Director: Andrea Nix Art Director: Diane Y Ernsberger Cover Designer: Lumina Datamatics, Inc Full-Service Project Management: Philip Alexander/Integra Software Services, Pvt, Ltd Pearson Education Limited Edinburgh Gate Harlow Essex CM20 2JE England and Associated Companies throughout the world Visit us on the World Wide Web at: www.pearsonglobaleditions.com © Pearson Education Limited 2018 The rights of Ronald Tocci, Neal Widmer, and Greg Moss to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988 Authorized adaptation from the United States edition, entitled Digital Systems, 12th edition, ISBN 978-0-134-22013-0, by Ronald Tocci, Neal Widmer, and Greg Moss, published by Pearson Education © 2017 All rights reserved No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without either the prior written permission of the publisher or a license permitting restricted copying in the United Kingdom issued by the Copyright Licensing Agency Ltd, Saffron House, 6–10 Kirby Street, London EC1N 8TS All trademarks used herein are the property of their respective owners The use of any trademark in this text does not vest in the author or publisher any trademark ownership rights in such trademarks, nor does the use of such trademarks imply any affiliation with or endorsement of this book by such owners ISBN 10: 129-2-16200-7 ISBN 13: 978-1-292-16200-3 British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library 10 14 13 12 11 10 Printed and bound in Vivar, Malaysia Typeset in Times Europa LT Std Roman by Integra Software Services, Pvt, Ltd www.downloadslide.net Preface This book is a comprehensive study of the principles and techniques of modern digital systems It teaches the fundamental principles of digital systems and covers thoroughly both traditional and modern methods of applying digital design and development techniques, including how to manage a systemslevel project The book is intended for use in two- and four-year programs in technology, engineering, and computer science It can also be used for High School STEM education courses in these topical areas Although a background in basic electronics is helpful, most of the material requires no electronics training Portions of the text that use electronics concepts can be skipped without adversely affecting the comprehension of the logic principles What’s New in This Edition? The following list summarizes the improvements in the twelfth edition of Digital Systems Details can be found in the section titled “Specific Changes” on page ■ ■ ■ ■ ■ ■ ■ Every section of every chapter now has a short list of expected outcomes for that section Chapter has been revised extensively in response to feedback from users New material on troubleshooting prototype circuits using systematic fault isolation techniques applied to digital logic circuits has been added to Section 4-13 Quadrature Shaft Encoders used to obtain absolute shaft position serve as a real example of flip-flop applications, and timing limitations More material has been added to better explain the behavior of VHDL data objects and how they are updated in sequential processes Throughout the text, obsolete technology has been deleted or abbreviated to provide only content appropriate to modern systems More modern examples are used as needed Some new problems have been added and outdated problems have been removed www.downloadslide.net PREFACE General Features In industry today, getting a product to market very quickly is important The use of modern design tools, CPLDs, and FPGAs allows engineers to progress from concept to functional silicon very quickly Microcontrollers have taken over many applications that once were implemented by digital circuits, and DSP has been used to replace many analog circuits It is amazing that microcontrollers, DSP, and all the necessary glue logic can now be consolidated onto a single FPGA using a hardware description language with advanced development tools Today’s students must be exposed to these modern tools, even in an introductory course It is every educator’s responsibility to find the best way to prepare graduates for the work they will encounter in their professional lives The standard SSI and MSI parts that have served as “bricks and mortar” in the building of digital systems for over 40 years are now obsolete and becoming less available Many of the techniques that have been taught over that time have focused on optimizing circuits that are built from these outmoded devices The topics that are uniquely suited to applying the old technology but not contribute to an understanding of the new technology are being de-emphasized From an educational standpoint, however, these small ICs offer a way to study simple digital circuits, and the wiring of circuits using breadboards is a valuable pedagogic exercise They help to solidify concepts such as binary inputs and outputs, physical device operation, and practical limitations, using a very simple platform Consequently, we have chosen to continue to introduce the conceptual descriptions of digital circuits and to offer examples using conventional standard logic parts For instructors who continue to teach the fundamentals using SSI and MSI circuits, this edition retains those qualities that have made the text so widely accepted in the past Many hardware design tools even provide an easy-to-use design entry technique that will employ the functionality of conventional standard parts with the flexibility of programmable logic devices A digital design can be described using a schematic drawing with pre-created building blocks that are equivalent to conventional standard parts, which can be compiled and then programmed directly into a target PLD with the added capability of easily simulating the design within the same development tool We believe that graduates will actually apply the concepts presented in this book using higher-level description methods and more complex programmable devices The major shift in the field is a greater need to understand the description methods, rather than focusing on the architecture of an actual device Software tools have evolved to the point where there is little need for concern about the inner workings of the hardware but much more need to focus on what goes in, what comes out, and how the designer can describe what the device is supposed to We also believe that graduates will be involved with projects using state-of-the-art design tools and hardware solutions This book offers a strategic advantage for teaching the vital topic of hardware description languages to beginners in the digital field VHDL is undisputedly an industry standard language at this time, but it is also very complex and has a steep learning curve Beginning students are often discouraged by the rigorous requirements of various data types, and they struggle with understanding edge-triggered events in VHDL Fortunately, Altera offers AHDL, a less demanding language that uses the same basic concepts as VHDL but is much easier for beginners to master So, instructors can opt to use AHDL to teach introductory students or VHDL for more advanced classes This edition offers more than 40 AHDL examples, more than 40 VHDL examples, and many examples of simulation testing All of these design files are available on the website (http://www.pearsonglobaleditions.com/tocci) www.downloadslide.net PREFACE Altera’s software development system is Quartus II The material in this text does not attempt to teach a particular hardware platform or the details of using a software development system We have chosen to show what this tool can do, rather than train the reader how to use it Many laboratory hardware options are available to users of this book Complete development boards are available that offer the normal types of inputs and outputs like logic switches, pushbuttons, clock signals, LEDs, and 7-segment displays Many boards also offer standard connectors for readily available computer hardware, such as a standard keyboard, computer mouse, VGA video monitor, COM ports, audio in/out jacks, plus two 40-pin general-purpose I/O ribbon connectors that allow connection to any digital peripheral hardware Our approach to HDL and PLDs gives instructors several options: The HDL material can be skipped entirely without affecting the continuity of the text HDL can be taught as a separate topic by skipping the material initially and then going back to the last sections of Chapters 3, 4, 5, 6, 7, and and then covering Chapter 10 HDL and the use of PLDs can be covered as the course unfolds— chapter by chapter—and woven into the fabric of the lecture/lab experience Among all specific hardware description languages, VHDL is clearly the industry standard and is most likely to be used by graduates in their careers We have always felt that it is a bold proposition, however, to try to teach VHDL in an introductory course The nature of the syntax, the subtle distinctions in object types, and the higher levels of abstraction can pose obstacles for a beginner For this reason, we have included Altera’s AHDL as the recommended introductory language for freshman and sophomore courses We have also included VHDL as the recommended language for more advanced classes or introductory courses offered to more mature students We not recommend trying to cover both languages in the same course Sections of the text that cover the specifics of a language are clearly designated with a color bar in the margin The HDL code figures are set in a color to match the color-coded text explanation The reader can focus only on the language of his or her choice and skip the other Obviously, we have attempted to appeal to the diverse interests of our market, but we believe we have created a book that can be used in multiple courses and will serve as an excellent reference after graduation Chapter Organization Many instructors opt to not use the chapters of a textbook in the sequence in which they are presented This book was written so that, for the most part, each chapter builds on previous material, but it is possible to alter the chapter sequence somewhat The first part of Chapter (arithmetic operations) can be covered right after Chapter (number systems), although this will lead to a long interval before the arithmetic circuits of Chapter are encountered Much of the material in Chapter (IC characteristics) can be covered earlier (e.g., after Chapter or 5) without creating any serious problems This book can be used either in a one-term course or in a two-term sequence In a one-term course, limits on available class hours might require omitting some topics Obviously, the choice of deletions will depend on factors such as program or course objectives and student background Sections www.downloadslide.net FiGurE P1 Letters denote categories of problems, and asterisks indicate that corresponding solutions are provided at the end of the text PREFACE PROBLEMS SECTION 9-1 B B 9-1 Refer to Figure 9-3 Determine the levels at each decoder output for the following sets of input conditions (a)*All inputs LOW (b)*All inputs LOW except E3 = HIGH (c) All inputs HIGH except E1 = E2 = LOW (d) All inputs HIGH 9-2.* What is the number of inputs and outputs of a decoder that accepts 128 different input combinations? * Answers to problems marked with an asterisk can be found in the back of the text in each chapter that deal with troubleshooting, PLDs, HDLs, or microcomputer applications can be deferred to an advanced course PrObLEM SETS This edition includes six categories of problems: basic (B), challenging (C), troubleshooting (T), new (N), design (D), and HDL (H) Undesignated problems are considered to be of intermediate difficulty, between basic and challenging Problems for which solutions are printed in the back of the text or on the website (http://www.pearsonglobaleditions com/tocci) are marked with an asterisk (see Figure P1) PrOjECT MANAGEMENT AND SySTEM-LEvEL DESiGN Several realworld examples are included in Chapter 10 to describe the techniques used to manage projects These applications are generally familiar to most students studying electronics, and the primary example of a digital clock is familiar to everyone Many texts talk about top-down design, but this text demonstrates the key features of this approach and how to use the modern tools to accomplish it SiMuLATiON FiLES This edition also includes simulation files that can be loaded into Multisim® The circuit schematics of many of the figures throughout the text have been captured as input files for this popular simulation tool Each file has some way of demonstrating the operation of the circuit or reinforcing a concept In many cases, instruments are attached to the circuit and input sequences are applied to demonstrate the concept presented in one of the figures of the text These circuits can then be modified as desired to expand on topics or create assignments and tutorials for students All figures in the text that have a corresponding simulation file on the website are identified by the icon shown in Figure P2 Specific Changes The major changes in the topical coverage are listed here ■ Chapter Chapter has been revised extensively in response to feedback from users The significance of how Digital Systems will impact innovations of the future is emphasized New material focuses on interpretation of terminology and introduction to concepts used throughout the text Basic concepts of binary www.downloadslide.net PREFACE FIGURE 9-1 General decoder diagram A0 O0 A1 N inputs A2 O1 Decoder N AN21 input codes FiGurE P2 ■ ■ ■ ■ ■ ■ ■ O2 M outputs OM21 Only one output is HIGH for each input code The icon denotes a corresponding simulation file on the Web signals are introduced and explained through examples New material on periodic cycles and measurements on digital waveforms is presented, setting the stage for understanding these issues in later chapters The basics of digital signals and sampling are explained at a very introductory level This chapter in the 11th edition had material that has now become very outdated since its publication Some of the historic analogies used in that edition were ineffective The revisions have replaced or eliminated these Chapter The Gray Code is used to introduce the concept of a quadrature encoder: a device that produces a 2-bit Gray Code sequence capable of discerning the direction and angular rotation of a shaft Chapter New problems at the end of this chapter focus on logic circuits common to automobiles Chapter The material introducing PLD programming and development software has been updated and improved The section on troubleshooting has been expanded to teach structured problem solving as it applies to hardware debugging of traditional prototyped digital circuits The VHDL material has been enhanced to explain some subtle but very important aspects of data objects in this language The role of the “PROCESS” is also more thoroughly covered improving the foundation that Chapter builds on Chapter High-speed digital systems are easily affected by timing limitations of the circuitry New material in this chapter explains the adverse effects caused when setup and hold time requirements are violated by explaining meta-stability A teaching example that can be reproduced in the laboratory environment has been added The focus is on the many applications of D flip-flops but it is presented in the context of a quadrature shaft encoder that must reliably and repeatedly keep track of absolute shaft position as it is rotated back and forth over many cycles Design techniques from Chapter are employed to design a circuit that should meet the system’s needs The initial circuit’s marginal performance demonstrates what happens when real-timing constraints are not taken into account A way to correct this problem is presented using even more applications of D flip-flops Chapter An Example from the 11th edition used some features of Quartus software that have since become obsolete The example has been modified to align with more recent updates of Quartus Chapter Very few and minor changes were made to Chapter Chapter The section on the obsolete Emitter Coupled Logic (ECL) was deleted along with other minor updates www.downloadslide.net PREFACE ■ ■ ■ ■ ■ Chapter The concept of Time Division Multiplexing is added to provide an example of how many digital signals are able to share a common data pathway A simple system is presented that can easily be reproduced in a laboratory exercise Chapter 10 No changes were made in Chapter 10 Chapter 11 No changes were made in Chapter 11 Chapter 12 The coverage of floating gate MOSFETS, the technology behind flash memory, is enhanced Chapter 13 This chapter has been generalized with references to older series of CPLDs and FPGAs abbreviated retained Features This edition retains all of the features that made the previous editions so widely accepted It utilizes a block diagram approach to teach the basic logic operations without confusing the reader with the details of internal operation All but the most basic electrical characteristics of the logic ICs are withheld until the reader has a firm understanding of logic principles In Chapter 8, the reader is introduced to the internal IC circuitry At that point, the reader can interpret a logic block’s input and output characteristics and “fit” it properly into a complete system The treatment of each new topic or device typically follows these steps: the principle of operation is introduced; thoroughly explained examples and applications are presented, often using actual ICs; short review questions are posed at the end of the section; and finally, in-depth problems are available at the end of the chapter These problems, ranging from simple to complex, provide instructors with a wide choice of student assignments These problems are often intended to reinforce the material without simply repeating the principles They require students to demonstrate comprehension of the principles by applying them to different situations This approach also helps students to develop confidence and expand their knowledge of the material The material on PLDs and HDLs is distributed throughout the text, with examples that emphasize key features in each application These topics appear at the end of each chapter, making it easy to relate each topic to the general discussion earlier in the chapter or to address the general discussion separately from the PLD/HDL coverage The extensive troubleshooting coverage is spread over Chapters through 12 and includes presentation of troubleshooting principles and techniques, case studies, 17 troubleshooting examples, and 46 real troubleshooting problems When supplemented with hands-on lab exercises, this material can help foster the development of good troubleshooting skills This edition offers more than 220 worked-out examples, more than 660 review questions, and more than 640 chapter problems/exercises Some of these problems are applications that show how the logic devices presented in the chapter are used in a typical microcomputer system Answers to a majority of the problems immediately follow the Glossary The Glossary provides concise definitions of all terms in the text that have been highlighted in boldface type An IC index is provided at the back of the book to help readers locate easily material on any IC cited or used in the text The back endsheets provide tables of the most often used Boolean algebra theorems, logic gate summaries, and flip-flop truth tables for quick reference when doing problems or working in the lab www.downloadslide.net PREFACE Supplements An extensive complement of teaching and learning tools has been developed to accompany this textbook Each component provides a unique function, and each can be used independently or in conjunction with the others WEb rESOurCES ■ ■ ■ Quartus ii Web version software from Altera This development system software is available from Altera Design files from the textbook figures More than 40 design files in each language are presented in figures throughout the text Students can load these into the Altera software and test them Circuits from the text rendered in Multisim® Students can open and work interactively with approximately 100 circuits to increase their understanding of concepts and prepare for laboratory activities The Multisim circuit files are provided for use by anyone who has Multisim software iNSTruCTOr rESOurCES ■ ■ ■ Online Instructor’s Resource Manual This manual contains worked-out solutions for all end-of-chapter problems in this textbook Online PowerPoint® presentations Figures from the text, in addition to Lecture Notes for each chapter, are available Online TestGen A computerized test bank is available To access supplementary materials online, instructors need to request an instructor access code Go to www.pearsonglobaleditions.com/tocci, where you can register for an instructor access code Within 48 hours after registering, you will receive a confirming e-mail, including an instructor access code Once you have received your code, go to the site and log on for full instructions on downloading the materials you wish to use Acknowledgments We are grateful to all those who evaluated the eleventh edition and provided answers to an extensive questionnaire: Their comments, critiques, and suggestions were given serious consideration and were invaluable in determining the final form of the twelfth edition We also are greatly indebted to Professor Frank Ambrosio, Monroe Community College, for his usual high-quality work on the Instructor’s www.downloadslide.net 555 PROBLEMS 74ALS161 CLK ENT ENP fin RCO U1 fout1 CLR 74ALS161 LOAD CLK ENT ENP QD QC QB QA D C B A U2 CLR LOAD D C B A FiGurE 7-109 D D RCO QD QC QB QA fout2 Problem 7-32 7-33.* Design a frequency divider circuit that will produce the following three output signal frequencies: 1.5 MHz, 150 kHz, and 100 kHz Use 74HC162 and 74HC163 counter chips and any necessary gates The input frequency is 12 MHz 7-34 Design a frequency divider circuit that will produce the following three output signal frequencies: MHz, 800 kHz, and 100 kHz Use 74HC160 and 74HC161 counter chips and any necessary gates The input frequency is 12 MHz SECTION 7-8 b b 7-35.* Draw the decoding gate required to produce a LOW output when a counter of five bits is at count 28 7-36 Draw the AND gates necessary to decode the 10 states of a decade counter that counts from 00112 (310) to 11002 (1210) SECTION 7-9 C C C C 7-37.* Analyze the synchronous counter in Figure 7-110(a) Draw its timing diagram and determine the counter’s modulus 7-38 Repeat Problem 7-37 for Figure 7-110(b) 7-39.* Analyze the synchronous counter in Figure 7-111(a) Draw its timing diagram and determine the counter’s modulus 7-40 Repeat Problem 7-39 for Figure 7-111(b) www.downloadslide.net 556 CHAPTER 7/COUNTERS AND REGISTERS J D J C CLK B K C CLR J A CLK CLK K D J B CLR CLK A K CLR K CLR CLK (a) J D CLK B CLR K CLR J A CLK K C CLR J B CLK K D J C CLK A K CLR CLK D C B A (b) FiGurE 7-110 C C Problems 7-37 and 7-38 7-41.* Analyze the synchronous counter in Figure 7-112(a) F is a control input Draw its state transition diagram and determine the counter’s modulus 7-42 Analyze the synchronous counter in Figure 7-112(b) Draw its complete state transition diagram and determine the counter’s modulus Is the counter self-correcting? SECTION 7-10 D 7-43.* (a) Design a synchronous counter using J-K FFs that has the following sequence: 000, 010, 101, 110, and repeat The undesired (unused) states 001, 011, 100, and 111 must always go to 000 on the next clock pulse (b) Redesign the counter of part (a) without any requirement on the unused states; that is, their NEXT states can be don’t cares Compare with the design from (a) www.downloadslide.net 557 PROBLEMS J C J A CLK CLK K C J B CLK A K B K CLK (a) J C CLK C J B A CLK CLK K K B J A K CLK (b) FiGurE 7-111 D D D D D Problems 7-39 and 7-40 7-44 Design a synchronous, recycling, MOD-4 up counter that produces the sequence 000, 010, 100, 110, and repeats Use J-K flip-flops (a) Force the unused states to 000 on the next clock pulse (b) Use don’t-care NEXT states for the unused states Is this design self-correcting? 7-45.* Design a synchronous, recycling, BCD down counter with J-K FFs using don’t-care NEXT states 7-46 Design a synchronous, recycling, MOD-6 up/down counter with J-K FFs Use the states 000 through 101 in the counter Control the count direction with input D (D = to count up and D = to count down) 7-47.* Design a synchronous, recycling, MOD-8, binary down counter with D flip-flops 7-48 Design a synchronous MOD-8 counter with D FFs that counts 0101 to 1100 repeatedly Force unused states to 0101 on next clock pulse www.downloadslide.net 558 CHAPTER 7/COUNTERS AND REGISTERS J D C CLK B C J A CLK CLK K D J B K J CLK A K K F CLK (a) C B C DC D A D B CLK DB A CLK C B D DA CLK A CLOCK (b) FiGurE 7-112 Problems 7-41 and 7-42 SECTIONS 7-11 AND 7-12 H, D, N 7-49.* Design a recycling, MOD-13, up counter The count sequence should be 0000 through 1100 Simulate (functional) the counter (a) Use LPM_COUNTER (b) Use an HDL www.downloadslide.net 559 PROBLEMS H, D, N H, D H, D 7-50 Design a recycling, MOD-25, down counter The count sequence should be 11000 through 00000 Simulate (functional) the counter (a) Use LPM_COUNTER (b) Use an HDL 7-51.* Design a recycling, synchronous MOD-8 Odd counter with D FFs using both AHDL and VHDL The counter should count all odd numbers from to 15 and repeat All unused states will be forced to at the next clock pulse 7-52 Design a bidirectional, half-step controller for a stepper motor using an HDL The direction control input (dir) will produce a clockwise (CW) pattern when HIGH or counterclockwise when LOW The sequence is given in Figure 7-113 Simulate the sequential circuit FiGurE 7-113 Problem 7-52 CW 0101 0001 1001 1000 Q3 Q2 Q1 Q0 CCW 0100 H, D, N H, D, N H, b H, b H, D, N H, D, N 0110 0010 1010 7-53.* Design a frequency divider circuit to output a 100-kHz signal The input frequency is MHz Simulate (functional) the counter (a) Use LPM_COUNTER (b) Use an HDL 7-54 Design a frequency divider circuit that will output either of two specified frequency signals The output frequency is selected by the control input fselect The divider will output a frequency of kHz when fselect = or 12 kHz when fselect = The input frequency is 60 kHz Simulate (functional) the counter (a) Use LPM_COUNTER Hints: Create a down counter that reloads the appropriate value (determined by fselect) after the terminal state is reached You will also need one logic gate (b) Use an HDL 7-55.* Expand the full-featured HDL counter in Section 7-12 to a MOD-256 counter Simulate the counter 7-56 Expand the full-featured HDL counter in Section 7-12 to a MOD-1024 counter Simulate the counter 7-57.* Design a recycling, MOD-16, down counter The counter should have the following controls (from lowest to highest priority): an activeLOW count enable (en), an active-HIGH synchronous clear (clr), and active-LOW synchronous load (ld) Decode the terminal count when enabled by en Simulate (functional) the counter Be sure to verify the decoder operation (a) Use LPM_COUNTER Use any necessary logic gates (b) Use an HDL 7-58 Design a recycling, MOD-10, up/down counter The counter will count up when up = and will count down when up = The counter should also have the following controls (from lowest to highest www.downloadslide.net 560 CHAPTER 7/COUNTERS AND REGISTERS priority): an active-HIGH count enable (enable), active-HIGH synchronous load (load), and an active-LOW asynchronous clear (clear) Decode the terminal count when enabled by enable Simulate (functional) the counter (a) Use LPM_COUNTER Use any necessary logic gates (b) Use an HDL SECTION 7-13 H H H, D, N H, D, N 7-59.* Create a MOD-1000 BCD counter by cascading together three of the HDL BCD counter modules (described in Section 7-13) Simulate the counter 7-60 Create a MOD-256 binary counter by cascading together two of the full-featured, MOD-16, HDL counter modules (described in Section 7-12) Simulate the counter 7-61.* Design a synchronous, MOD-50 BCD counter by cascading a MOD-10 and a MOD-5 counter together The MOD-50 counter should have an active-HIGH count enable (enable) and an active-LOW synchronous clear (clrn) Be sure to include the terminal count detection for the one’s digit to cascade with the ten’s digit Simulate (functional) the counter (a) Use LPM_COUNTER Use any necessary logic gates (b) Use an HDL 7-62 Design a synchronous, MOD-100, BCD down counter by cascading two MOD-10, down counter modules together The MOD-100 counter should have a synchronous parallel load (load) Simulate (functional) the counter (a) Use LPM_COUNTER (b) Use an HDL SECTION 7-14 H H 7-63.* Modify the HDL description in Figure 7-60 or Figure 7-61 to add a rinse sequence after the clothes are washed The new state machine sequence should be idle S wash_fill S wash_agitate S wash_spin S rinse_fill S rinse_agitate S rinse_spin S idle Use hot water to wash, and cold water to rinse (add output bits to control two water valves) Simulate the modified HDL design 7-64 Simulate the HDL traffic light controller design presented in Section 7-14 PART SECTIONS 7-15 THROUGH 7-16 b 7-65.* A set of 74ALS174 registers is connected as shown in Figure 7-114 What type of data transfer is performed with each register? Determine the output of each register when the MR is pulsed momentarily LOW and after each of the indicated clock pulses (CP#) in Table 7-10 How many clock pulses must be applied before data that are input on I5–I0 are available at Z5–Z0? www.downloadslide.net 561 PROBLEMS I5 I4 I3 I2 I1 I0 D5 D4 D3 D2 D1 D0 CLK D5 CP D4 D3 D2 D1 D0 CP 74ALS174 74ALS174 MR MR Q5 Q4 Q3 Q2 Q1 Q0 W5 W4 W3 W2 W1 W0 D5 D4 D3 D2 D1 Q5 Q4 Q3 Q2 Q1 Q0 Y5 Y4 Y3 Y2 Y1 Y0 D0 D5 CP D4 D3 D2 D1 D0 CP 74ALS174 74ALS174 MR MR Q5 Q4 Q3 Q2 Q1 Q0 X5 X4 X3 X2 X1 X0 Q5 Q4 Q3 Q2 Q1 Q0 Z5 Z4 Z3 Z2 Z1 Z0 MR FiGurE 7-114 TAbLE 7-10 b b b b Problem 7-65 c CLK MR I5–I10 X 101010 CP1 101010 CP2 010101 CP3 000111 CP4 111000 CP5 011011 CP6 001101 CP7 000000 CP8 000000 W5–W0 X5–X0 Y5–Y0 Z5–Z0 7-66 Complete the timing diagram in Figure 7-115 for a 74HC174 How does the timing diagram show that the master reset is asynchronous? 7-67.* How many clock pulses will be needed to completely load eight bits of serial data into a 74ALS166? How does this relate to the number of flip-flops contained in the register? 7-68 Repeat Example 7-20 for the input waveforms given in Figure 7-116 7-69.* Repeat Example 7-22 with DS = and the input waveforms given in Figure 7-117 7-70 Apply the input waveforms given in Figure 7-118 to a 74ALS166 and determine the output produced 7-71.* While examining the schematic for a piece of equipment, a technician or an engineer will often come across an IC that is unfamiliar In such cases, it is often necessary to consult the manufacturer’s data www.downloadslide.net 562 CHAPTER 7/COUNTERS AND REGISTERS CP MR D5 - D0 110011 010010 101001 010110 001110 Q5 Q4 Q3 Q2 Q1 Q0 FiGurE 7-115 Problem 7-66 CLK CLR SER QH FiGurE 7-116 Problem 7-68 CP SH/LD P0 - P7 1100 1010 (Q0) (Q1) (Q2) (Q3) (Q4) (Q5) (Q6) Q7 FiGurE 7-117 Problem 7-69 0011 0101 100011 www.downloadslide.net 563 PROBLEMS FiGurE 7-118 Problem 7-70 CLK CLK INH SH/LD CLR ABCD EFGH 0101 0011 1001 0010 SER (QA) (QB) (QC) (QD) (QE) (QF) (QG) QH sheets for specifications on the device Research the data sheet for the 74AS194 bidirectional universal shift register to answer the following questions: (a) Is the CLR input asynchronous or synchronous? (b) True or false: When CLK is LOW, the S0 and S1 inputs have no effect on the register (c) Assume the following conditions: QA QB QC QD = 1 A B C D = 1 CLR = SR SER = SL SER = C If S0 = and S1 = 1, determine the register outputs after one CLK pulse After two CLK pulses After three After four (d) Use the same conditions except S0 = and S1 = and repeat part (c) (e) Repeat part (c) with S0 = and S1 = (f) Repeat part (c) with S0 = and S1 = (g) Use the same conditions as in part (c), except assume that QA is connected to SL SER What will be the register outputs after four CLK pulses? 7-72 Refer to Figure 7-119 to answer the following questions: (a) Which register function (load or shift) will be performed on the next clock if in = and out = 0? What data value will be input when clocked? www.downloadslide.net 564 CHAPTER 7/COUNTERS AND REGISTERS FiGurE 7-119 Problem 7-72 CLK CLK A F G H CLK INH SH/LD IN B C D E 74ALS166 CLR SER QH OUT (b) Which register function (load or shift) will be performed on the next clock if in = and out = 1? What data value will be input when clocked? (c) Which register function (load or shift) will be performed on the next clock if in = and out = 0? What data value will be input when clocked? (d) Which register function (load or shift) will be performed on the next clock if in = and out = 1? What data value will be input when clocked? (e) What input condition will eventually (after several clock pulses) cause the output to switch states? (f) To change the output logic level requires the new input condition to last for at least how many clock pulses? (g) If the input signal changes levels and then goes back to its original logic level before the number of clock pulses specified in part (f), what happens to the output signal (h) Explain why this circuit can be used to debounce switches SECTION 7-17 b b 7-73.* Draw the diagram for a MOD-5 ring counter using J-K flip-flops Make sure that the counter will start the proper count sequence when it is turned on 7-74 Draw a sequence table for the first 10 clock pulses and the state diagram of the MOD-5 ring counter in Problem 7-73 What changes will you incorporate in the circuit to convert it into a Johnson counter? What is the MOD value of this counter? Draw its state diagram 7-75.* Draw the diagram for a MOD-10 Johnson counter using a 74HC164 Make sure that the counter will start the proper count sequence when it is turned on Determine the count sequence for this counter and draw the decoding circuit needed to decode each of the 10 states This is another example of a decade counter that is not a BCD counter 7-76 If the Johnson counter in Problem 7-75 is changed to a MOD-20 counter with 60Hz clock input, find the frequency and duty cycle SECTION 7-18 T 7-77.* The MOD-10 counter in Figure 7-8(b) produces the count sequence 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, and repeats Identify some possible fault conditions that might produce this result www.downloadslide.net PROBLEMS T 565 7-78 The MOD-10 counter in Figure 7-8(b) produces the count sequence 0000, 0101, 0010, 0111, 1000, 1101, 1010, 1111, and repeats Identify some possible fault conditions that might produce this result SECTIONS 7-19 AND 7-20 N N N N H H 7-79.* Create an eight-bit SISO shift register The serial input is called ser and the serial output is called qout An active-LOW enable (en) controls the shift register Simulate (functional) the design (a) Use LPM_SHIFTREG Use any necessary logic gates (b) Use an HDL 7-80 Create an eight-bit PIPO shift register The data in is d[7 0] and the outputs are q[7 0] An active-HIGH enable (ld) controls the shift register Simulate (functional) the design (a) Use LPM_FF (b) Use an HDL 7-81.* Create an eight-bit PISO shift register The data in is d[7 0] and the output is q0 The shift-register function is controlled by sh_ld 1sh_ld = to synchronously parallel load and sh_ld = to serial shift) The serial input while shifting should be a constant LOW The register also should have an active-LOW asynchronous clear (clrn) Simulate (functional) the design (a) Use LPM_SHIFTREG Use any necessary logic gates (b) Use an HDL 7-82 Create an eight-bit SIPO shift register The data in is ser_in and the outputs are q[7 0] The shift-register function is enabled by an active-HIGH control named shift The shift register also has a higher priority active-HIGH synchronous clear (clear) Simulate (functional) the design (a) Use LPM_SHIFTREG Use any necessary logic gates (b) Use an HDL 7-83.* Simulate the universal shift-register design from Example 7-27 7-84 Create an eight-bit universal shift register by cascading two of the modules in Example 7-27 Simulate the design SECTION 7-21 H, D H, D 7-85.* Design a MOD-10, self-starting Johnson counter with an active-HIGH, asynchronous reset (reset) using an HDL Simulate the design 7-86 Sometimes a digital application may need a ring counter that recirculates a single zero instead of a single one The ring counter would then have an active-LOW output instead of an active-HIGH Design a MOD-8, self-starting ring counter with an active-LOW output using an HDL The ring counter should also have an active-HIGH hold control to disable the counting Simulate the design SECTION 7-22 H 7-87.* Use Altera’s simulator to test the nonretriggerable, level-sensitive, one-shot design example in either Figure 7-95 (AHDL) or 7-96 www.downloadslide.net 566 CHAPTER 7/COUNTERS AND REGISTERS H (VHDL) Use a 1-kHz clock and create a 10-ms output pulse for the simulation Verify that: (a) The correct pulse width is created when triggered (b) The output can be terminated early with the reset input (c) The one-shot design is nonretriggerable and cannot be triggered again until it has timed out (d) The trigger signal must last long enough for the clock to catch it (e) The pulse width can be changed to a different value 7-88 Modify the nonretriggerable, level-sensitive, one-shot design example from either Figure 7-95 (AHDL) or Figure 7-96 (VHDL) so that the one-shot is retriggerable but still level-sensitive Simulate the design DRILL QUESTION b 7-89.* For each of the following statements, indicate the type(s) of counter being described (a) Each FF is clocked at the same time (b) Each FF divides the frequency at its CLK input by (c) The counting sequence is 111, 110, 101, 100, 011, 010, 001, 000 (d) The counter has 10 distinct states (e) The total switching delay is the sum of the individual FFs’ delays (f) This counter requires no decoding logic (g) The MOD number is always twice the number of FFs (h) This counter divides the input frequency by its MOD number (i) This counter can begin its counting sequence at any desired starting state (j) This counter can count in any direction (k) This counter can suffer from decoding glitches due to its propagation delays (l) This counter only counts from to (m) This counter can be designed to count through arbitrary sequences by determining the logic circuit needed at each flip-flop’s synchronous control inputs ANSWERS TO OUTCOME ASSESSMENT QUESTIONS PART SECTION 7-1 False 0000 128 SECTION 7-2 Each FF adds its propagation delay to the total counter delay in response to a clock pulse MOD-256 SECTION 7-3 Can operate at higher clock frequencies and has more complex circuitry Six FFs and four AND gates ABCDE www.downloadslide.net 567 ANSWERS TO OUTCOME ASSESSMENT QUESTIONS SECTION 7-4 D, C, and A True, because a BCD counter has 10 distinct states kHz SECTION 7-5 In an up counter, the count is increased by with each clock pulse; in a down counter, the count is decreased by with each pulse Change connections to respective inverted outputs instead of Qs SECTION 7-6 It can be preset to any desired starting count Asynchronous presetting is independent of the clock input, while synchronous presetting occurs on the active edge of the clock signal SECTION 7-7 LOAD is the control that enables the parallel loading of the data inputs D C B A 1A = LSB2 CLR is the control that enables the resetting of the counter to 0000 True All control inputs 1CLR, LOAD, ENT, and ENP2 on the 74162 must be HIGH LOAD = 1, CTEN = 0, and D> U = to count down 74HC163: to 65,535; 74ALS190: to 9999 or 9999 to SECTION 7-8 Sixty-four A six-input NAND gate with inputs A, B, C, D, E, and F SECTION 7-9 We will not have to deal with transient states and possible glitches in output waveforms PRESENT state/NEXT state table The gates control the count sequence Unused states all lead back to the count sequence of the counter SECTION 7-10 See text It associates every possible PRESENT state with its desired NEXT state It shows the necessary levels at each flip-flop’s synchronous input to produce the counter’s state transitions True SECTION 7-11 Arithmetic Use the MegaWizard Manager An asynchronous clear will occur as soon (after a short propagation delay) as the control signal goes active while a synchronous clear will occur at the next clock edge after asserting the control Cout will automatically decode the last (or terminal) state in the count sequence Cin will also enable/disable the cout signal SECTION 7-12 PRESENT state/NEXT state tables The desired NEXT state AHDL: ff[ ].clk = !clock VHDL: IF (clock = '0' AND clock'EVENT) THEN Behavioral description Asynchronous clear causes the counter to clear immediately Synchronous load occurs on the next active clock edge AHDL: Use clrn port on FFs; VHDL: Define clear function before checking for clock edge By the order of evaluation in an IF statement SECTION 7-13 Both HDLs can use a block diagram to connect modules; VHDL can also use a text file that describes the connections between components A bus is a www.downloadslide.net 568 CHAPTER 7/COUNTERS AND REGISTERS collection of signal lines; it is represented graphically by a heavy-weight line Count enable and terminal count decoding SECTION 7-14 A counter is commonly used to count events, while a state machine is commonly used to control events A state machine can be described using symbols to describe its states rather than actual binary states The compiler assigns the optimal values to minimize the circuitry The description is much easier to write and understand PART SECTION 7-16 Parallel in/serial out True Serial in/parallel out Serial in/ serial out The 74165 uses asynchronous parallel data transfer; the 74174 uses synchronous parallel data transfer A HIGH prevents shifting on CPs Compare to corresponding outputs in the figure SECTION 7-17 Ring counter Johnson counter connected to the input of the first FF Sixteen; eight The inverted output of the last FF is (a)False (b) True (c) True SECTION 7-19 PIPO, SISO, PISO, SIPO (all 4) SECTION 7-20 AHDL: reg[].d = (reg[6 0], dat) VHDL: reg: = reg(6 DOWNTO 0) & dat Because the register may continue to receive clock edges during hold SECTION 7-21 It can start in any state, but it will eventually reach the desired ring sequence Lines 11 and 12 Lines 12 and 13 SECTION 7-22 The reset input The clock frequency and the delay value loaded into the counter Synchronously The output pulse width is very consistent The output pulse responds to the trigger edge immediately The state of the trigger on the current clock edge and its state on the previous edge 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Expression 18 0 www.downloadslide.net 13 CONTENTS 4-6 4-7 4-8 4-9 4 -1 0 4 -1 1 4 -1 2 4 -1 3 4 -1 4 4 -1 5 4 -1 6 4 -1 7 Don’t-Care Conditions 18 1 Summary 18 3 Exclusive-OR and Exclusive-NOR Circuits 18 3 Exclusive-OR 18 3... stored 10 1 10 1 10 1 11 0 11 0 10 00 11 0 11 0 11 1 10 00 11 1 11 1 11 1 (a) Sampled every hour 90 80 70 60 50 40 30 20 10 Sampled every hour 0 10 15 (b) Sampled every hours 80 70 60 50 40 30 20 10 Sampled... 74ALS16 0 -1 63/74HC16 0 -1 63 Series 450 The 74ALS19 0 -1 91/ 74HC19 0 -1 91 Series 454 Multistage Arrangement 459 7 -1 3 7 -1 4 7 -1 5 7 -1 6 7 -1 7 7 -1 8 7 -1 9 Decoding a Counter 460 Active-HIGH Decoding 4 61 Active-LOW