Digital systems - Principles and applications (20/e): Part 2

Part 2 ebook “Digital systems - principles and applications” has contents: msi logic circuits, integrated-circuit logic families, digital system projects using hdl, interfacing with the analog world, memory devices, programmable logic device architectures.

www.downloadslide.net C H A P T E R integrated-circuit logic families ■ outline 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 Digital IC Terminology The TTL Logic Family TTL Data Sheets TTL Series Characteristics TTL Loading and Fan-Out Other TTL Characteristics MOS Technology Complementary MOS Logic CMOS Series Characteristics Low-Voltage Technology Open-Collector/Open-Drain Outputs 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 Tristate (Three-State) Logic Outputs High-Speed Bus Interface Logic CMOS Transmission Gate (Bilateral Switch) IC Interfacing Mixed-Voltage Interfacing Analog Voltage Comparators Troubleshooting Characteristics of an FPGA www.downloadslide.net ■ chaPter outcomes Upon completion of this chapter, you will be able to: ■ Read and understand digital IC terminology as specified in manufacturers’ data sheets ■ Compare the characteristics of standard TTL and the various TTL series ■ Determine the fan-out for a particular logic device ■ Use logic devices with open-collector outputs ■ Analyze circuits containing tristate devices ■ Compare the characteristics of the various CMOS series ■ Analyze circuits that use a CMOS bilateral switch to allow a digital system to control analog signals ■ Describe the major characteristics of and differences among TTL, ECL, MOS, and CMOS logic families ■ Describe the various considerations that are required when interfacing digital circuits from different logic families ■ Use voltage comparators to allow a digital system to be controlled by analog signals ■ Use a logic pulser and a logic probe as digital circuit troubleshooting tools ■ introduction As we described in Chapter 4, digital IC technology has advanced rapidly from small-scale integration (SSI), with fewer than 12 gates per chip; through medium-scale integration (MSI), with 12 to 99 equivalent gates per chip; on to large-scale and very large scale integration (LSI and VLSI, respectively), which can have tens of thousands of gates per chip; and to ultra-large-scale integration (ULSI), with over 100,000 gates per chip, and giga-scale integration (GSI), with million or more gates Most of the reasons that modern digital systems use integrated circuits are obvious ICs pack a lot more circuitry in a small package, so that the overall size of almost any digital system is reduced The cost is dramatically reduced because of the economies of mass-producing large volumes of similar devices Some of the other advantages are not so apparent ICs have made digital systems more reliable by reducing the number of external interconnections from one device to another Before we had ICs, every circuit connection was from one discrete component (transistor, diode, resistor, etc.) to another Now most of the connections are internal to the ICs, where they are protected from poor soldering, breaks or shorts in connecting paths on a circuit board, and other physical problems ICs have also drastically reduced the amount of electrical power needed to perform a given function because their miniature circuitry typically requires less power than their discrete counterparts In addition to the 571 www.downloadslide.net 572 CHAPTER 8/INTEGRATED-CIRCUIT LOGIC FAMILIES savings in power-supply costs, this reduction in power has also meant that a system does not require as much cooling There are some things that ICs cannot They cannot handle very large currents or voltages because the heat generated in such small spaces would cause temperatures to rise beyond acceptable limits In addition, ICs cannot easily implement certain electrical devices such as inductors, transformers, and large capacitors For these reasons, ICs are principally used to perform low-power circuit operations that are commonly called information processing That is precisely the job of the digital logic circuits that we have been studying The digital circuit will make decisions based on the input conditions that are present When devices that require higher power levels must be controlled by a logic circuit, some type of interfacing circuit will be needed The interfacing circuit will typically use discrete components or special power IC chips With the widespread use of ICs comes the necessity to know and understand the electrical and timing characteristics of the most common IC logic families Remember that the various logic families differ in the major components that they use in their circuitry TTL and ECL use bipolar transistors as their major circuit element; PMOS, NMOS, and CMOS use unipolar MOSFET transistors as their principal component These various logic families have differing electrical characteristics that must be considered when designing digital systems The electrical characteristics of a logic family are dependent upon both the transistor type and on the internal circuits of the chips Numerous digital IC subfamilies have been developed over time to provide improvements in system power consumption and speed We have seen a continuous (and continuing) evolution from high-power/ low-speed devices to high-speed/low-power chips In this chapter, we will present the important characteristics of each of the IC families and their subfamilies The most important point is understanding the nature of the input circuitry and output circuitry for each logic family Once these are understood, you will be much better prepared to analysis, troubleshooting, and some design of digital circuits that contain any combination of IC families We will study the inner workings of devices in each family with the simplest circuitry that conveys the critical characteristics of all members of the family 8-1 digital ic terminology outcomes Upon completion of this section, you will be able to: ■ Define, interpret, and measure commonly used parameters and parameter designations from data sheets ■ Look up and interpret performance information from data sheets Although there are many digital IC manufacturers, much of the nomenclature and terminology is fairly standardized The most useful terms are defined and discussed below Current and voltage Parameters (See Figure 8-1) ■ ViH(min)—High-Level input voltage The minimum voltage level required for a logical at an input Any voltage below this level will not be accepted as a HIGH by the logic circuit www.downloadslide.net 573 SECTION 8-1/DIGITAL IC TERMINOLOGY HIGH IOH IIH VOH VIH (a) FiGurE 8-1 LOW 15 V IOL IIL VOL VIL (b) Currents and voltages in the two logic states ■ ■ ■ ■ ■ ■ ■ ViL(max)—Low-Level input voltage The maximum voltage level required for a logic at an input Any voltage above this level will not be accepted as a LOW by the logic circuit VOH(min)—High-Level Output voltage The minimum voltage level at a logic-circuit output in the logical state under defined load conditions VOL(max)—Low-Level Output voltage The maximum voltage level at a logic-circuit output in the logical state under defined load conditions IiH—High-Level input Current The current that flows into an input when a specified high-level voltage is applied to that input IiL—Low-Level input Current The current that flows into an input when a specified low-level voltage is applied to that input IOH—High-Level Output Current The current that flows from an output in the logical state under specified load conditions IOL—Low-Level Output Current The current that flows from an output in the logical state under specified load conditions Note: The actual current directions may be opposite to those shown in Figure 8-1, depending on the logic family All descriptions of current flow in this text refer to conventional current flow (from higher potential to lower potential) In keeping with the conventions of most data books, current flowing into a node or device is considered positive, and current flowing out of a node or device is considered negative Fan-Out In general, a logic-circuit output is required to drive several logic inputs Sometimes all ICs in the digital system are from the same logic family, but many systems have a mix of various logic families The fan-out (also called loading factor) is defined as the maximum number of logic inputs that an output can drive reliably For example, a logic gate that is specified to have a fan-out of 10 can drive 10 logic inputs If this number is exceeded, the output logic-level voltages cannot be guaranteed Obviously, fan-out depends on the nature of the input devices that are connected to an output Unless a different logic family is specified as the load device, fanout is assumed to refer to load devices of the same family as the driving output www.downloadslide.net 574 CHAPTER 8/INTEGRATED-CIRCUIT LOGIC FAMILIES Propagation Delays A logic signal always experiences a delay in going through a circuit The two propagation delay times are defined as follows: ■ ■ tPLH Delay time in going from logical to logical state (LOW to HIGH) tPHL Delay time in going from logical to logical state (HIGH to LOW) Figure 8-2 illustrates these propagation delays for an INVERTER Note that tPHL is the delay in the output’s response as it goes from HIGH to LOW It is measured between the 50% points on the input and output transitions The tPLH value is the delay in the output’s response as it goes from LOW to HIGH FiGurE 8-2 delays Propagation Input 50% t Output 50% tPHL tPLH In some logic circuits, tPHL and tPLH are not the same value, and both will vary depending on capacitive loading conditions The values of propagation times are used as a measure of the relative speed of logic circuits For example, a logic circuit with values of 10 ns is a faster logic circuit than one with values of 20 ns under specified load conditions Power requirements Every IC requires a certain amount of electrical power to operate This power is supplied by one or more power-supply voltages connected to the power pin(s) on the chip labeled VCC (for TTL) or VDD (for MOS devices) The amount of power that an IC requires is determined by the current, ICC (or IDD), that it draws from the VCC (or VDD) supply, and the actual power is the product ICC * VCC (or IDD * VDD) For many ICs, the current drawn from the supply varies depending on the logic states of the circuits on the chip For example, Figure 8-3(a) shows a NAND chip where all of the gate outputs are HIGH The current drain on the VCC supply for this case is called ICCH Likewise, Figure 8-3(b) shows the current when all of the gate outputs are LOW This current is called ICC L The values are always measured with the outputs open circuit (no load) because the size of the load will also have an effect on ICC H In some logic circuits, ICCH and ICCL will be different values For these devices, the average current is computed based on the assumption that gate outputs are LOW half the time and HIGH half the time ICCH + ICCL This equation can be rewritten to calculate average power dissipated: ICC1avg2 = PD1avg2 = ICC1avg2 * VCC www.downloadslide.net 575 SECTION 8-1/DIGITAL IC TERMINOLOGY FiGurE 8-3 ICCH and ICCL 1VCC 1VCC ICCH ICCL 1 1 1 0 1 1 1 0 1 1 1 (a) (b) Noise immunity Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits These unwanted, spurious signals are called noise and can sometimes cause the voltage at the input to a logic circuit to drop below VIH(min) or rise above VIL(max), which could produce unpredictable operation The noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise without causing spurious changes in the output voltage A quantitative measure of noise immunity is called noise margin and is illustrated in Figure 8-4 Figure 8-4(a) is a diagram showing the range of voltages that can occur at a logic-circuit output Any voltages greater than VOH(min) are considered a logic 1, and any voltages lower than VOL(max) are considered a logic Voltages in the disallowed range should not appear at a logic-circuit output under normal conditions Figure 8-4(b) shows the voltage requirements at a logic-circuit input The logic circuit responds to any input greater than VIH(min) as a logic 1, and it responds to voltages lower than VIL(max) as a logic Voltages in the indeterminate range produce an unpredictable response and should not be used DC noise VOH (min) VNH VIH (min) Indeterminate range Disallowed range VOL (max) VNL VIL (max) Logic Logic Output voltage ranges Input voltage requirements (a) (b) Voltage Logic Logic Voltage FiGurE 8-4 margins www.downloadslide.net 576 CHAPTER 8/INTEGRATED-CIRCUIT LOGIC FAMILIES The HIGH-state noise margin VNH is defined as VNH = VOH1min2 - VIH1min2 (8-1) and is illustrated in Figure 8-4 VNH is the difference between the lowest possible HIGH output and the minimum input voltage required for a HIGH When a HIGH logic output is driving a logic-circuit input, any negative noise spikes greater than VNH appearing on the signal line can cause the voltage to drop into the indeterminate range, where unpredictable operation can occur The LOW-state noise margin VNL is defined as VNL = VIL1max2 - VOL1max2 (8-2) and it is the difference between the largest possible LOW output and the maximum input voltage required for a LOW When a LOW logic output is driving a logic input, any positive noise spikes greater than VNL can cause the voltage to rise into the indeterminate range EXAMPLE 8-1 The input/output voltage specifications for the standard TTL family are listed in Table 8-1 Use these values to determine the following (a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input (b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input TAbLE 8-1 I/O voltage specifications Parameter VOH Min (V) Typical (V) Max (V) 2.4 0.2 VOL VIH 3.4 0.4 2.0* VIL 0.8* *Normally only the minimum VIH and maximum VIL values are given Solution (a) When an output is HIGH, it may be as low as VOH1min2 = 2.4 V The minimum voltage that an input responds to as a HIGH is VIH1min2 = 2.0 V A negative noise spike can drive the actual voltage below 2.0 V if its amplitude is greater than VNH = VOH1min2 - VIH1min2 = 2.4 V - 2.0 V = 0.4 V (b) When an output is LOW, it may be as high as VOL1max2 = 0.4 V The maximum voltage that an input responds to as a LOW is VIL1max2 = 0.8 V A positive noise spike can drive the actual voltage above the 0.8-V level if its amplitude is greater than VNL = VIL1max2 - VOL1max2 = 0.8 V - 0.4 V = 0.4 V www.downloadslide.net 577 SECTION 8-1/DIGITAL IC TERMINOLOGY invalid voltage Levels For proper operation the input voltage levels to a logic circuit must be kept outside the indeterminate range shown in Figure 8-4(b); that is, they must be either lower than VIL(max) or higher than VIH(min) For the standard TTL specifications given in Example 8-1, this means that the input voltage must be less than 0.8 V or greater than 2.0 V An input voltage between 0.8 and 2.0 V is considered an invalid voltage that will produce an unpredictable output response, and so must be avoided In normal operation, a logic input voltage will not fall into the invalid region because it comes from a logic output that is within the stated specifications However, when this logic output is malfunctioning or is being overloaded (i.e., its fan-out is being exceeded), then its voltage may be in the invalid region Invalid voltage levels in a digital circuit can also be caused by power-supply voltages that are outside the acceptable range It is important to know the valid voltage ranges for the logic family being used so that invalid conditions can be recognized when testing or troubleshooting Current-Sourcing and Current-Sinking Action Logic families can be described according to how current flows between the output of one logic circuit and the input of another Figure 8-5(a) illustrates current-sourcing action When the output of gate is in the HIGH state, it supplies a current IIH to the input of gate 2, which acts essentially as a resistance to ground Thus, the output of gate is acting as a source of current for the gate input We can think of it as being like a faucet that acts as a source of water FiGurE 8-5 Comparison of current-sourcing and current-sinking actions 1VCC LOW Load gate Current sourcing VOH IIH LOW Driving gate supplies (sources) current to load gate in HIGH state Driving gate (a) 1VCC Driving gate HIGH Current sinking VOL HIGH IIL Driving gate receives (sinks) current from load gate in LOW state Load gate (b) Current-sinking action is illustrated in Figure 8-5(b) Here the input circuitry of gate is represented as a resistance tied to +VCC, the positive terminal of a power supply When the gate output goes to its LOW state, current will flow in the direction shown from the input circuit of gate back through the output resistance of gate to ground In other words, in the LOW state, the circuit output that drives the input of gate must be able to sink a current, IIL, coming from that input We can think of this as acting like a sink into which water is flowing www.downloadslide.net 578 CHAPTER 8/INTEGRATED-CIRCUIT LOGIC FAMILIES The distinction between current sourcing and current sinking is an important one, which will become more apparent as we examine the various logic families iC Packages Developments and advancements in integrated circuits continue at a rapid pace The same is true of IC packaging There are various types of packages, which differ in physical size, the environmental and power-consumption conditions under which the device can be operated reliably, and the way in which the IC package is mounted to the circuit board Figure 8-6 shows seven representative IC packages The package in Figure 8-6(a) is the DiP (dual-in-line package), which has been around for a long time Its pins (or leads) run down the two long sides of the rectangular package The device shown is a 24-pin DIP Note the Notch Pins on all four sides Pins on all four sides Chipped corner Pin 13 Pin 32 Pin Pin 12 Pin 13 Pin Pin 12 Pin 33 Pin Pin 24 Pin 48 Pin 28 24-pin DIP 28-pin PLCC (J-lead) socket or surface-mount (a) 48-pin QFP (gull-wing) surface-mount (c) (d) 1.5 mm max Bevel 0.8 mm Pin Pin Pin 16-pin SOIC (gull-wing) surface-mount (b) A B C D E F G H J K L M N P R T A B C D E F G H J K L M N P R T 5.5 mm 13.5 mm 96-pin LFBGA surface-mount (e) FiGurE 8-6 Common IC packages Pin www.downloadslide.net 579 SECTION 8-1/DIGITAL IC TERMINOLOGY 0.9 mm A1 corner U T R P N M L K 15 mm J H G F E D C B A 0.95 mm 0.80 mm 2.1 mm 10 11 12 13 14 15 16 17 15 mm FiGurE 8-6 2.0 mm 208-pin LGA surface-mount 5- or 6-pin SC-70 surface-mount (f) (g) Continued presence of the notch on one end, which is used to locate pin Some DIPs use a small dot on the top surface of the package to locate pin The leads extend straight out of the DIP package so that the IC can be plugged into an IC socket or inserted into holes drilled through a printed circuit board The spacing between pins (lead pitch) is typically 100 mils (a mil is a thousandth of an inch) Nearly all new circuit boards that are produced using automated manufacturing equipment have moved away from using DIP packages whose leads are inserted through holes in the board Current manufacturing methods use surface-mount technology (SMT), which places an IC onto www.downloadslide.net 1010 INDEX Code converters (continued) conversion process, 711–712 other implementations, 714 Codec, 871 Column address strobe (CAS), 926 Combinational logic circuits, 156–254 algebraic simplification, 160–165 complete design procedure, 167–172 complete simplification process, 177–180 designing, 165–172 exclusive-NOR, 183–188 exclusive-OR, 183–188 Karnaugh map method, 172–183 parity generator and checker, 189–190 product-of-sums, 158–159 simplifying, 160–165 sum-of-products form, 158–159 summary, 240–241 Combined addition and subtraction, 397 Combining DRAM chips, 944–945 Command register, 910 Common input/output pins (in RAM), 918–919 Commutative laws, 113 Complementation, 100 (see also NOT operation) Complete hierarchy of the project (digital clock using HDL), 786 Complex programmable logic devices (CPLDs), 964 Computers data acquisition system, 842–844 decision process of a program, 136 digital, 48–51 embedded controller, 50 functional diagram of, 49 major parts of, 48–49 microcomputer, 49 microcontroller, 49 microprocessor, 49 programming languages, 134–137 types of, 49–50 Concatenating, 534 Conditional signal assignment statement, 735 Constants, 414 Contact bounce, 263 Control bus, 896 inputs, 273, 285 synchronous, 273 unit, 49 Controlled inverter, 186 Conversion time, ADC, 841–842, 847 Converter, data, 915 Count enable, 451 Counters and registers, 428–548 asynchronous (ripple), 430–434 propagation delay, 434–436 basic idea, 467 BCD, decoding, 462 cascading, 459–460 decade, 445 decoding, 451, 460–463, 525 design procedure, 469–472 displaying states, 441 feedback, with, 522 glitches, 436, 441 HDL, 480–492 J-K excitation table, 469 Johnson, 523–525 decoding, 525 with MOD numbers _2N, 439–440 multistage arrangement, 459–460 NEXT state, 464–467 parallel in/parallel out (74ALS174/74HC174), 514–516 parallel in/serial out (74ALS165/74HC165), 518–520 PRESENT state, 464–467 presettable, 448–450 recycle, 430 ring, 522–523, 678 ripple, 341–343, 430–434 self-correcting, 465 serial in/parallel out (74ALS164/74HC164), 520–521 serial in/serial out (74ALS166/74HC166), 516–518 74ALS160-163/74HC160-163 series, 450–454 74ALS190-191/74HC190-191 series, 454–458 shift register, 522–526 spike, 441 summary, 512, 548–549 synchronous (parallel), 436–439, 450–454 synchronous (parallel) down and up/down, 446–448 synchronous design, 467–475 synchronous design with D FFs, 474–475 synchronous presetting, 449 synchronous, analyzing, 464–467 transition states, 441 troubleshooting, 526–529 undesired states, 469 with MOD numbers _2N, 439–440 Counting binary, 42–43 decimal, 40–41 hexadecimal, 64 operation, 303–304 CPU, 49 Cross Bar Technology (74CBT), 616 low voltage (74CBTLV), 616 Crystal-controlled clock generators, 322 Current parameters for digital ICs, 572–573 sinking action, TTL, 577, 584 sinking transistor, TTL, 584 sourcing action, 577, 584 sourcing transistor, TTL, 584 transients, TTL, 601–602 D DAC (see Digital-to-analog converter) Data acquisition, 842–846, 869 bus bundle method, 723 defined, 714 floating, 716 operation, 719–725 compression, 870 converter, 915 distributors, 693–703 hold time, 922 lines, 313 rate buffer, 948 routing, by MUXs, 688–689 sampling, 842 selectors, 682–683 setup time, 922 storage and transfer, 296–298 tables, 915 transfer operation, 296 word, 722 Data transfer, 296–298 asynchronous, 296 data busing, 719–720 demultiplexers, 693–703 hold time requirement, 299–300 operation, 719–720 parallel, 282, 297–298 parallel versus serial transfer, 301 www.downloadslide.net INDEX economy and simplicity of, 301 speed, 301 and portability, 914 and storage, 296–298 registers, between, 719 serial, 297 shift registers, 298–301 simulation, full-step, (HDL), 771 simultaneous, 297 synchronous, 297 Decade counters, 445 Decimal counting, 40–41 point, 39 Decimal system, 39–40 binary-to-decimal conversion, 58 conversions, summary, 65–66 decimal-to-binary conversion, 59–61 counting range, 61 decimal-to-hex conversion, 62–63 hex-to-decimal conversion, 62 Decimal-to-BCD priority encoder (74147), 675–676 Decision control structures in HDL, 230–240 Decoders, 659–667 address, 900 applications, 665–666 BCD-to-7 segment drivers, 667–669 BCD-to-decimal, 660 Binary-to-octal, 660 column, 900 demultiplexer, 693–703 ENABLE inputs, 660 4-to-10, 664 liquid crystal displays (LCDs), 668–669 1-of-10, 664 1-of-8, 660–662 row, 900 3-line-to-8-line, 664 using HDL, 725–728 Decoding counters, 460–463 Johnson, counter, 523–525 Decoupling, power-supply TTL, 602 DeMorgan’s theorems, 115–118 implications of, 117–118 Demultiplexers (DEMUXs), 693–703, 736–739 1-line-to-8-line, 694–695 security monitoring system, applications, 695–697 Dependency notation &, 718 ◇, 621 ▽, 625 Depletion MOSFET, 603 Describing logic circuits, 88–155 summary, 144–145 Description languages versus programming languages, 134–137 Designing combinational logic circuits, 165–172 Detecting a transition or event, 295 Detecting an input sequence, 293–294 Development software (for PLDs), 217–219 Diagrams logic circuit connections, 198–199 simplified bus timing, 721 state transition, 304, 441, 465 timing, 465 Differential inputs, 849 Digital, techniques amplitude control, 833–834 and analog systems, 37–39 arithmetic, 360–427 1011 2’s-complement system addition, 371–372 2’s-complement system, multiplication, 377 2’s-complement system, subtraction, 372–375 BCD addition, 377–379 binary addition, 362–363 binary division, 377 binary multiplication, 375–376 carry propagation, 392–393 circuits, 383–384 full adder, 385 hexadecimal addition, 380–381 hexadecimal representation of signed numbers, 382–383 hexadecimal subtraction, 381–382 Integrated-circuit parallel adder, 393–395 number circles and binary arithmetic, 374–375 operations and circuits, 360–427 parallel binary adder, 384–386 signed number representation, 363–370 summary, 417–418 camera, 870 cellular telephone, 870–871 circuits, 28, 34 (see also Logic circuits) computers, 48–51 (see also Microcomputers) family tree, 962–967 integrated circuits, 34 multiplexer, 682–683 number systems, 39–43 one-shots, HDL, 541–548 pulses, 269–270 quantity, 815–816 ramp ADC, 837–839 representation, 35–36 signal processing (DSP), 865–868 architecture, 867 arithmetic logic unit (ALU), 867 barrel shifter, 867 filtering, 866–868 interpolation filtering, 868 multiply and accumulate section (MAC), 867 oversampling, 867 weighted average, 867 techniques advantages, 37 limitations, 38–39 temperature control system, 38 vs analog, review, 815–817 Digital signals, 29–33 duty cycle, 32 edges/events, 32 highs and lows over time, 31 period/frequency, 31–32 periodic/aperiodic, 31 timing, 30 transitions, 32 Digital systems, 37 input internally shorted to ground or supply, 202–203 introductory concepts, 22–55 summary, 51–52 malfunction in internal circuitry, 202 open signal lines, 206–207 open-circuited input or output, 203–205 output internally shorted to ground or supply, 203 output loading, 208 power supply, faulty, 207–208 short between two pins, 205–206 shorted signal lines, 207 tree diagram, 705 troubleshooting, 200–201, 637–638, 679–682, 703–706 prototyped circuits, 210–214 Digital-to-analog converter (DAC), 39, 816–845 accuracy, 830–831 analog output, 818 www.downloadslide.net 1012 INDEX Digital-to-analog converter (DAC) (continued) analog-to-digital conversion, used in, 836–837 applications, 833–834 bipolar, 824 circuitry, 824–829 control, used in, 833 conversion, 817–824 conversion accuracy, 826 current output, with, 826–828 digitizing a signal, 845 full-scale output, 818, 820 input weights, 819–820 integrated circuit (AD7524), 832–833 monotonicity, 831 offset error, 831 output waveform, 820 percentage resolution, 821–822 perfect, 830 R/2R ladder, 828–829 resolution, 820–822 serial, 834 settling time, 831 signal reconstruction, 844 specifications, 829–831 staircase, 820 staircase test, 835 static accuracy test, 835 step size, 820–821 troubleshooting, 834–835 Digitize reconstructing a signal, 842–844 signal, 833, 844–846 Digits, 35, 39 DIMM, 933 Diode, Schottky barrier (SBD), 590 DIP (dual-in-line package), 193 Discrete steps, 35 Displaying counter states, 441 Displays LCD, 668–673 backlit, 669 passive matrix panel, 672 reflective, 669 Super Twisted Nematic (STN), 672 TFT (Thin Film Transistor), 673 Twisted Nematic (TN), 672 LED, 668–669 common-anode, 668–669 common-cathode, 668–669 Distributive law, 113 Divide and conquer, troubleshooting process, 680 Dividend, 377 Division, binary, 377 Divisor, 377 D latch (transparent latch), 282–284, 334 D latch (see Flip-flops) Don’t-care conditions, 181–182 Double Data Rate SDRAM (DDRSDRAM), 934 Driver, decoder, 665 DSP (Digital Signal Processing), 865–868 Dual in-line package (DIP), 580 Dual-in-line package (DIP), 193 Dual-slope ADC, 857–858 Duty cycle, 32, 433–434 DVD player, block diagram, 219 Dynamic RAM (DRAM), 922–923 address multiplexing, 925–928 architecture, simplified, 926 combining chips, 944–945 controller, 932 DDRSDRAM, 934 DIMM, 933 EDO, 934 FPM (Fast Page Mode), 934 memory modules, 933–934 read/write cycles, DRAM, 929–930 read cycle, 929 write cycle, 930 refresh counter, 932 refreshing, 923, 930–932 burst, 931 CAS-before RAS refresh, 931, 932 distributed, 931 RAS-only refresh, 931 SDRAM (Synchronous DRAM), 934 SIMM, 933 simplified architecture of a typical, 926 SODIMM, 933 structure and operation, 924–928 technology, 933–935 E Edge-detector circuit, 277 Edge falling, 29 negative, 29 Edges, of a clock signal, 271–272 Edges/events, 32 Edge-triggered devices, 335–340 event, 335 logic primitive, 335 EDO (Extended Data Output) DRAM, 934 EEPROMs (electrically erasable PROMs), 907–908 Eight-input multiplexers, 684–686 Electrical noise, 76 Electrically Erasable PROMs (EEPROMs), 907–908 Electrostatic discharge (ESD), 613 microcontroller program memory, 914 ELSIF, 235–236 using AHDL, 236 using VHDL, 237 Embedded controller, 50 ENABLE inputs, decoders, 660–664 Enable/Disable circuits, 190–192 Encoders, 672–679 decimal-to-BCD priority, 675–676 8-line-to-3-line, 674 octal-to-binary, 674 priority, 675–676 switch, 676–679 Encoding, 673, 936 Enhancement MOSFET, 603 EPROMs (erasable programmable ROMs), 906–907 Erasable Programmable ROMs (EPROMs), 906–907 Error detection, parity method for, 76–78 Etching, incomplete, 207 Even-parity method, 77 Event, 335 Excitation table, J-K, 468 Exclusive NOR circuit, 185–188 OR circuit, 183–184 Extension, sign, 367–368 External faults, 206–207 F Falling edge, 29 Fan-out, 573 CMOS, 612 determining, 594–597 TTL, 593–598 Fast page mode (FPM) DRAM, 934 Fast TTL (74F), 591 FGMOSFET, 911 www.downloadslide.net 1013 INDEX Field-programmable gate arrays (FPGA), 639–640, 964–967 Altera Cyclone II characteristics using general purpose I/O standards, 640 Altera Cyclone II comparison of counter performance, 641 architecture, 934 characteristics of, 639–641 logic voltage levels, 639–640 maximum input voltage and output current ratings, 641 power dissipation, 640 power-supply voltage, 639 switching speed, 641 Filling K map from output expression, 180–181 First-in, first-out memory (FIFO), 947–948 Flash ADC, 856 conversion time of, 856 memory, 909–913 NAND, 911–912 NOR, 911–912 technology, 911–912 typical CMOS memory IC, typical, 109–911 Flip-flops, 47, 256–359 ambiguous output, 278 applications, 291 with timing constraints, 306–312 asynchronous inputs, 284–287 bistable multivibrator, 259 clearing, 259 clock signals, 271–274 clocked, 271–274 clocked D, 280–282 implementation of, 280 D (data), 280–281 implementation of, 270 D latch (transparent latch), 282–284, 334 defined, 258 edge-triggered, 272 feedback, 258 frequency division and counting, 302–305 input sequence detection, 293–294 J-K, 278–280 latches, 47 memory characteristics, 259 NAND gate latch, 259–264 alternate representations, 262 summary of, 261–262 troubleshooting case study, 267–269 using AHDL, 333 NOR gate latch, 265–267 override inputs, 285 propagation delays, 288 resetting, 259 S-R, 274–277 setting, 259 setup and hold times, 272–274 shift registers, 298–301 state on power-up, 267 summary, 343–344 synchronization, 292–293 terminology, 262 timing considerations, 287–289 timing problems, 289–291, 310–312 transition or event detection, 295 troubleshooting circuits, 322–327 Floating, 197 bus, 716 gate, MOSFETs, 906–908, 911–912 inputs (see also Unconnected inputs) Floating inputs, 197–198 (see also Unconnected inputs) Four-input multiplexers, 684 Free-running multivibrator, 319–322 Frequency, 31–32, 32, 271 counter project (HDL), 805–809 (see also HDL) division, 302–305, 432–433 and counting, 302–305 Full adder, 385 design of, 386–389 K-map simplification, 388 Full-featured counters in HDL, 487–488 Full-scale error (of a DAC), 830 Full-scale output (of a DAC), 818, 820 Full-step sequence (HDL stepper-motor), 768 Function generator, 915 Fusible-link, PROMs, 905 G GAL (Generic array logic), 974–975 output logic macro cells (OLMCs), 974–975 Gate(s) AND, 97–100 arrays, 963–964 NAND, 108–112 NOR, 108–112 NOT (inverter), 100–101 OR, 93–97 propagation delay, 131–132 which representation to use, 125–131 XNOR, 185–188 XOR, 183–184 Generator parity, 189–190 function, 915 Giga-scale integration (GSI), 194, 571 Glitches, 436, 441 Gray Code, 68–70 Gunning Transceivers Logic Plus, 627 Plus (74GTLP), 616 H Half-adder, 389 Half-step sequence (HDL stepper-motor), 768 HDL (hardware description language), 134, 217 adders, 412–414 behavioral description, 484 behavioral level of abstraction, 484 bit arrays, 223–224 bit vectors, 223–224 CASE, 538, 726, 771, 789–790 choosing coding techniques, 511 concatenation, 533 counters, 480–492 circuits with multiple components, 340–343 code converters, 741–744 combining blocks using only, 794–795 comparator, 740–741 decision control structures, 230–240 concurrent, 230 sequential, 230 decoder/driver, 7-segment, 729–732 decoders, using, 725–728 demultiplexers, 736–739 designing number systems in, 222 digital clock project, 781–798 block diagram, 782 building the blocks from the bottom up, 786 combining blocks graphically, 793–794 complete hierarchy of the project, 786 hours section circuit, 782 MOD-6 counter simulation, 787–788 MOD-60 section, 785 prescaler, 785 top-down hierarchical design, 784–786 www.downloadslide.net 1014 INDEX HDL (hardware description language) (continued) encoders, 732–736 format and syntax, 138–141 frequency counter project, 805–809 block diagram, 807 sampling interval, 806 timing and control block, 807 timing diagram, 808 full-featured counters in, 487–488 hierarchical design, 493 IF/ELSE, 231–232, 540 IF/ELSIF, 789 IF/THEN, 231 index, 223 keypad encoder project, 775–781 block diagram, 776 encoder operation, 776 problem analysis, 775 problem decomposition, 777 simulation, 781 strategic planning, 777 literals, 222 magnitude comparator, 740–741 microwave oven project, 798–805 definition of the project, 799–809 encoder/timer input control block, 803 hierarchy showing blocks and signals, 804 integration and testing, 804 magnetron control block, 803 minutes/seconds counter, 801 problem decomposition, 800–804 strategic planning, 800–804 synthesis, 804 system block diagram, 799 TC (terminal count), 802 the 3-digit BCD down counter for minutes and seconds, 802 MOD-12 design, 790–791 MOD-60 graphic block symbol, 794 mode, 139 multiplexers, 736–739 nesting, 774 NEXT, 538–539 one-shots, 541–548 PRESENT, 539 projects using, 764–812 registers, 533–539 representing data, 222–227 retriggerable, edge-triggered one-shots in, 544–545 ring counters, 539–540 scalars, 222 schematic diagram, 139 D latch, 334 NAND latch, 333 simulation of basic counter, 487 simulation of full-featured counter, 491–492 small-project management, 766–767 definition, 766, 799–800 problem decomposition, 766–767, 769–770, 777, 800–804 strategic planning, 766, 769–770, 777, 800–804 synthesis and testing, 767, 770–771, 804 system integration and testing, 767, 804 state transition description methods, 481 stepper motor driver project, 767–775 full-step sequence, 771 half-step sequence, 768–769 problem decomposition, 769–770 problem definition, 768–769 strategic planning, 769–770 synthesis and testing, 770–774 wave-drive sequence, 768 structural level of abstraction, 343 syntax and format, 138–141 TABLE, 726 timing simulation, 221 truth tables, 227–230 type, 139 wiring modules together, 493–500 Hertz, 271 Hexadecimal addition, 380–381 arithmetic, 380–382 number system, 61–66 representation of signed numbers, 382–383 subtraction, 381–382 Hierarchical design, 219 Hierarchy, 784–786 High capacity programmable logic devices (HCPLDs), 964 generations, 978–979 High-speed bus interface logic, 625–626 High-speed CMOS 74HC/HCT, 609 High-state noise margin (VNH), 576 Hold time (tH), 273–274, 287, 299 I IC synchronous counters, 450–460 IEEE/ANSI symbol for open-collector/drain outputs, 621 tristate outputs, 625 IF/ELSE, 231–232 IF/THEN, 231 IF/THEN/ELSE using AHDL, 232–233 Implementing logic circuits with PLDs, 137–138 Implications of DeMorgan’s theorems, 117–118 Incomplete address decoding, 943–944 Indeterminate logic level, 201 voltages, 197 Inhibit circuits, 99 Input currents for standard devices with a supply voltage of V, 631 sequence detection, 293–294 unit, 48 Integrated-circuit logic families, 571–657 ALU(s), 398–402 add operation, 399 AND operation, 400 CLEAR operation, 399 EX-OR operation, 400 expanding the, 401 OR operation, 400 PRESET operation, 400 SUBTRACT operation, 400 basic characteristics, 193–200 bipolar, 194–195 defined, 571–572 interfacing, 629–633 summary, 641 terminology, 572–581 unipolar, 194–195 Integrated-circuit packages, 578–581 ball grid array, 580 common, 578 dual-in-line (DIP), 578, 580 gull-wing, 580 J-shaped leads, 580 land grid array (LGA), 580 lead pitch, 578 low-profile five-pitch ball grid array (LFBGA), 580 plastic leaded chip carrier (PLCC), 580 quad flat pack (QFP), 580 shrink small outline package (SSOP), 580 small outline IC (SOIC), 580 surface-mount technology, 578 www.downloadslide.net 1015 INDEX thin quad flat pack (TQFP), 580 thin shrink small outline package (TSSOP), 580 thin very small outline package (TVSOP), 580 Integrated-circuit parallel adder, 393–395 Integrated-circuit registers, 514–521 parallel in/parallel out (74ALS174/74HC174), 514–515 parallel in/serial out (74ALS165/74HC165), 518–520 serial in/parallel out (74ALS164/74HC164), 520–521 serial in/serial out (74ALS166/74HC166), 516–518 Integrated-circuit shift-register counters, 526 Intellectual property (IP), 967 Interfacing 5-V TTL and CMOS, 631 high-voltage outputs driving low-voltage loads, 634 integrated circuit, 629–633 logic ICs, 630 low-voltage outputs driving high-voltage loads, 634 mixed-voltage, 634–635 not needed, 630 required, 630 with the analog world, 814–885 summary, 872–873 Intermediate signals, 132–133 Interpolation filtering, 868 Introduction to digital 1s and 0s, 24–28 Introductory concepts, 22–55 Invalid voltage levels, 577 Inversion, 100–101 (see also NOT operation) Inverted flip-flop output, 258 Inverter, 101 circuits containing, 103–104 controlled inverter, 186 response to slow noisy inverter, 315 Inverting tristate buffer, 623 J J-K excitation table, 468 J-K flip-flops, 278–280 J-lead packages, standard memory, 933 Jam transfer, 297, 449 JEDEC standard, 217 JTAG interface, 217, 975 Johnson counter, 523–525 decoding, 525 K Karnaugh map complete simplification process, 177–180 don’t-care conditions, 181–182 filling from output expression, 180–181 format, 172–174 looping, 174–177 method, 172–183 simplification, 388 summary, 183 L Labeling active-LOW signals, 130 bistate signals, 130–131 Ladder, R/2R, 828–829 Land grid array (LGA), 580 Large-scale integration (LSI), 194, 571 Latches, 47, 259–269, 282–284 (see also Flip-flops) resetting, 261 S-R, 262 setting, 261 Latch-up, 614 Latency, 927 Least significant bit (LSB), 42 Least-significant digit (LSD), 39 Level triggered, 32 Libraries of parameterized modules (LPMs), 328 Light-emitting diodes (LEDs), 668–669 common-anode vs common-cathode, 668–669 Limitations of digital techniques, 38–39 Linear buffers, 948 Linearity error (of a DAC), 830 Liquid crystal displays (LCDs), 669–672 backplane, 670 driving a, 670–671 types, 671–673 Loading factor, 573 TTL, 593–598 Local signals,VHDL, 143 Logic diagram using Quartus II schematic capture, 199 function generation, 692–693 level, 91 primitive, 335 probe, how to use, 201, 637–638 pulser, how to use, 201, 637–638 standard, (PLD), 964 states, 25 Logic circuits analysis using a table, 105–106 analyzing, 128–130 and technology, 33–34 arithmetic, 383–384 connection diagrams, 198–199 defined, 33 describing, 88–155 algebraically, 102–104 disabled, 190–192 enabled, 190–192 evaluation of outputs, 104–106 implementing from Boolean expressions, 107–108 implementing with PLDs, 137–138 interface, 629–633 pulse-shaping circuit, 433 pulse-steering, 192 Logic gates, 91–155 alternate representation, 122–125 AND, 98 Boolean theorems, 112–115 DeMorgan’s theorems, 115–118 evaluation of outputs, 104–106 NAND, 108–112 NOR, 108–112 NOT circuit (INVERTER), 101 OR, 94–97 summary of methods to describe, 132–134 truth tables, 92–93 which representation to use, 125–131 XNOR, 185–188 XOR, 183–184 Logic operations, 91 on bit arrays with HDLs, 410–411 Logic signals labeling active-LOW, 130 labeling bistate, 130–131 Logic symbol interpretation, 124 summary, 125 Logical complementation or inversion (NOT operation), 100–101 Look-ahead carry, 393 Look-up table (LUT), 965 Looping, 174–177 octets, 176–177 pairs, 174–175 quads, 175–176 www.downloadslide.net 1016 INDEX Low-voltage (74LV), 616 BiCMOS Technology (74LVT), 616 CMOS (74LVC), 615–616 series characteristics, 616 voltage technology, 614–617 Low-power Schottky TTL 74LS series (LS-TTL), 591 Low-state noise margin (VNL), 576 Low-voltage differential signaling (LVDS), 627 LPMs, 328 LUT (Look-up table), 965 functional block diagram, 977 LVDS (low-voltage differential signaling), 627 M Machines, state, 501–512 Macrofunction, 404 Magnetic storage, 935–936 Magnetoresistive RAM, 936 Magnitude comparator, 707–710, 740–741 applications, 709 cascading inputs, 708–709 data inputs, 708 outputs, 708 Magnitude of binary numbers, 364 Major parts of a computer, 48–49 Mask-Programmed gate arrays (MPGAs), 963 ROM (MROM), 905 Maximum clocking frequency (fMAX), 288 Maxplus2 functions, VHDL, 226 Mealy model, 501 Medium-scale integration (MSI), 194, 571 Megafunction LPMs for arithmetic circuits, 405–406 Megafunction registers, 529–532 MegaWizard settings, 529–530 Memory, 47, 884–959 auxiliary, 888, 891 bipolar NMOS and CMOS static RAM cells, 919–920 bootstrap, 914 cache, 891, 946–947 capacity, 889 cell, 889 CMOS static RAM cell, 920 compact disk, 888 connections, CPU, 895–897 density, 889 devices, 886–959 dynamic, devices, 891 embedded microcontroller program, 914 enable, 893 expanding capacity, 937–945 expanding word size, 937–945 fetch operation, 890 first-in, first-out (FIFO), 947–948 flash, 909–913 architecture, NAND, 913 bulk erase, 909 command register, 910 functional diagram, 911 IC, typical CMOS flash memory, 910–911 NAND, 911–912 NOR, 911–912 sector erase, 909 tradeoffs, 909 fold-back, 944 general operation, 892–895 magnetoresistive random access (MRAM), 936 main, 888, 891 map, 944 mass, 888, 914 module, 945 modules, DRAM, 933–934 NMOS static RAM cell, 920 nonvolatile, 890–891, 897 other technologies blu-ray, 936–937 magnetic storage, 935–936 optical, 936–937 random-access (RAM), 890 read-only (ROM), 891 read/write, 891 sequential-access, 890–891 special functions, 945–948 cache memory, 946–947 first-in, first-out, 947–948 static, devices, 891 store operation, 890 summary, 948–949 terminology, 888–891 unit, 48 volatile, 890 word, 890 working, 888, 891 Metastable states, 273, 312 Microcomputer application, 313–314 defined, 49 input unit, 48 memory unit, 48 output unit, 49 Microcontroller, 49 Microprocessor, 49 Digital signal processing (DSP), 962–963 READ operation, 896 WRITE operation, 896 Minuend, 373 Mixed systems, digital and analog, 37–39 Mixed-voltage interfacing, 634–635 high-voltage outputs driving low-voltage loads, 634–635 low-voltage outputs driving high-voltage loads, 634 voltage-level translator, 634 MOD number, 304, 432 changing, 441 general procedure, 443–444 Johnson counter, 523–525 ring counter, 522–523 Monostable multivibrator, 316–319 (see also One-shot) Monotonicity (of a DAC), 831 Moore model, 501 simulation of, 504–505 traffic light controller, 505–508 MOS electrostatic discharge (ESD), 613 FETs, 602–605 logic family, 602–605 NMOS, 603–605 static sensitivity, 613–614 MOS Floating-gate, 911 MOSFET, 602–605 basic switch, 603–604 CMOS, 606–608 digital circuits, 603–604 FGMOSFET, 911 N-MOS, 603 P-MOS, 605 Most significant bit (MSB), 42 Most significant digit (MSD), 39 MSI logic circuits BCD-to-7 segment decoder/drivers, 667–668 BCD-to-decimal decoder, 664 data busing, 712–713 decoders, 659–667 demultiplexers (DEMUXs), 693–703 encoders, 673–679 liquid crystal displays (LCDs), 669–672 www.downloadslide.net 1017 INDEX multiplexers (MUX), 682–693 summary, 744–745 tristate registers, 718–719 Multiple-emitter input transistor, 581 Multiplexers (MUX), 682–693, 736–739 applications, 688–693, 709–710 control sequence, seven-step, 691 eight-input, 684–685 four-input, 684 operation sequencing, using, 689–692 quad two-input, 686–687 time division, 699–703 two-input, basic, 683–684 Multiplexing ADC, 864–865 address (in DRAM), 925–928 Multiplication in the 2’-complement system, 377 of binary numbers, 375–376 N NAND gate, 108–112 alternate representation, 122–125 CMOS, 607 counter decoding, 460–463 defined, 110 internal circuitry of the edge-triggered J-K FF, 279–280 internal circuitry of the edge-triggered S-R FF, 276–277 latch flip-flop, 259–264 TTL, 581 universality of, 119–122 which representation to use, 125–131 Negation, 367–368 Negative edge, 29 Negative-going threshold voltage (VT-), 314–316 Negative-going transition (NGT), 271 NEXT state, 464–467 Nibble, 72–73 Nios® II, 967 NMOS logic circuits, 603 NMOS static RAM cell, 920 Noise, 37, 323 immunity, 575 Noise margin, 575 CMOS, 611 DC, 575 Nonretriggerable one-shot, 316–317 Nonvolatile memory, 906–907, 909, 914 NOR gate, 108–112 alternate representation, 122–125 CMOS, 607–608 defined, 108 latch, 265–267 NMOS, 603 universality of, 119–122 which gate representation to use, 125–131 Normal flip-flop output, 258 NOT circuit (INVERTER), 100–101 alternate representation, 122–125 circuits containing, 103–104 controlled inverter, 186 defined, 101 DeMorgan’s theorems, 115–118 implementing from Boolean expressions, 107–108 symbol, 101 which representation to use, 125–131 NOT operation, 91, 100–101 Number circles and binary arithmetic, 374–375 Number systems, 39–43 (see also Binary system) and codes, 56–87 applications, 79–81 binary, 41–42 decimal, 39–40 (see also Decimal system) digital, 39–43 hexadecimal, 61–66 summary, 81 Numerical representations, 34–36 O Observation/analysis, troubleshooting process, 680 Octal-to-binary encoders, 674 Octets, looping, 176–177 Odd-parity method, 77 Offset error, 831 1’s-complement form, 364 One-shot (monostable multivibrator), 316–319 actual devices, 318 AHDL, 542, 545–546 HDL, 541–548 retriggerable, edge-triggered in HDL, 544–545 VHDL, 543–545, 546–548 One-time programmable ROM (OTP), 906, 965 Open-collector buffer/drivers, 620–621 outputs, 617–621 Open-collector buffer/drivers, 620–621 Open-drain buffer/drivers, 620–621 outputs, 617–621 Operation fetch, 890 refresh, 891 Operational amplifier (in a DAC), 825 Optical memory, 936–937 OR gate, 94–97 alternate logic-gate representation, 122–125 Boolean theorems, 112–115 defined, 94 implementing from Boolean expressions, 107–108 symbol, 94 OR operation, 94–97 summary, 95–96 which representation to use, 125–131 Organizational hierarchical chart, 220 Oscillator, Schmitt-trigger, 319 OTP (one-time programmable ROM), 906, 965 Output buffers, ROM, 900 currents for standard devices with a supply voltage of V, 631 enable (OE), 894 enable time (tOE), 902 loading, 208 unit, 49 Overflow bit, 389 Override inputs, 285 P Pairs, looping, 174–175 Parallel loading, 448 parallel in/parallel out 74ALS174/74HC174, 514–516 parallel in/serial out 74ALS165/74HC165, 518–520 parallel-to-serial conversion, 689 transmission, 45–47 Parallel binary adder, 384–386 2’s-complement circuits, 395–398 carry propagation, 392–393 complete, with registers, 389–391 integrated circuits, 393–395 troubleshooting case study, 402–404 Parallel data transfer, 282, 297–298 versus serial transfer, 301 www.downloadslide.net 1018 INDEX Parallel and serial transmission, 45–47 trade-offs between, 46 Parameterizing the bit capacity of a circuit, 414–417 Parasitic, 614 Parity bit, 77–78 checker, 189–190 checking, 77, 189 errors single-bit, 77 two-bit, 77 generation, 189 generator, 189–190 method for error detection, 76–78 Percentage resolution, 821–822 Period, 31–32, 32, 271 periodic digital signals, 31 Pipeline ADC, 860–862 PIPO (parallel in/parallel out), 514 PISO (parallel in/serial out), 513 PISO register, AHDL, 535–536 PISO register, VHDL, 535–538 Pixels, 672 Plastic leaded chip carrier (PLCC), 580 Positional-value system, 39 Positive-going threshold voltage (VT+), 314 Positive-going transition (PGT), 271 Power down (in MROM), 905 requirements for digital ICs, 574–575 supply decoupling, TTL, 602 Precision reference supply, 826 Prescaler (digital clock using HDL), 785 PRESENT state, 464–467 PRESET, 285 Presettable counters, 448–450 Priority encoders, 675 Problem decomposion, (using HDL), 766, 769–770, 777 Product-of-sums, 158–159 Program, defined, 37, 48 Programmable Logic Devices (PLDs), 135, 214–222, 327–328, 960–981 architecture/s, 970–975 FPGA (see Field-programmable gate arrays) FPLA (field-programmable logic array), 974 programmable array logic (PAL), 965, 971–974 PROMs, 970–971 summary, 979 CPLD, 964 design and development process, 220–221 test vectors, 220 top-down, 220 development cycle flowchart, 221 development software, 217–219 AHDL, 218 compilers, 137 timing simulation, circuit described in HDL, 221 VHDL, 218 examples of, 963–967 FPGA (see Field-programmable gate arrays) fundamentals of PLD circuitry, 968–970 generic array logic (GAL), 974–975 hardware, 215–216 HCPLD, 964 hierarchical design, 219 look-up table (LUT), 971 macrocell, 965 mask-programmed gate arrays (MPGAs), 961 maxplus2 megafunction, 327–328 more on, 964–967 one-time programmable (OTP), 965 organizational hierarchical chart, 220 primitives, 327 product lines, 968 programmable array logic (PAL), 965 programmer, 217 programming, 216–217, JEDEC standard 217 development board, 217 JTAG, 217 zero insertion force socket (ZIF), 216–217 sequential circuits using schematic entry, 327–330 SPLD, 964–965 standard J lead memory packaging, 933 symbology, 969 universal, 217 Programmable ROMs (PROMs), 905–906 Programmer, 217 Programming languages, computer, 135–136 Projects, using HDL, 764–812 digital clock, 781–798 frequency counter, 805–799 keypad encoder, 775–781 management, 766–767 microwave oven, 798–805 stepper motor driver, 767–775 Propagation delay(s), 131 flip-flop, 288 in asynchronous counters, 434–436 integrated circuits, 574–575 TTL NAND gate, 588 Pull-down transistor, TTL, 584 Pull-up transistor, TTL, 584 Pulse(s), 269–270 leading edge, 269 negative, 269–270 positive, 269–270 shaping circuit, 433 steering circuit, 192, 277 trailing edge, 269 Q Quad flat pack (QFP), 580 two-input multiplexers, 686 Quad looping, 175–176 Quadrature encoders, 70–71, 294, 306–312 Quantization error, 840–841 Quartus II, 135 decoders, 661–662 magnitude comparator, 710 maxplus2 library, 529 mux, 682–683 schematic capture, 199 Quartz crystal, 322 watch, 303 Quasi-stable state, 316 R R/2R ladder digital-to-analog converters, 828–829 RAMs (random-access memories) architecture, 917–919 capacity expansion, 940–943 defined, 890 dynamic devices, 891 magnetoresistive, 936 power-up self-test, 977–978 semiconductor, 916 static (SRAM), 919–922 word size expansion, 937–945 Read operation CPU, 896 defined, 918 RAM, 916 Read/Write memory (RWM), 891 www.downloadslide.net INDEX 1019 Reconstructing a digitized signal, 844–845 Reflective LCDs, 669–670 Refresh counter, 932 Refreshing, DRAM, 923, 930–932 Register array, 900 Registers, 296, 428–548 accumulator, 384 address pointer, 947 and counters, 428–548 complete parallel adder with, 389–391 data transfer, 513 HDL, 533–539 megafunction, 529–532 notation, 390–391 sequence of operations, 391 shift left operation, 301 tristate (74ALS173/HC173), 718–719 Repeated division method, 59–60 Representing binary quantities, 43–45 data in HDL, 222–227 signed numbers, 363–370 using 2’s-complement, 365–366 RESET, 285 Resetting a flip-flop, defined, 261 Resolution, 820–823 ADC, 840–842 DAC, 820–821, 830 Resolution, percentage, 821–822 Retriggerable one-shot, 317 Ring counter, 522–523, 678 in circuit, 678 starting a, 522 state diagram, of, 522, 777 ROM (read-only memory), 897–899 applications, 914–916 architecture, 899 output buffers, 900–901 block diagram, 897–898 burning-in, 897 column decoder, 899 defined, 900–901 erased, 897 mask-programmed, 903–905 one-time programmable (OTP), 906 programming, 897 READ operation, the, 898 row decoder, 899 timing, 901–902 types of, 902–908 Row address strobe (RAS), 926 Run length limited (RLL) encoding, 936 Sequential circuit design, 467–475 Sequential circuits, 291 design, 467–475 in PLDs using schematic entry, 327–330 using HDL, 331–334 using schematic entry, 327–330 Sequential logic systems, troubleshooting, 526 Serial ADCs, 846 serial in/serial out, 74ALS166/74HC166, 516–518 transmission, 45–47 Serial data transfer, 298–301 between registers, 300 Sets, HDL, 410 Setting the flip-flop and resetting simultaneously, 261 latch, 261 Setup time (tS), 272–274, 287 74 TTL series, 590, 591 74AC series, 196, 609 74ACT series, 196, 609 74AHC series, 609 74AHCT series, 609 74ALB series, 616 74ALS TTL series, 591–592 74ALVC series, 615 74ALVT series, 616 74AS TTL series, 591–592 74AUC series, 615 74AVC series, 615 74C series, 196 74CBT series, 616 74CBTLV series, 616 74F-Fast TTL series, 591 74GTLP series, 616 74HC series, 196, 609 74HCT series, 196, 609 74LS TTL series, 196, 591 74LV series, 616 74LVC series, 615–616 74LVT series, 616 74S TTL series, 591 74SSTV series, 616 74 TTL series, 196 74TVC series, 616 Shift-register counters, 522–526 Shift registers, 298–301, 514–516, 516–518, parallel in/parallel out 74ALS174/74HC174, serial in/serial out 74ALS166/74HC166 left, 301 Shrink small outline package (SSOP), 580 Sigma delta modulation, (ADC), 858–860 Sigma (∑), 393 Sign bit, 363 extension, 367–368 magnitude system, 364 Signal alias, 846 contention, 205 duty cycle, 433–434 flow, 431 Signed numbers, 363–370 in sign-magnitude form, 364 SIMM, 933–934 Simple programmable logic devices (SPLDs), 964–965 Simulation of state machines, 504–505 SIPO (serial in/parallel out register), 513 SISO (serial in/serial out register), 513 SISO register, AHDL, 534–535 SISO register, VHDL, 534 Skew, clock, 325–327 S SAM (sequential-access memory), 890–891 Sample-and-hold circuits, 863–864 Sampling, 842 frequency, 845 SBD (Schottky Barrier Diode), 591 Schmitt-trigger devices, 314–316 oscillator, 319 response to slow noisy input, 315 Schottky barrier diode (SBD), 591 TTL 74S series, 591 SDRAM (synchronous DRAM), 934 Sector erase, 909 Security monitoring system, 695–697 Select inputs, (in MUXs), 682–683 Sense amplifier (in DRAM), 925 Sequential-access memory (SAM), 890–891 www.downloadslide.net 1020 INDEX Small outline integrated circuit (SOIC), 580 Small-project management (using HDL), 766–767 definition, 766, 799–800 problem decomposition, 766–767 strategic planning, 766–767 synthesis and testing, 767 system integration and testing, 767 Small-scale integration (SSI), 194, 571 SODIMM, 933 Solder bridges, 207 Special memory functions, 945–948 Spike, 441 SPLDs, 964–965 S-R latches, 262 Staircase test, of a DAC, 835 waveform, of a DAC, 820 Standard cell ASICs, 964 logic, (PLD), 964 State descriptions in AHDL, 481–482 descriptions in VHDL, 483–486 machines, 501–512 simulation of, 504–505 traffic light controller, 505–508 table, 303 transition description methods, HDL, 481 transition diagram, 304, 441 Mod-6 counter, 441 synchronous counter, 469 Static accuracy test, of a DAC, 835 Static RAM (SRAM), 919–924 actual chip (MCM6264C), 922–924 read cycle, 920–922 timing, 920 write cycle, 922 Step-size, 820–821 Stepper motor control, 472–474 driver project (HDL), 767–775 (see also HDL) universal, interface circuit, 770 Straight binary coding, 66 Strategic planning (using HDL), 766–767, 769–770 Stub Series Terminated Logic (74SSTV), 616 SUBDESIGN, 140, 224–225 Subpixels, 672 Substrate, 193 Subtraction BCD, 379 binary, 363 hexadecimal, 381–382 2’s-complement circuits, 395–398 2’s-complement system, 372–375 Subtrahend, 373 Successive-approximation ADC, 846–854 Sum bit, 385 Sum-of-products form, 158–159 Switch bilateral, 627–629 debouncing, 263 encoders, 676–679 Synchronization, flip-flop, 292–293 Synchronous control inputs, 272 counter design with D FF, 474–475 inputs, 272, 285 presetting, 450 systems, 251, 271 transfer, 296 Synchronous (parallel) counters, 436–439 actual ICs, 438–439 advantages over asynchronous, 439 design, 467–475 stepper motor control, 472–474 down and up/down, 446–448 operation, 438–439 presettable, 448–450 Synchronous data transmission system, 697–699 receiver operation, 699 system timing, 699 transmitter operation, 698–699 Synthesis and testing (using HDL), 767, 770–771 System integration and testing (using HDL), 767 T Table analysis using, 105–106 circuit excitation, 468–439, 471 J-K excitation, 468–469 look-up (LUT), 965 state, 303 Temperature-limit detector using an LM339, 636 Temporary storage, RAM, 916 Test vectors, 220 Theorems Boolean, 112–115 DeMorgan’s, 115–118 multivariable, 113–114 Thin Film Transistor (TFT) LCD, 673 Thin quad flat pack (TQFP), 580 Thin shrink small outline package (TSSOP), 580 Thin very small outline package (TVSOP), 580 3-line-to-8-line decoder, 664 TI signal switch (TS switch), 616 Tied-together inputs, TTL, 599 Time Division Multiplexing, 699–703 Timer 555 used as an astable multivibrator, 319–322 (see also Astable multivibrator) Timing diagrams, 27, 465 simplified bus, 721 Timing problems in flip-flop circuits, 289–291 Toggle mode, 278 Toggles, 42 Top-down hierarchical design (digital clock using HDL), 784–786 Totem-pole output circuit, 584–585 Tradeoffs (for nonvolatile memories), 909 Transducer, 816 Transfer data, register, 513 Transfer operation, data, 296 Transition diagram, state, 304 Transition states, 441 Translation Voltage Clamp (74TVC), 616 Transmission gate, CMOS, 627–629 Transparent latch, (D-Latch), 282–284 Trigger input, 276 Tristate data bus, 625 outputs, 622–625 registers (74ALS173/HC173), 718–719 connected to data bus, 718 Troubleshooting, case study, fault basic steps, 200–201 case study parallel binary adder/subtractor, 402–404 counters, 526–529 decoders, circuit with, 673–674 digital systems, 200–201, 637–638 (see also Digital systems) digital-to-analog converters, 834–835 divide-and-conquer, 680 fault correction, 200 dectection, 200 external IC, 206–210 isolation, 200 www.downloadslide.net 1021 INDEX finding shorted nodes, 638 flip-flop circuits, 322–327 internal IC faults, 202–206 logic pulser and probe to test a circuit, using, 638 observation/analysis, 680 open inputs, 323–324 shorted outputs, 324–325 parallel binary adder/subtractor, 402–404 prototyped circuits, 210–214 security monitoring system, 695–697 sequential logic systems, 526 synchronous data transmission system, 697–698 tools used in, 201, 637–638 tree diagram, 705 Truth tables, 92–93 using AHDL, 228–229 using HDL, 227–230 using VHDL, 229–230 TTL logic family, 34, 195–196, 581–586 active pull-up action, 585 ALS series, 196 AS series, 196 biasing inputs LOW, 600 characteristics, 589–593 circuit operation-HIGH state, 582 circuit operation-LOW state, 581–582 comparison of series characteristics, 592 current ratings, 596 current transients, TTL, 601–602 current-sinking action, TTL, 584 data sheets, 586–589 defined, 195 fan-out, 593–598 fast series (74F), 591–592 ground, 196–197 input voltages, 610 interfacing V and CMOS, 631 INVERTER circuit, 195 loading, 593–598 logic-level voltage ranges, 197 low-power Schottky 74LS series (LS-TTL), 591 LS series, 196 maximum voltage ratings, 588 NAND gate, basic, 581–582 NOR gate, basic, 586 open-collector outputs, 617–622 other characteristics, 598–602 output voltages, 610 power, 196–197 power dissipation, 588 propagation delays, 588 S series, 196 Schottky 74S series, 591 series characteristics, 592–593 standard 74 series, 592 subfamilies, 195, 589–593 summary, 585 supply (power) voltage, 196–197, 587 temperature range, 587 tied-together inputs, 599 totem-pole output circuit, 581, 585 tristate, 622–625 Twisted-ring counters, 524 unconnected inputs (floating), 197–198, 598 unused inputs, 598–599 voltage levels, 587–588 Two-input multiplexer, basic, 683–684 2’s-complement addition, 371–372 circuits, 395–398 addition, 395–398 subtraction, 395–398 form, 364 special case representation, 368–370 subtraction, 372–375 system, 364 addition and subtraction, combined, 397–398 multiplication, 375–376 Types of computers, 49–50 embedded controller, 50 microcomputer, 49 microcontroller, 49 microprocessor, 49 Types of LCDs, 671–673 Typical ADC architectures for applications, 862–863 Typical CMOS flash memory IC, 910–911 U Unasserted levels, 130 Unconnected inputs CMOS, 197–198, 613 TTL, 197–198, 598–599 Unipolar digital ICs, 194–195 (see also CMOS logic family) Universal programmers, 217 Universal shift register, AHDL,VHDL, 537–538 Universality of NAND gates and NOR gates, 119–122 Usefulness of hex, 64–65 UV light, EPROMs, 907 V VERSA Module Eurocard (74VME), 616 VHDL, 135–136, 486–487, n-bit adder/subtractor 416–417 adder/subtractor, 416–417 ARCHITECTURE, 141, 225, 496, 499 BCD-to-binary code converter, 743 BEGIN, 141, 483, 486 behavioral description of a counter in, 486 BIT, 141, 226, 338 BIT_VECTOR declarations, 225–227, 229, 410, 412, 486, 495 Boolean description using, 140 BUFFER, 495 cascading BCD counters, 497–498 CASE, 238, 483–484, 494, 504, 508, 511, 538, 779 code converter, 743 comments, 143–144 comparator, 743 complete clock, 797 COMPONENT(s), 336–338, 495, 500, 508, 796 conditional signal assignment statement, 735 declaration, 337 graphic representation using, 337 HDL circuits with multiple, 340–343 library, 336–338 concurrent assignment statement, 140 CONSTANT, 416 converter, 743 D latch, 334 data types, common, 226 decoding the MOD-5 counter, 494–495 decoder(s), 728 drivers, 730–731 full-step sequence, 771 demultiplexers, 738–739 design file, 229 digital clock project, 781–798 (see also HDL) DOWNTO, 410, 779 driver, 730–732 eight-bit adder, 412–413 ELSIF, 235–237 encoder, 735–736 END, 141, 484 ENTITY, 141, 225, 229, 342, 483, 494–495, 499–500 enumerated type, 504 www.downloadslide.net 1022 INDEX VHDL (continued) essential elements in, 141 EVENT, 339, 342, 484 flip-flops, 338–340 J-K flip-flop, 338–340 MOD-8 ripple counter, 341–342 simulation, 339 frequency counter project, 805–809 full-featured counter, 489–490 full-step sequence, 771 IF/THEN/ELSE, 233–234, 504, 511, 733, 741 IN, 225 INTEGER, 226, 233, 412, 486, 489, 732–733 intermediate signals in, 144 J-K flip-flop, 338–340 simulation, 339 keypad encoder project (HDL), 775–781 (see also HDL) simulation, 781 solution, 779–781 libraries, 226, 735 components, 336–338 of parameterized modules, 327 local signals, 143–144 LPMs, 328 macrofunctions, 226 magnitude comparator, 741 MAP, 495, 500, 508 maxplus2 functions, 226 MOD-5 counter, 484 MOD-6 counter, 786, 796 graphic block symbols, 793 simulation, 788 MOD-8 counter, 770 simulation, 770 MOD-10 counter, 788–789, 796 MOD-12 counter, 791–794 graphic block symbols, 794 simulation, 793 MOD-60 counter, 796 MOD-100 BCD counter, 499–500 module integration, 796–798 multiplexers, 738–739 NAND latch, 333 nonretriggerable one-shot, 543–548 objects, 226 one-shots, simple, 543–545 PACKAGE, 416 PISO register, 536–538 PORT, 141 MAP, 338, 343 PROCESS, 234, 338, 342, 483–484, 486, 489–490, 494, 511, 538, 546, 732, 741, 779, 792 RANGE, 233, 486 retriggerable, edge-triggered one-shot, 546–548 ripple-up counter (MOD-8), 341–343 SELECT, 229 sensitivity list, 234 shift register, universal, 537–538 SIGNAL, 143–144, 229–230, 339, 342, 410, 483, 730, 735, 792 simulation, 543–544, 547–548 simulation of full-featured counter, 489–491 simulation testing, 774 SISO register, 534 state descriptions in, 483–486 state machine, simple, 503 STD_LOGIC, 226, 337 STD_LOGIC_VECTOR, 226 stepper driver, 773 stepper motor driver project, 767–775 traffic light controller, 508–511 truth tables, 229–230 concatenating, 229–230 selected signal assignments, 229–230 TYPE, 503 values, table, 229 VARIABLE, 339, 483, 546, 730, 735, 792 WHEN, 728 WITH, 229 VHDL (very-high-speed integrated circuit hardware description language), 135–136 VLSI (very-large scale integration), 194, 571 Volatile memory, 890–891 Voltage comparators, 634–636 controlled oscillator, linear (VCO), 858 level translator, 634 levels, invalid, 576–577 parameters for digital ICs, 572–573 to frequency ADC, 858 W Wave-drive sequence (HDL stepper-motor), 768 Wired-AND connection, 619–620 Word, 72–73 size, 73 Write cycle, 313 Write cycle address setup time, 922 data hold time, 922 data setup time, 922 time, 922 Write enable (WE) input, 893–894 Write operation CPU, 896 defined, 890 RAM, 918 Z Zero count, 42 Zero insertion force socket (ZIF), 216–217 www.downloadslide.net 1023 BOOLEAN THEOREMS x·15x x105x x1151 x1x51 x1y5y1x x·050 x·x50 x1x5x 10 13a 15a 17 x·y5y·x x (y z) (x y) z x y z 11 x(y z) xy xz 13b x xy x y 15b (w x) (y z) wy xy wz xz x xy x y x·x5x 12 x(yz) (xy)z xyz 14 x xy x 16 x1y5xy xy x y LOGIC GATE TRUTH TABLES A 0 1 OR NOR A1B A1B 0 1 B 1 AND NAND XOR A · B A · B A!B 0 1 1 1 0 XNOR A!B 0 LOGIC GATE SYMBOLS x5A1B A B x5A1B A B OR Gate NOR Gate x AB A A x AB B B AND Gate NAND Gate x5A!B AB AB A B x A ! B AB AB A B XOR XNOR www.downloadslide.net 1024 FLIP-FLOPS NOR Latch SET Q Normally low S Q R Q S 1 R 0 1 Q No change Q51 Q50 Invalid S 1 R 0 1 Q Invalid Q50 Q51 No change (Alternate symbol) Q RESET NAND Latch SET Q Normally high S Q R Q (Alternate symbol) Q RESET Clocked S-R CLK R Q c Clocked J-K CLK K Q c Clocked D D CLK Asynchronous Inputs c c CLK c c c c D Q EN 1 Q Q Q Q0 (no change) Ambiguous Q Q0 (no change) Q (toggles) of CLK has no effect on Q c EN c K 0 1 Q D Latch D c of CLK has no effect on Q J 1 Q J CLK R 0 1 S 1 Q S CLK c c Q of CLK has no effect on Q D X Q* No change *Q follows D input while EN is HIGH PRE Q J CLK K Q PRE 1 0 CLR 1 Q* No effect; FF can respond to J, K and CLK Q = independent of J, K, CLK Q = independent of J, K, CLK Ambiguous (not used) *CLK can be in any state CLR ... IIH IIL - 0.4 mA 16 mA 40 mA - 1.6 mA -1 mA 20 mA 50 mA -2 mA - 0.4 mA mA 20 mA - 0.4 mA -2 mA 20 mA 20 mA - 0.5 mA - 0.4 mA mA 20 mA - 0.1 mA -1 mA 20 mA 20 mA - 0.6 mA *Some devices may have... ratings 9.5 1.7 1 .2 45 20 0 70 100 20 40 20 33 2. 7 2. 7 2. 5 2. 5 2. 5 0.4 0.5 0.5 0.5 0.5 0.5 2. 0 2. 0 2. 0 2. 0 2. 0 2. 0 0.8 0.8 0.8 0.8 0.8 0.8 Voltage parameters EXAMPLE 8-3 Use Table 8-6 to calculate... with the standard TTL noise margins? Solution 74LS VNH = = = VNL = = = EXAMPLE 8-4 74 VOH1min2 - VIH1min2 2. 7 V - 2. 0 V 0.7 V VIL1max2 - VOL1max2 0.8 V - 0.5 V 0.3 V VNH = 2. 4 V - 2. 0 V = 0.4