DuongThanCong.com Intelligent Algorithms in Ambient and Biomedical Computing CuuDuongThanCong.com Philips Research VOLUME Editor-in-Chief Dr Frank Toolenaar Philips Research Laboratories, Eindhoven, The Netherlands SCOPE TO THE ‘PHILIPS RESEARCH BOOK SERIES’ As one of the largest private sector research establishments in the world, Philips Research is shaping the future with technology inventions that meet peoples’ needs and desires in the digital age While the ultimate user benefits of these inventions end up on the high-street shelves, the often pioneering scientific and technological basis usually remains less visible This ‘Philips Research Book Series’ has been set up as a way for Philips researchers to contribute to the scientific community by publishing their comprehensive results and theories in book form Dr Rick Harwig CuuDuongThanCong.com Intelligent Algorithms in Ambient and Biomedical Computing Edited by Wim Verhaegh Philips Research Laboratories, Eindhoven, The Netherlands Emile Aarts Philips Research Laboratories, Eindhoven, The Netherlands and Jan Korst Philips Research Laboratories, Eindhoven, The Netherlands CuuDuongThanCong.com A C.I.P Catalogue record for this book is available from the Library of Congress ISBN-10 ISBN-13 ISBN-10 ISBN-13 1-4020-4953-6 (HB) 978-1-4020-4953-8 (HB) 1-4020-4995-1 (e-book) 978-1-4020-4995-8 (e-book) Published by Springer, P.O Box 17, 3300 AA Dordrecht, The Netherlands www.springer.com Printed on acid-free paper All Rights Reserved © 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work Printed in the Netherlands CuuDuongThanCong.com Contents Contributing Authors Preface xvii Acknowledgments Part I xi xxi Healthcare Bioscience Computing and the Role of Computational Simulation in Biology Christopher D Clack 1.1 Introduction to bioscience computing 1.2 Simulating adaptive behaviour 1.3 Impact and future directions for bioscience computing 1.4 Summary and conclusions References 3 15 16 17 The Many Strands of DNA Computing Nevenka Dimitrova 2.1 Introduction 2.2 DNA computing 2.3 Synthetic biology 2.4 Conclusion and future directions References 21 Bio-Inspired Data Management Martin L Kersten and Arno P.J.M Siebes 3.1 Introduction 3.2 Data cell overview 3.3 The communication infrastructure 3.4 The life cycle 3.5 Application challenges 3.6 Conclusion References 37 CuuDuongThanCong.com 21 22 31 33 34 37 40 46 49 51 54 55 vi Contents An Introduction to Machine Consciousness Kees van Zon 4.1 Introduction 4.2 Biological consciousness 4.3 Machine consciousness 4.4 Is it relevant? 4.5 Applications 4.6 Conclusion References Part II 57 57 59 60 65 67 69 69 Lifestyle Optimal Selection of TV Shows for Watching and Recording Wim F.J Verhaegh 5.1 Introduction 5.2 Problem definition 5.3 Computational complexity 5.4 Scheduling shows for watching 5.5 A dynamic programming approach 5.6 Run time improvements 5.7 Experiments 5.8 Conclusion References 73 Movie-in-a-Minute: Automatically Generated Video Previews Mauro Barbieri, Nevenka Dimitrova and Lalitha Agnihotri 6.1 Introduction 6.2 Related work 6.3 Requirements 6.4 Formal model 6.5 Implementation and results 6.6 Need for personalization 6.7 Conclusions References 89 Features for Audio Classification: Percussiveness of Sounds Janto Skowronek and Martin McKinney 7.1 Introduction 7.2 Feature extraction algorithm 7.3 Experiments 7.4 Summary References CuuDuongThanCong.com 73 75 76 77 78 80 82 85 87 89 90 91 92 95 99 100 100 103 103 105 109 117 117 Contents vii Extracting the Key from Music Steffen Pauws 8.1 Introduction 8.2 Musical pitch and key 8.3 Method 8.4 Evaluation 8.5 Conclusion References 119 Approximate Semantic Matching of Music Classes on the Internet Zharko Aleksovski, Warner ten Kate and Frank van Harmelen 9.1 Introduction 9.2 Semantic coordination 9.3 Internet music schemas 9.4 Approximate matching 9.5 Experiment with approximate matching 9.6 Future work 9.7 Conclusion References 133 10 Ontology-Based Information Extraction from the World Wide Web Jan Korst, Gijs Geleijnse, Nick de Jong and Michael Verschoor 10.1 Introduction 10.2 Problem definition 10.3 Solution approach 10.4 Case study: Finding famous people on the Web 10.5 Concluding remarks References 11 Privacy Protection in Collaborative Filtering by Encrypted Computation Wim F.J Verhaegh, Aukje E.M van Duijnhoven, Pim Tuyls and Jan Korst 11.1 Introduction 11.2 Memory-based collaborative filtering 11.3 Encryption 11.4 Encrypted user-based algorithm 11.5 Encrypted item-based algorithm 11.6 Conclusion References CuuDuongThanCong.com 119 121 122 129 130 131 133 135 136 139 140 144 146 146 149 149 151 153 154 165 165 169 169 171 176 178 182 183 184 viii Part III Contents Technology 12 A First Look at the Minimum Description Length Principle Peter D Grăunwald 12.1 Introduction and overview 12.2 The fundamental idea: Learning as data compression 12.3 MDL and model selection 12.4 Crude and refined MDL 12.5 The MDL philosophy 12.6 MDL and Occam’s razor 12.7 History 12.8 Challenges for MDL: The road ahead 12.9 Summary, conclusion and further reading References 187 187 189 192 195 202 205 207 208 210 211 13 Semantic Web Ontologies and Entailment: Complexity Aspects Herman J ter Horst 13.1 Introduction 13.2 RDF graphs and simple entailment 13.3 RDFS entailment and D* entailment 13.4 pD* entailment 13.5 Conclusion References 215 14 Bayesian Methods for Tracking and Localization ă and Nikos Vlassis Wojciech Zajdel, Ben J.A Krose 14.1 Introduction 14.2 Bayesian networks for dynamic systems analysis 14.3 Localization of a mobile platform 14.4 Tracking with distributed cameras 14.5 Conclusions and remaining issues References 243 15 Private Profile Matching Berry Schoenmakers and Pim Tuyls 15.1 Introduction 15.2 Preliminaries 15.3 Secure approximate matching w.r.t Hamming distance 15.4 Conclusion References 259 CuuDuongThanCong.com 215 219 223 233 241 241 243 244 250 253 257 258 259 261 267 271 272 Contents 16 Air Fair Scheduling for Multimedia Transmission over Multi-Rate Wireless LANs Sai Shankar N., Richard Y Chen, Ruediger Schmitt, Chun-Ting Chou and Kang G Shin 16.1 Introduction 16.2 Fairness in wireless/mobile networks 16.3 AFS in an IEEE 802.11e wireless LAN 16.4 Station scheduler 16.5 Local scheduler (LS) 16.6 Numerical and simulation results 16.7 Experimental setup and results 16.8 Conclusions References ix 273 273 277 282 285 287 291 293 296 296 17 High Throughput and Low Power Reed Solomon Decoder for Ultra Wide Band Akash Kumar and Sergei Sawitzki 17.1 Motivation 17.2 Introduction to Reed Solomon 17.3 Channel model 17.4 Architecture design options 17.5 Design flow 17.6 Results 17.7 Benchmarking 17.8 Optimisations to design 17.9 Conclusions References 299 Index 317 CuuDuongThanCong.com 299 300 301 304 308 309 312 312 314 315 High Throughput and Low Power Reed Solomon Decoder 17.4.1 307 Design decisions In order to choose a good architecture for the application, various factors have to be considered Gate count This determines the silicon area to be used for development It is a one-time production cost, but can be critical if it is too high Latency Latency is defined as the delay between the received code word and the corresponding decoded code word The lower the latency, the smaller is the FIFO buffer size required and therefore, it also determines the silicon area to a large extent Critical path delay This determines the minimum clock period, i.e maximum frequency that the system can be operated at Table 17.1 shows a summary of all the above mentioned parameters For our intended UWB application, speed is of prime concern as it has to be able to support data rates as high as 1.0 Gbps At the same time, power has to be kept low, as it is to be used in portable devices as well This implies that the active hardware at any time should be kept low Also, the overall latency and gate count of computational elements should be low since that would determine the total silicon area of the design Key equation solver Reformulated inversion-less and dual line implementation of the modified Berlekamp Massey have the smallest critical path delay among all the alternatives of the Key Equation Solver Inversion-less and dualline architectures are explained in [Chang et al., 1998] and [Kang & Park, 2002] respectively When comparing inversion-less and dual-line implementations, dual line is a good compromise in latency and computational elements needed The latency is one of the lowest and it has the least critical path delay of all the architectures summarized Thus, dual-line implementation of the BM algorithm is chosen for the key-equation solver Another benefit of this architecture is that the design is very regular and hence easy to implement RS code As we can see from Table 17.1, the hardware requirement for the entire block is a function of t, the error correction capability, and the latency is a function of both n and t Thus, while we want to have a code with high error correction capability, we can not have a very high value of t as the hardware needed is proportional to it The value of n determines the bit-width of the symbol and therefore the hardware needed, but only logarithmically However, one would want to have a value of n = 2m − 1, to derive maximum benefit out of the hardware The value of t is often chosen to be a power of in order to maximize the hardware utilized in design Taking into account the results CuuDuongThanCong.com 308 Akash Kumar and Sergei Sawitzki of Channel Model Simulation, RS(255, 239) is chosen, since it has an error correction capability of 17.4.2 Highlights Table 17.2 shows the various parameters for choosing dual line architecture with n = 255, k = 239, and t = The overall critical path delay is hence Mul + Add Table 17.2 Summary of hardware utilization for dual-line architecture Architecture Adders Multipliers Muxes Latches Latency Syndrome Computation Dual-line Chien/Forney 2t 2t 2t 2t 4t + 2t + 2t 2t 2t + 4t 4t + 2t + 10 n 3t + Total For RS(255, 239) 6t 48 8t + 67 6t + 50 10t + 11 91 3t + n + 284 17.5 Design flow The first step was to develop a C-model for the decoder ‘Gcc’ compiler was used to compile the code and to check if the code worked correctly Output of each intermediate stage was compared with the expected output according to the algorithm with the aid of an example Once the algorithm was fully developed and tested in C, VHDL-code was developed The VHDL code was structured such that it could be easily synthesized A wrapper class was written around it, in order to test it This VHDL code was compiled and tested using Cadence tools ‘Ncsim’ was used to simulate the system and generate the output stream for the same input tests as were used for testing C code The output stream from VHDL and C were then compared When this output was found to be matched for various input test cases, synthesis experiments were started Ambit from Cadence was used to analyse the hardware usage and frequency of operation after various optimisation settings The design flow needed for verification of synthesized design and power estimation has been explained in Figure 17.6 As shown in the figure the core VHDL modules were optimised and synthesized using ambit The synthesized model was written out into a verilog netlist using ambit itself Once the netlist was obtained, it was compiled using ncvlog into the work library together with the technology library The library used was for the same technology as the CuuDuongThanCong.com 309 High Throughput and Low Power Reed Solomon Decoder VHDL Wrapper VHDL Core 3a 3b Verilog Netlist of Design VHDL Wrapper Verilog Netlist of CMOS12/18 library Work Library ncvlog ambit Optimize and Synthesize Compile into work library ncshell ambit Generate Verilog Netlist Import top interface to VHDL ncvhdl ncvhdl Compile into work library dncelab/ dncsim Elaborate and Simulate Compile into work library Figure 17.6 Design flow for design verification and estimation of power one used for synthesis As can be seen, the wrapper modules were actually written in VHDL, while the compiled core was from the verilog Thus, to allow interaction between the two, the top interface of the work library, was extracted into a VHDL file and then compiled into the work library This was done using ncshell and ncvhdl respectively This being done, the wrapper modules were compiled into the work library From this point onwards, two approaches were used Ncelab and ncsim were used purely for simulating the synthesized design, and dncelab and dncsim were used to obtain power estimate, which were essentially the same tools, but included the DIESEL routines for estimating the power dissipated in the design Diesel is an internal tool developed within Philips which estimates the power for the simulated design, and hence the accuracy of the results depends on the input provided 17.6 Results This section covers the results of various synthesis experiments conducted Resource utilization, timing analysis and the power consumption were used as benchmarking parameters 17.6.1 Area analysis Ambit was run for 0.12 µm and 0.18 µm CMOS technology The silicon area required was analysed for various timing constraints A comparison for area of the decoder is shown in Table 17.3 This table shows the area requirement when the constraint was set to ns, which can support 200 MHz frequency, i.e CuuDuongThanCong.com 310 Akash Kumar and Sergei Sawitzki 1.6 Gbps The total number of design cells used, including the memory, were 12,768 and 12,613 for 0.12 µm and 0.18 µm respectively Table 17.3 Resource utilization for the decoder Module Chien FIFO Forney Gen elp eep Gen syndromes top view Module Area (µm2 ) CMOS12 CMOS18 7, 663 83, 183 21, 608 89, 602 17, 828 15, 675 148, 684 52, 936 186, 404 34, 754 219, 913 438, 472 17.6.2 Power analysis The power estimates provided in this section are for design operation at 125 MHz, which translates to data rate of 1Gbps Variation with number of errors Figure 17.7 shows the variation of power with the number of errors found in the codeword for 0.12 µm technology As can be seen from the graph obtained, the power dissipated for the FIFO and syndrome computation block is independent of the number of errors as expected For the block that computes the Error Locator Polynomial (ELP) and Error Evaluator Polynomial (EEP), it is clearly seen that the power dissipated increases linearly with the number of errors The Chien search block also shows a linear increase in the power dissipated The behaviour of Forney evaluator is a bit different from the other modules We see that the power dissipated for the codeword with an even number of errors is not significantly larger to the one with the previous number of errors The reason lies in the fact that the degree of EEP for codeword with one error is often the same as the one with two errors, and so on and so forth However, as a general rule, there is still an increase in the power dissipation, because of some computation that is done for each error found Distribution of power in different modules Figure 17.8 shows a distribution of power when there are maximum number of errors correctable in the received code word, while Figure 17.9 shows the distribution when the code word is received intact As can be seen, in the case of no errors, bulk of the power is consumed in computing syndromes, apart from the memory In the event of maximum errors detected, the Forney block consumes the maximum power CuuDuongThanCong.com 311 High Throughput and Low Power Reed Solomon Decoder Power Dissipation versus number of errors in codeword 3000 Power Dissipated (µW) 2500 Forney FIFO Elp-Eep Syndrome Chien 2000 1500 1000 500 0 Number of Errors Figure 17.7 modules Graph showing variation of power dissipated with number of errors for different The total power consumption varies from 14 mW to 17 mW with the former corresponding to no-error case, while the latter corresponding to maximum errors Forney: 1% Chien: 6% Forney: 38% Syndrome: 16% Chien: