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Introduction to Reconfigurable Computing CuuDuongThanCong.com Introduction to Reconfigurable Computing Architectures, Algorithms, and Applications by Christophe Bobda University of Kaiserslautern, Germany CuuDuongThanCong.com A C.I.P Catalogue record for this book is available from the Library of Congress ISBN 978-1-4020-6088-5 (HB) ISBN 978-1-4020-6100-4 (e-book) Published by Springer, P.O Box 17, 3300 AA Dordrecht, The Netherlands www.springer.com Printed on acid-free paper All Rights Reserved c 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work CuuDuongThanCong.com To Lewin, Jan and Huguette for being so patient CuuDuongThanCong.com Foreword "Christophe Bobda’s book is an all-embracing introduction to the fundamentals of the entire discipline of Reconfigurable Computing, also seen with the eyes of a software developer and including a taxonomy of application areas Reconfigurable Computing is a disruptive innovation currently going to complete the most important breakthrough after introduction of the von Neumann paradigm On software to FPGA migrations a dazzling array of publications from a wide variety application areas reports speed-up factors between and orders of magnitude and promises to reduce the electricity bill by at least an order of magnitude Facing the tcyberinfrastructure’s growing electricity consumption (predicted to reach 35–50% of the total electricity production by the year 2020 in the USA) also this energy aspect is a strategic issue The focal point of worldwide almost 15 million software developers will shift toward new solutions of the productivity problems which stem from programming the coming many-core microprocessors and from educational deficits Currently Reconfigurable Computing for High Performance computing is even disorienting the supercomputing scene Their tremulous question is: Do we need to learn hardware design? In the past, when students asked for a text book, we had to refer to a collection of specialized books and review articles focused on individual topics or special application areas, where Reconfigurable Computing takes only a corner or a chapter, sometimes even treating FPGAs as exotic technology (although in important areas it is mainstream for a decade) The typical style of those books or articles assumes that the reader has a hardware background: a leap too far for the existing software developers community The book by Christophe Bobda, however, has also been written for people with a software background, substantially reducing the educational leap bybridging the gap His book has the potential to become a best-seller and to CuuDuongThanCong.com viii Foreword stimulate the urgently needed transformation of the software developer population’s mindset, by playing a similar role as known from the famous historic Mead-&-Conway textbook for the VLSI design revolution Reiner Hartenstein, IEEE fellow, Professor, TU Kaiserslautern " CuuDuongThanCong.com Contents Foreword Preface About the Author List of Figures List of Tables vii xiii xv xvii xxv INTRODUCTION General Purpose Computing Domain-Specific Processors Application-Specific Processors Reconfigurable Computing Fields of Application Organization of the Book 11 RECONFIGURABLE ARCHITECTURES Early Work Simple Programmable Logic Devices Complex Programmable Logic Device Field Programmable Gate Arrays Coarse-Grained Reconfigurable Devices Conclusion 15 15 26 28 28 49 65 IMPLEMENTATION Integration FPGA Design Flow Logic Synthesis Conclusion 67 68 72 75 98 CuuDuongThanCong.com vi Contents HIGH-LEVEL SYNTHESIS FOR RECONFIGURABLE DEVICES 99 Modelling 100 Temporal Partitioning Algorithms 120 Conclusion 148 TEMPORAL PLACEMENT Offline Temporal Placement Online Temporal Placement Managing the Device’s Free Space with Empty Rectangles Managing the Device’s Occupied Space Conclusion 149 151 160 161 165 179 ONLINE COMMUNICATION Direct Communication Communication Over Third Party Bus-based Communication Circuit Switching Network on Chip The Dynamic Network on Chip (DyNoC) Conclusion 181 181 182 183 183 188 199 212 PARTIAL RECONFIGURATION DESIGN Partial Reconfiguration on Virtex Devices Bitstream Manipulation with JBits The Modular Design Flow The Early Access Design Flow Creating Partially Reconfigurable Designs Partial Reconfiguration using Handel-C Designs Platform design Enhancement in the Platform Design Conclusion 213 214 216 217 225 234 244 246 256 257 SYSTEM ON A PROGRAMMABLE CHIP Introduction to SoPC Adaptive Multiprocessing on Chip Conclusion 259 259 268 284 CuuDuongThanCong.com Contents vii APPLICATIONS Pattern Matching Video Streaming Distributed Arithmetic Adaptive Controller Adaptive Cryptographic Systems Software Defined Radio High-Performance Computing Conclusion 285 286 294 298 307 310 313 315 317 References 319 Appendices A Hints to Labs Prerequisites Reorganization of the Project Video8 non pr B Party C Quick Part-Y Tutorial 336 337 338 338 345 349 CuuDuongThanCong.com References 333 [198] M A Tahir, A Bouridane, and F Kurugollu, “An fpga based coprocessor for glcm and haralick texture features and their application in prostate cancer classification,” Analog Integr Circuits Signal Process., vol 43, no 2, pp 205–215, 2005 [199] J Teich, S P Fekete, and J Schepers, “Optimizing dynamic hardware reconfiguration, Angewante Mathematic Und Informatik Universităat zu Kă oln, Tech Rep 97.228, 1998 [200] G R G S J Thomas, “An optimal parallel jacobi-like solution method for the singular value decomposition,” in Proc Int Conf on Parallel Processing, January 1988 [201] C Torres-Huitzil and M Arias-Estrada, “Fpga-based configurable systolic architecture for window-based image processing,” EURASIP Journal on Applied Signal Processing, vol 2005, no 7, pp 1024–1034, 2005, doi:10.1155/ASP.2005.1024 [202] S Trimberger, “Scheduling designs into a time-multiplexed fpga,” in International Symposium on Field Programmable Gate Arrays(FPGA 98) Monterey, California: ACM/SIGDA, 1998, pp 153 – 160 [203] F Vahid and T Givargis, Embedded System Design: A Unified Hardware/Software Introduction New York, NY, USA: John Wiley & Sons, Inc., 2001 [204] R Vaidyanathan and J L Trahan, Dynamic Reconfiguration: Architectures and Algorithms IEEE Computer Society, 2003 [205] R Vaidyanathan and J L Trahan, Dynamic Reconfiguration: Architectures and Algorithms (Series in Computer Science (Kluwer Academic/Plenum Publishers).) Plenum Publishing Co., 2004 [206] A van Breemen and T de Vries, “An agent-based framework for designing multicontroller systems,” Proc of the Fifth International Conference on The Practical Applications of Intelligent Agents and Multi-Agent Technology, pp 219-235, Manchester, U.K, Apr 2000 [207] C Veciana-Nogués and J Domingo-Pascual, “Adaptive video on demand service on rsvp capable network,” in ECMAST ’99: Proceedings of the 4th European Conference on Multimedia Applications, Services and Techniques London, UK: SpringerVerlag, 1999, pp 212–228 [208] “Vhdl online.” [Online] Available: http://www.vhdl-online.de/ [209] J E Volder, “The birth of cordic,” J VLSI Signal Process Syst., vol 25, no 2, pp 101–105, 2000 [210] E Waingold, M Taylor, D Srikrishna, V Sarkar, W Lee, V Lee, J Kim, M Frank, P Finch, R Barua, J Babb, S Amarasinghe, and A Agarwal, “Baring it all to software: Raw machines,” Computer, vol 30, no 9, pp 86–93, 1997 [Online] Available: citeseer.ist.psu.edu/waingold97baring.html [211] H Walder, S Nobs, and M Platzner, “Xf-board: A prototyping platform for reconfigurable hardware operating systems.” in ERSA, 2004, p 306 [212] H Walder and M Platzner, “A runtime environment for reconfigurable hardware operating systems.” in FPL, 2004, pp 831–835 CuuDuongThanCong.com 334 References [213] D W Wall, “Limits of instruction-level parallelism,” in Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating System (ASPLOS), vol 26, no New York, NY: ACM Press, 1991, pp 176189 [Online] Available: http://citeseer.ist.psu.edu/wall90limits.html ă [214] K Weiss, T Steckstor, C Otker, I Katchan, C Nitsch, and J Philipp, Spyder - Virtex X2 User’s Manual, 1999 [215] S A White, “Application of distributed arithmetic to digital signal processing: A tutorial review,” IEEE ASSP Magazine, pp 4–19, July 1989 [216] G Wigley and D Kearney, “The development of an operating system for reconfigurable computing,” in Proceedings of the 9th IEEE Symposium Field-Programmable Custom Computing Machines(FCCM’01) IEEE-CS Press, April 2001 [217] S E G William Lehr, Fuencisla Merino, “Software radio: Implications for wireless services, industry structure, and public policy,” Massachusetts Institute of Technology, Program on Internet and Telecoms Convergence, Tech Rep., Aug 2002 [218] J W Williams and N Bergmann, “Embedded linux as a platform for dynamically self-reconfiguring systems-on-chip,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 2004, pp 163–169 [Online] Available: http://espace.library.uq.edu.au/view.php?pid=UQ:410 [219] M Wirthlin and B Hutchings, “A dynamic instruction set computer,” in IEEE Symposium on FPGAs for Custom Computing Machines, P Athanas and K L Pocek, Eds Los Alamitos, CA: IEEE Computer Society Press, 1995, pp 99–107 [Online] Available: citeseer.nj.nec.com/wirthlin95dynamic.html [220] P L E Wolfgang Rosenstiel, New Algorithms Architectures and Applications for Reconfigurable Computing Berlin: Springer, 2005 [221] T Wollinger, J Guajardo, and C Paar, “Security on fpgas: State-of-the-art implementations and attacks,” Trans on Embedded Computing Systems, vol 3, no 3, pp 534–574, 2004 [222] T J Wollinger, M Wang, J Guajardo, and C Paar, “How well are high-end dsps suited for the aes algorithms? aes algorithms on the tms320c6x dsp.” in AES Candidate Conference, 2000, pp 94–105 [223] Xilinx, “A guide to using field programmable gate arrays (fpgas) for application-specific digital signal processing performance,” http://www.xilinx.com, 1995 [224] Xilinx, “The role of distributed arithmetic design in fpga-based signal processing,” http://www.xilinx.com, 2000 [225] Xilinx, “Spartan-3 fpgas,” http://www.xilinx.com, 2000 [226] Xilinx Inc., “The early access partial reconfiguration lounge,” (registration required) [Online] Available: http://www.xilinx.com/support/prealounge/protected/index.htm [227] Xilinx Inc., “Early access partial reconfiguration user guide,” xilinx User Guide UG208, Version 1.1, March 6, 2006 [Online] Available: http://www.xilinx.com/ bvdocs/appnotes/xapp290.pdf CuuDuongThanCong.com References 335 [228] Xilinx Inc., “Virtex-II Pro XUP Development Board,” http://www.xilinx.com/ univ/xupv2p.html [229] Xilinx Inc., “Xilinx ISE Software Manuals and Help - PDF Collection,” 2005 [Online] Available: http://toolbox.xilinx.com/docsan/xilinx8/books/manuals.pdf [230] Xilinx Inc., “Edk platform studio documentation,” 2007 [Online] Available: http://www.xilinx.com/ise/embedded/edk docs.htm [231] H Yang and D F Wong, “Efficient network flow based min-cut balanced partitioning,” in International Conference on Computer-Aided Design, 1994 [232] Y Yang, Z Abid, and W Wang, “Two-prime rsa immune cryptosystem and its fpga implementation,” in GLSVSLI ’05: Proceedings of the 15th ACM Great Lakes symposium on VLSI New York, NY, USA: ACM Press, 2005, pp 164–167 CuuDuongThanCong.com Appendix A Hints to Labs This chapter gives a step-by-step guide in note form to create a partially reconfigurable system It has been developed while reconstructing the Video8 example and is intended to give hints to the reader on how to create own designs A more detailed description of the demonstration project can be found in 5.2 on page 236 The sources of the guide can be found on the book’s Web page Following the directory and entity names, refer to the Video8 project A profound knowledge of VHDL, ISE and EDK will be needed to comprehend the instructions CuuDuongThanCong.com 338 Appendix A Tutorial Creation of partially reconfigurable designs On the Example of Video8 Version 1.0 Prerequisites Following basic conditions should be present when accomplishing this guide In case of deviations the given approach might not be feasible ISE 8.1.01i PR8 or PR12 (Early Access Partial Reconfiguration patch for ISE) EDK 8.1.02i Abbreviations: PR PRM TL TLM DIR partially reconfigurable partially reconfigurable module top-level top-level module directory root directory of the project Reorganization of the Project Video8 non pr elevate PRM (rgbfilter) to the TLM (top.vhd): initially rgbfilter is instantiated in entity video in But PRM may not be sub-modules of a static part This change now is only the first step rgbfilter will have to be brought up completely to the top-level module 1.1 In video in.vhd: additional ports have to be adjoined to the entity declaration of video in so that rgbfilter can be instantiated outside this entity but the rest may stay the same as before entity video_in is { LLC_CLOCK_to_filter : out std_logic; R_out_to_filter : out std_logic_vector(0 to 9); G_out_to_filter : out std_logic_vector(0 to 9); B_out_to_filter : out std_logic_vector(0 to 9); h_counter_out_to_filter : out std_logic_vector(0 v_counter_out_to_filter : out std_logic_vector(0 valid_out_to_filter : out std_logic; R_in_from_filter : in std_logic_vector(0 to 9); G_in_from_filter : in std_logic_vector(0 to 9); B_in_from_filter : in std_logic_vector(0 to 9); h_counter_in_from_filter : in std_logic_vector(0 v_counter_in_from_filter : in std_logic_vector(0 valid_in_from_filter : in std_logic }; CuuDuongThanCong.com to 9); to 9); to 9); to 9); 339 Appendix A 1.2 In video in.vhd: modules that formerly accessed the rgbfilter instance have to be redirected to outward ports For example simply by rewriting corresponding signals: signals out to the filter: R_out_to_filter
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