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1. C. J. Alpert, C. -N. Chu, and P. G. Villarrubia. The coming of age of physical synthesis, In IEEE/ACM ICCAD, San Jose, CA, 2007, pp. 246–249 |
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3. C. J. Alpert, S. K. Karandikar, Z. Li, G. -J. Nam, S. T. Quay, H. Ren, C. N. Sze, P. G. Villarrubia, and M.C. Yildiz. Techniques for fast physical synthesis. Proceedings of the IEEE, 95(3):573–599, March 2007 |
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Tiêu đề: |
Proceedings of the IEEE |
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4. U. Brenner and A. Rohe. An effective congestion driven placement framework. In Proceedings of International Symposium on Physical Design, San Jose, CA, pp. 6–11, 2002 |
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Tiêu đề: |
Proceedings ofInternational Symposium on Physical Design |
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5. J. Darringer, E. Davidson, D. J. Hathaway, B. Koenemann, M. Lavin, J. K. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, and L. Trevillyan. EDA in IBM: Past, present, and future. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12):1476–1497, December 2000 |
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Tiêu đề: |
IEEE Transactionson Computer-Aided Design of Integrated Circuits and Systems |
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6. I. Sutherland, R. F. Sproull, and D. Harris. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Fransisco, CA, 1999 |
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Tiêu đề: |
Logical Effort: Designing Fast CMOS Circuits |
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8. E. Bozorgzadeh, S. Ghiasi, and M. Sarrafzadeh. Optimal integer delay budget assignment on directed acyclic graphs. IEEE Transactions on CAD of ICs and Systems, 23(8):1184–1199 |
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Tiêu đề: |
IEEE Transactions on CAD of ICs and Systems |
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9. V. Kravets and P. Kudva. Implicit enumeration of structural changes in circuit optimization. In Proceedings of Design Automation Conference, San Diego, CA, pp. 439–441, June 2004 |
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Tiêu đề: |
Proceedingsof Design Automation Conference |
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10. R. E. Bryant. Graph-based algorithms for Boolean function maniupulation. IEEE Transactions on Computers, C-35(6):677–691, August 1986 |
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Tiêu đề: |
IEEE Transactions onComputers |
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11. G. R. Chiu, D. P. Singh, V. Manohararajah, and S. D. Brown. Mapping arbitrary login functions into synchronous embedded memories for area reduction on FPGAS. In IEEE/ACM ICCAD, San Jose, CA, pp. 135–142, 2006 |
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12. B. Guan and C. Sechen. Large standard cell libraries and their impact on layout area and circuit performance.In IEEE ICCD, Austin, TX, pp. 378–383, 1996 |
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13. A. Hussain and K. Umino. Method to close timing on all corners with synopsys galaxy at and below 130 nm. In SNUG, San Jose, CA, 2005 |
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14. R. Murgai. Improved layout-driven area-constrained timing optimization by net buffering, In 18th Interna- tional Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05), Kolkota, India, pp. 97–102, 2005 |
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Tiêu đề: |
18th Interna-tional Conference on VLSI Design "held jointly with "4th International Conference on Embedded SystemsDesign |
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16. C. Guardiani, M. Bertoletti, N. Dragone, M. Malcotti, and P. McNamara. An effective DFM strategy requires accurate process and IP pre-characterization. In IEEE/ACM DAC, Anaheim, CA, pp. 760–761, June 2005 |
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17. H. Ren, D. Z. Pan, C. J. Alpert, and P. Villarrubia. Diffusion-based placement migration. In Proceedings of Design Automation Conference, Anaheim, CA, pp. 515–520, 2005 |
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Tiêu đề: |
Proceedings ofDesign Automation Conference |
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18. R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkarni. Pushing ASIC performance in a power envelope. In Proceedings of Design Automation Conference, Anaheim, CA, p. 788, 2003 |
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Tiêu đề: |
Proceedings of Design Automation Conference |
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19. H. Li, S. Bhunia, Y. Chen, T. N. Vijaykumar, and K. Roy. Deterministic clock gating for microprocessor power reduction. In High-Performance Computer Architecture, Anaheim, CA, pp. 113–122, 2003 |
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Tiêu đề: |
High-Performance Computer Architecture |
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7. L. Trevillyan, P. Kotecha, A. Drumm, and R. Puri. A Method for Incremental Cell Placement for Minimum Wire Length, U. S. patent pending |
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15. V. N. Kravets. Constructive multi-level synthesis by way of functional properties. PhD Thesis, University of Michigan, Ann Arbor, MI, 2001 |
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