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CuuDuongThanCong.com ALGORITHMS FOR VLSI PHYSICAL DESIGN AUTOMATION THIRD EDITION CuuDuongThanCong.com This Page Intentionally Left Blank CuuDuongThanCong.com ALGORITHMS FOR VLSI PHYSICAL DESIGN AUTOMATION THIRD EDITION Naveed A Sherwani Intel Corporation KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW CuuDuongThanCong.com eBook ISBN: Print ISBN: 0-306-47509-X 0-7923-8393-1 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©1999 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: CuuDuongThanCong.com http://kluweronline.com http://ebooks.kluweronline.com To my parents Akhter and Akram Sherwani CuuDuongThanCong.com This Page Intentionally Left Blank CuuDuongThanCong.com Contents Foreword Preface Acknowledgements xvii xix xxvii VLSI Physical Design Automation 1.1 VLSI Design Cycle 1.2 New Trends in VLSI Design Cycle 1.3 Physical Design Cycle 1.4 New Trends in Physical Design Cycle 1.5 Design Styles 1.5.1 Full-Custom 1.5.2 Standard Cell 1.5.3 Gate Arrays 1.5.4 Field Programmable Gate Arrays 1.5.5 Sea of Gates 1.5.6 Comparison of Different Design Styles 1.6 System Packaging Styles 1.6.1 Die Packaging and Attachment Styles 1.6.1.1 Die Package Styles 1.6.1.2 Package and Die Attachment Styles 1.6.2 Printed Circuit Boards 1.6.3 Multichip Modules 1.6.4 Wafer Scale Integration 1.6.5 Comparison of Different Packaging Styles 1.7 Historical Perspectives 1.8 Existing Design Tools 1.9 Summary 13 15 17 18 20 22 25 25 26 26 26 27 27 29 31 31 32 33 35 Design and Fabrication of VLSI Devices 2.1 Fabrication Materials 2.2 Transistor Fundamentals 2.2.1 Basic Semiconductor Junction 2.2.2 TTL Transistors 39 40 43 43 45 CuuDuongThanCong.com viii Contents 2.2.3 MOS Transistors 2.3 Fabrication of VLSI Circuits 2.3.1 nMOS Fabrication Process 2.3.2 CMOS Fabrication Process 2.3.3 Details of Fabrication Processes 2.4 Design Rules 2.5 Layout of Basic Devices 2.5.1 Inverters 2.5.2 NAND and NOR Gates 2.5.3 Memory Cells 2.5.3.1 Static Random Access Memory (SRAM) 2.5.3.2 Dynamic Random Access Memory (DRAM) 2.6 Summary 2.7 Exercises Fabrication Process and its Impact on Physical Design 3.1 Scaling Methods 3.2 Status of Fabrication Process 3.2.1 Comparison of Fabrication Processes 3.3 Issues related to the Fabrication Process 3.3.1 Parasitic Effects 3.3.2 Interconnect Delay 3.3.3 Noise and Crosstalk 3.3.4 Interconnect Size and Complexity 3.3.5 Other Issues in Interconnect 3.3.6 Power Dissipation 3.3.7 Yield and Fabrication Costs 3.4 Future of Fabrication Process 3.4.1 SIA Roadmap 3.4.2 Advances in Lithography 3.4.3 Innovations in Interconnect 3.4.3.1 More Layers of Metal 3.4.3.2 Local Interconnect 3.4.3.3 Copper Interconnect 3.4.3.4 Unlanded Vias 3.4.4 Innovations/Issues in Devices 3.4.5 Aggressive Projections for the Process 3.4.6 Other Process Innovations 3.4.6.1 Silicon On Insulator 3.4.6.2 Silicon Germaniun 3.5 Solutions for Interconnect Issues 3.6 Tools for Process Development 3.7 Summary 3.8 Exercises CuuDuongThanCong.com 46 48 51 53 53 58 62 62 64 66 67 69 71 71 75 76 77 77 79 79 80 81 82 82 82 83 85 85 86 87 87 87 87 88 88 89 90 90 90 91 93 94 94 Contents Data Structures and Basic Algorithms 4.1 Basic Terminology 4.2 Complexity Issues and NP-hardness 4.2.1 Algorithms for NP-hard Problems 4.2.1.1 Exponential Algorithms 4.2.1.2 Special Case Algorithms 4.2.1.3 Approximation Algorithms 4.2.1.4 Heuristic Algorithms 4.3 Basic Algorithms 4.3.1 Graph Algorithms 4.3.1.1 Graph Search Algorithms 4.3.1.2 Spanning Tree Algorithms 4.3.1.3 Shortest Path Algorithms 4.3.1.4 Matching Algorithms 4.3.1.5 Min-Cut and Max-Cut Algorithms 4.3.1.6 Steiner Tree Algorithms 4.3.2 Computational Geometry Algorithms 4.3.2.1 Line Sweep Method 4.3.2.2 Extended Line Sweep Method 4.4 Basic Data Structures 4.4.1 Atomic Operations for Layout Editors 4.4.2 Linked List of Blocks 4.4.3 Bin-Based Method 4.4.4 Neighbor Pointers 4.4.5 Corner Stitching 4.4.6 Multi-layer Operations 4.4.7 Limitations of Existing Data Structures 4.4.8 Layout Specification Languages 4.5 Graph Algorithms for Physical design 4.5.1 Classes of Graphs in Physical Design 4.5.1.1 Graphs Related to a Set of Lines 4.5.1.2 Graphs Related to Set of Rectangles 4.5.2 Relationship Between Graph Classes 4.5.3 Graph Problems in Physical Design 4.5.4 Algorithms for Interval Graphs 4.5.4.1 Maximum Independent Set 4.5.4.2 Maximum Clique and Minimum Coloring 4.5.5 Algorithms for Permutation Graphs 4.5.5.1 Maximum Independent Set 4.5.5.2 Maximum -Independent Set 4.5.6 Algorithms for Circle Graphs 4.5.6.1 Maximum Independent Set 4.5.6.2 Maximum -Independent Set 4.5.6.3 Maximum Clique 4.6 Summary 4.7 Exercises CuuDuongThanCong.com ix 97 99 100 101 102 102 102 103 104 104 104 106 108 110 110 111 115 115 115 117 117 119 120 122 123 130 131 131 135 135 136 138 138 140 142 142 143 144 144 146 148 148 149 151 151 152 558 Bibliography [TKS76] B S Ting, E S Kuh, and I Shirakawa The multilayer routing problem: Algorithms and necessary and sufficient conditions for the single row, single layer case IEEE Transactions on Circuits and Systems, pages 768–778, December 1976 [TKS82] S Tsukijama, E S Kuh, and I Shirakawa An algorithm for single row routing with prescribed street congestion IEEE Transactions on Circuits and Systems, pages 765–772, September 1982 [TMSK84] T T K Trang, M Marek-Sadowska, and E S Kuh An efficient single-row routing algorithm IEEE Transactions on ComputerAided Design, vol CAD-3:178–183, July 1984 [Tom81] M Tompa An optimal solution to a wire-routing problem Journal of Computer and System Sciences, 23(2): 127–150, October 1981 [TR89] R R Tummala and E J Rymaszewski Microelectronics Packaging Handbook Van Nostrand Reinhold, 1989 [Tsa91] R Tsay Exact zero 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pages 32–35, 1990 [Van91] A Vannelli An adaptation of the interior point method for solving the global routing problem IEEE Transanctions on Computer-Aided Design of Integrated Circuits, CAD-10(2), 1991 CuuDuongThanCong.com Bibliography 559 [VCW89] G Vijayan, H H Chen, and C K Wong On vhv-routing in channels with irregular boundaries IEEE Transactions on Computer-Aided Design, CAD-8(2), 1989 [VK83] M P Vecchi and S Kirkpatrick Global wiring by simulated annealing IEEE Transactions on Computer-Aided Design of Integrated Circuits, CAD-2(4), 1983 [VT91] G Vijayan and R Tsay A new method for floorplanning using topological constraint reduction IEEE Transactions on Computer-Aided Design, pages 1494–1501, December 1991 [WC89] Y Wei and C Cheng Towards efficient hierarchical designs by ratio cut partitioning Proceedings of IEEE International Conference on Computer-Aided Design, 1:298–301, 1989 [WC95] Kai Wang and Wai-Kai Chen Floorplan area optimization using network analogous approach ISCAS ’95., 1995 IEEE International Symposium, 1:167 –170, 1995 [WE92] N Weste and K Eshraghian Principles of CMOS VLSI Design - A systems perspective, Second Edition Addison-Wesley, 1992 [WHSS92] B Wu, N Holmes, N Sherwani, and M Sarrafzadeh Over-thecell routers for new cell models Proceedings of 29th ACM/IEEE Design Automation Conference, pages 604–607, June 1992 [Wi178] J Williams Sticks - a graphical compiler for high level Isi design Proceedings of AFIPS, pages 289–295, 1978 [Wir77] N Wirth What can we about the unnecessary diversity of notations for synctactic definitions? Communications of the ACM, November 1977 [WL86] D F Wong and C L Liu A new algorithm for floorplan design Proceedings of 23rd ACM/IEEE Design Automation Conference, pages 101–107, 1986 [WLC90] S J Well, J Leroy, and R Crappe An efficient two-dimensional compaction algorithm for vlsi symbolic layout Proceedings of European Design Automation Conference, pages 196–200, 1990 [WLLC93] L Y Wang, Y.T Lai, B.D Liu, and T.C Chang A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths ICCAD, pages 196–200, 1993 [Won89] S C Wong A 5000-gate cmos epld with multiple logic and interconnect arrays Proceedings of 1989 CICC, pages 5.8.1 – 5.8.4, May 1989 CuuDuongThanCong.com 560 Bibliography [Won98] Zhou Wong Global routing with crosstalk constraints 35th Design Automation Conference Proceedings, pages 374–377, June 1998 [Woo91] N Woo A heuristic method for fpga technology mapping based on the edge visibility Proceedings of 28th ACM/IEEE Design Automation Conference, pages 248–251, 1991 [WS91] B Wu and N A Sherwani Clock routing for high-performance circuits using movable clock terminals Proceedings of Fourth International Conference on IC Design, Manufacture and Application, pages 94–100, September 1991 [WS92] B Wu and N A Sherwani Effective buffer insertion of clock trees for high-speed vlsi circuits Microelectronics, 23:291–300, July 1992 [WW90] T Wang and D Wong An optimal algorithm for floorplan area optimization Proceedings of the 27th ACM/IEEE Design Automation Conference, pages 180–186, 1990 [XGC97] J Xu, P Guo, and C Cheng Cluster refinement for block placement 34th Design Automation Conference Proceedings, pages 762–765, June 1997 [Xio86] J G Xiong Algorithms for global routing Proceedings of Design Automation Conference, 1986 [XK86] X M Xiong and E S Kuh The scan line approach to power and ground routing Proceedings of IEEE International Conference on Computer-Aided Design, pages 6–10, November 1986 S Z Yao, C K Cheng, D Dutt, S Nahar, and C Y Lo Cellbased hierarchical pitchmatching compaction using minimal lp Trans CAD , 14 (4):523–526, 1995 [YG78] M Yannakakis and F Gavril Edge dominating sets in graphs unpublished 1978 [YG87] M Yannakakis and F Gavril The maximum k-colorable problem for chordal graphs Information Processing Letters, pages 133– 137, January 1987 [YK82] T Yoshimura and E S Kuh Efficient algorithms for channel routing IEEE Transactions on Computer-Aided Design, CAD1(1):25–30, January 1982 [YKR87] D C Yeh, S M Kang, and V B Rao Cmos logic circuit partitioning for equal chip complexity Proceedings of IEEE International Conference on Computer Design, pages 358–360, 1987 CuuDuongThanCong.com Bibliography 561 [YM90] J Yih and P Mazumder A neural network design for circuit partitioning IEEE Transactions on Computer-Aided Design, pages 1265–1271, 1990 [YSAF95] H Youssef, S M Sait, and K J Al-Farra Timing influenced force directed floorplanning Proceedings EURO-DAC ’95., pages 156 –161, 1995 [YTK95] T Yamanouchi, K Tamakashi, and T Kambe Hybrid floorplanning based on partial clustering and module restructuring ICCAD-96 Digest of Technical Papers., 1996 IEEE/ACM International Conference, pages 478 –483, 1995 [YW91] C Yang and D F Wong Optimal channel pin assignment IEEE Transactions Computer-Aided Design, CAD 10(11):1413–1423, November 1991 [YYL88] X Yao, M Yamada, and C L Liu A new approach to the pin assignment problem Proceedings of 25th ACM/IEEE Design Automation Conference, pages 566–572, 1988 CuuDuongThanCong.com This Page Intentionally Left Blank CuuDuongThanCong.com Author Index Akers, S B , 262, 464, 477 Arnold, P B , 315 Bagrodia, R., 190 Bakoglu, H B , 74, 447, 523 Barahona, F , 407 Bhasker, J , 200 Bhatt, A , 366 Bhingarde, S , 396, 398, 415 Boyer, D G , 464, 467 Brady, H N , 211 Brayton, R K , 186, 498 Burman, S , 277, 494 Burns, J , 463 Burstein, M , 169, 290 Buschbom, M , 523 Chan, H , 232 Chan, S P , 415 Chandar, K , 494 Chang, K C , 403 Chao, T., 290 Charney, H R , 183 Chen, H H , 334 Chen, H , 277 Chen, R W , 415 Cheng, C , 241, 290 Cheng, C.-K , 169 Chern, T C , 407 Chiang, C , 281 Cho, J D , 448 Cho, T., 367 Ciesielski, M J , 403 Cohoon, J P , 230, 358 Cong, J , 145, 149, 190, 286, 373, 408, 415, 430, 498, 519 Conway, L , 58, 156 Coppersmith, D , 212 Cormen, T , 101 CuuDuongThanCong.com Cullum, J , 183 Dai, W W , 214, 290, 467, 517 Danda, S., 246, 377 Davidson, E E , 523 Dayan, T , 517 Deutsch, D N , 323, 414 Dijkstra, E W , 108, 272 Ding, Y., 498 Donath, W E , 183 Du, D H C , 403 Dunlop, A E , 239 Edahiro, M., 448 Eichenberger, P A , 462 El Gamal, A , 441, 493 Ercolani , 498 Eschermann, B , 214 Even, S , 144, 462 Fiduccia, C M , 169, 339 Filo, D , 498 Fujisawa, T , 313-314 Fussell, D ,442 Gajski, D D , 448 Gao, T , 242 Garey, M R , 101 Gavril, F , 146 Geyer, J M , 464 Glick, P., 414 Goldberg, M K , 169 Gonzalez, T F , 366 Gopal, I S , 212 Greene, J , 190, 493 Hadlock, F O , 264, 407 Hall, K M , 241 Hamachi, G T , 367 Han, S , 367 Haruyama, S , 442 Hashimoto, A , 367, 403 564 Heck, P L , 358 Heath, J., 367 Heisterman, J , 282 Hightower, D W , 269, 442 Hill, D D , 290 Ho, J M , 274, 448, 517 Ho, T T., 367 Holmes, N , 149, 389, 396, 398 Hong, S J , 290 Hong, X., 290 Hossain, M , 149, 410, 440 Hseih, H , 473 Hsu, C P , 290, 306, 407 Hsu, Y C , 290, 367 Hsueh, M Y , 463 Huang, J., 290 Hwang, F K , 113, 273 Iyengar, S S., 367 Jackson, M A B , 429 Johnson, D S , 101 Kahng, A , 430 Kajitani, Y , 367, 403, 415 Kang, S M , 517 Kaptanoglu, S , 493 Karmarkar, N , 290 Karp, R M , 290 Karplus, K , 498 Katsadas, E., 415 Kawamoto, T , 367 Kedem, G , 290 Keel, J , 290 Kernighan, B W , 169, 239 Khan, W A., 440 Khawaja, R., 396 Khoo K.-Y., 519 Kinnen, E , 200, 403, 415 Kirkpatrick, S , 290 Kozminski, K , 200 Kring, C , 169 Kruskal J B., 107 Kubitz, W J , 290 Kuh, E S , 214, 241, 290, 313, 330, 334, 347, 429, 467, 509 Kuo, Y S , 407 LaPotin, D P , 512 Lawler, E L , 185 CuuDuongThanCong.com Author Index Lee, C Y , 261 Lee, D T , 145, 408 Lee, K W , 290 Leighton, F T , 290 Leiserson, C E , 101, 366 Lempel, A , 144 Lengauer, T , 282, 461 Leong, H W , 473 Levitt, K N , 185 Li, Z., 190 Liao, Y -Z , 461, 473 Lin, M.-S , 414 Lin, R., 246 Lin, S , 169 Lin, Y.-L , 367 Liu, C L , 145, 205, 242, 373, 408, 414, 473 Lou, R D , 145 Lursinsap, C , 448 Madhwapathy, S., 377, 398 Malik, A A , 458 Mailhot, F , 498 Marek-Sadowska, M , 367, 408 Masuda, S , 405, 415 Mattheyses, R M , 169 Mazumder, P , 232, 246 Mead, C , 58, 156 Mehta, D., 156 Metropolis, N , 178 Micheli, G D , 498 Mikami, K , 269 Mlynski, D A , 441 Mohan, S., 246 Mory-Rauch, L , 211 Moulton, A S , 441 Murgai, R , 186, 498 Naclerio, N J , 405, 415 Nair, R , 290 Nakajima, K , 396, 405, 415 Natarajan, S , 398 Newton, A R , 169 Nishizaki, Y , 498 Ousterhout, J K , 35, 156, 367 Pan, P , 205 Pan, Y , 290 Panyam, A , 377, 396, 398, 415 Author Index Paris, W , 230 Pedram, M , 214 Perng, H.-W , 414 Pinter, R Y , 366, 403, 407 Plato, D L , 183 Pnnueli, A , 144 Preas, B T , 286 Preparata, F , 156 Prim, R C , 275 Pyo, S, 367 Quinn, N R , 232 Raghavan, R , 366-367 Ramanathan, P , 447 Rao, V B , 179 Reed, J , 325 Rivest, R L , 101 Roberts, D L , 464 Robins, G , 430 Rose, J , 290 Rosen, J , 198 Rothermel, H-J , 441 Roychowdhury, V , 493 Rymaszewski, E J , 523 Saab, Y G , 179 Sahni, S , 200, 366-367 Sangiovanni-Vincentelli, A , 186, 227, 325, 358, 468, 498 Santamauro, M , 325 Sarrafzadeh, M., 145,149, 281, 389, 396, 398, 408, 448, 517 Sato, K , 396 Schiele, W L , 462 Schlag, M , 473 Schweikert, F , 169 Sechen, C , 227, 290 Sequin, C H , 468 Shahookar, K , 232 Shamos, M I , 156 Shanbhag, A., 246 Shenoy, N ,498 Sherwani, N A , 149, 246, 277, 377, 389, 396, 398, 410, 432, 440, 494 Shih, W , 407 Shin, H , 358, 447, 468 Shin, M , 509 CuuDuongThanCong.com 565 Shirakawa, I , 313 Shragowitz, E , 198, 246, 290 Shugard, D , 290 Smith II, R , 367 So, H C , 312 Soukup, J ,263 Sriram, M , 517 Srinivasan.,, 429 Staepelaere, D , 517 Stevens, J , 321, 367, 403 Stevens, K R , 403 Stone, A J , 185 Suaris, P R , 290 Supowit, K J , 148, 190 Sutanthavibul, S , 198, 246 Syed, Z , 441 Tabuchi, K , 269 Takahashi, K , 396 Tarjan, R E , 156, 461 Terai, H , 396 Tewksbury, S K , 512 Ting, B S , 313 Tsai, F S , 367 Tsay, R , 196, 433, 509 Tsui, R , 367 Tummala, R R , 523 Turner, J , 185 Vaidya, P M , 242 VanCleemput, W M , 403 Vecchi, M P , 290 Vijayan, G., 196, 274, 448, 498, 517 Wei, Y , 169 Weste, N., 467 Wolfe, P , 183 Wong, D F , 212, 448 Wong, C K , 212, 274, 281, 461, 473, 517 Woo, N , 498 Wu, B , 396, 432 Xiong, J G , 448 Xue, T., 290 Yang, J C , 212 Yoshimura, K , 347 Yoshimura, T , 330 Zheng, S Q , 367 This Page Intentionally Left Blank CuuDuongThanCong.com Subject Index Acker’s coding scheme, 263 algorithm, approximate, 102, 287, 410 branch and bound, 242, 286 constructive, see placement deterministic, 225 Dijkstra’s, see path divide and conquer, 100, 157, 340 dynamic programming, 100, 108, 148, 375 geometric matching, see clock greedy, 100, 142-143, 283, 317, 321, 339-341, 355, 358, 367 Hadlock’s, see global routing heuristic, 98, 103, 111, 113, 315317, 355, 358, 361, 366 Hightower’s, see global routing Kruskal’s, see spanning tree Lee’s, see global routing left edge, see channel line sweep, 115, 117, 359-360 maze running, see global routing maximum k-independent set, 146 methods of means and median, see clock Mikami’s, see global routing most recent layer, see compaction neighbor find, 117, 119, 121, 125 point find, 100, 117, 124, 294, 305 polynomial time, 100,117,124, 294, 305 Prim’s, see spanning tree probabilistic, 225 CuuDuongThanCong.com recursive, 276, 343 scanline, 458 shadow propagation, see compaction simulated evolution, see search Soukup’s, see global routing virtual grid, see compaction weighted center, see clock zero skew, see clock architecture, FPGA, see FPGA gate array, see gate array area, routing, 192, 247 area routing, see area ASIC, 17, 479 aspect ratio, see block assignment, channel segment , 390 layer, 295, 358 pin, see pin channel, see channel general, 209 terminal, 308, 390 atomic operations, 117-119, 121, 124 BEAR system, 214 benchmark, 345 bipartitation, see partitioning bipolar, see transistor block, aspect ratio, 193 fixed, 191, 198 flexible, 191, 199 board level, partitioning, see partitioning placement, see placement capacity, 568 channel, see channel edge, 146 channel, 249 assignment, 211 capacity, 249, 252, 366 height, 258, 363 routing, 249, 390 greedy, 375, 391 left edge, 144, 346-347 YACR2, 325-327 chip level, partitioning, see partitioning placement, see placement clock, 418 frequency, 419 period, 419 routing, 294, 305, 427 geometric matching algorithm, 430 method of means and medians algorithm, 429 weighted center algorithm, 432 zero skew algorithm, 433 skew, 419 inter, 439 intra, 440 zero, 433 clocking scheme, 419 compaction, 118, 228, 450 compression ridge, 464 graph based, 451, 453 hierarchical, 452, 473 most recent layer algorithm, 467 one dimensional, 451 468 shadow propagation, 456 split grid, 464 two dimensional, 451, 470 virtual grid, 451, 463 x, 451 y, 451 complexity, 100 time, 100 worst case, 318, 358 component, 100 CuuDuongThanCong.com Subject Index computational geometry, 98, 101, 104, 115 concentric circle mapping, 210 conductor, 41 congestion, 41 constraint, capacity, 257 horizontal, 298 integrality, 283 overlap, 470 vertical, 299 contact, burried, 52, 59, 63 cooling schedule, 118, 228, 450 corner stitching, 123-124, 126, 128, 131 crossover, 230, 306 crosstalk, 81 crossunder, 440 cut, tree, 283 cycle, 419 vertical constraint, 331 decomposition, 313 degree, 99 of a rooted tree, 99 of a vertex, 99 in-degree, 99, 329 out-degree, 99, 330 delay, 422 computation, 423 models, 425 RC, 80, 82, 422 demand points, 111, 255 detailed routing, 248, 291 problem, 291, 293, 362 detour, 266, 344 die attachment, TAB, 503 flip-chip, 503 wire bonding, 503 dogleg, 297, 312 doping, 42, 44, 54 drain, 46, 52, 79 dual, 138, 200 edge, 99 Subject Index cost, 106, 108, 111, 113 directed, 99 incident, 99 electron, 40, 42-43, 45, 48 escape point, 269 Euclidian, geometry, 277 fabrication, 39, 47-48, 53, 59, 71, 75 material, 40 nMOS, 51 feedthrough, 257 floorplan, 193 slicing, 194 floorplanning, 191, 283 constraint based, 196 integer program, 198 forest, 107 FPGA, global routing, 257 full-custom, 293 design style, 15 detailed routing, 15 global routing, 257 partitioning, 166 placement, 224 function, 293 gate array, 20, 98-99, 104, 135, 345 architecture, 20 compaction, 138 design style, 15 global routing, 258, 287, 290 partitioning, 167 placement, 224, 409 gates, NAND, 62, 64, 66 NOR, 62, 64 global routing, 248, 255 concurrent, 260, 287 hierarchical, 283, 290 in full custom, see full-custom in gate array, see gate array in multichip module, see Multichip Modules in standard cell, see standard cell line probe, 269, 271-273, 287 CuuDuongThanCong.com 569 Hadlock’s algorithm, 264, 266, 268 Hightower algorithm, 269-271 maze running, 260-261, 267, 269, 272-273, 287, 358 Mikami’s algorithm, 269-271 Lee’s algorithm, 111, 261, 263264, 267, 269 Soukup’s algorithm, 263-265, 268 parallel, 290 problem, 255 sequential, 260, 287 graph, 20, 98-99, 104, 135, 345 bipartite, 100, 110, 148, 318 channel intersection, 254, 256 checker board, 254 circle, 137, 148 clique, 99, 137, 141-143, 151 co-comparability, 138 coloring, 102, 141, 143 comparability, 138 complete, 99, 274-275 constraint, 456 horizontal, 299 vertical, 300, 390 directed, 99 directed acyclic, 99, 349 grid, 253, 261 interval, 136, 142, 299 models, 253 overlap, 136-137, 316 permutation, 136-137, 140-142, 144, 147, 408 planar, 224, 409 routing, 255 tree, 99 triangulated, 138, 142 H-tree, 428 Hierarchical, compaction, see compaction global, see global routing hole, 41, 43, 46 hyper, graph, 100 terminals, 374 570 insulator, 40 integer linear program, 261, 282 integration, large scale, small scale, 2.5 dimensional, 512 very large scale, wafer scale, 31 I/O pads, 18, 40, 43, 94 ions, 18, 40, 43, 94 knock-knee, 296-297 Lambda 58 geometry, 277, 279 layer, 130 assignment, 401 diffusion, 44, 47, 54-55 mask, 47, 50 metal1, 46, 63 metal2, 46 meta13, 46 oxide, 40, 43-44, 46-47, 50-51, 54 polysilicon, 46, 50 layout, grid-based, 405 H-tree, 428 mask, 2, 39, 44, 50, 53 symbolic, 449 manhattan, 266 master, 420 sea-of-gates, 25 matrix, 343, 403 max-cut, 110 MCM, see Multichip Modules metal1, see layer meta12, see layer meta13, see layer methods, nine zone, 211 rip-up and reroute, 12, 325, 334 min-cut, 110, 164 MOS, 43, 45-47, 55, 63 CMOS, 43, 48, 53, 63, 85 nMOS, 47-48, 51, 53, 64 Multichip Modules, 29, 501 pin redistribution, 515 CuuDuongThanCong.com Subject Index programmable, 503 routing, 515 detailed, 257 global, 257 type, C, 502 D, 502 L, 502 mutation, 230 neighbour, 117, 119, 121-122, 126, 138 net, 157 multi-terminal, 253, 323, 353 sequencing, 260 two-terminal, 253 noise, 81 over-the-cell, models, 371 symbolic, 414 routing, 258, 305, 352, 369-370 high performance, see performance driven in three layers, 396 in two layers, 320, 373 oxidation, 55, 71 parasitic effect, 79 partitioning, 157 bi, 165 circuit, 158 graph, 163 level, board, 158 chip, 158 system, 158 simulated annealing, 177 simulated evolution, 179 path, 99, 255, 266, 349 critical, 161, 460 directed, 99, 331, 336 length, 99 shortest, 107, 272-273 Dijkstra’s Algorithm, 108, 272 performance driven, partitioning, 185 placement, 192, 242 routing, 400 Subject Index global, 247, 255, 257, 287 over-the-cell, 398 photolithography, 50, 86 photoresist, 50, 56 pin, assignment, 192, 207 equipotential, 207 functionally equivalent, 207 in a circuit, 191 redistribution, see Multichip Modules type, topological, 211 placement, 191, 255 cluster growth, 240 Constructive algorithm, 225 force-directed algorithm, 232 level, 219 board, 219 chip, 220 system, 219 resistive network optimization, 241 simulated annealing, 226 simulated evolution, 229 poly, see layer polysilicon, see layer power and ground routing, 247, 440 power dissipation, 82 problem, decision, 101 detailed routing, see detailed routing global routing, see global routing maximum k-independent set, 146 min-cost max-flow, 146 NP-complete, 101, 249, 252, 292, 304, 323 NP-hard, 101, 294 shortest path, see path program, integer, 198 programmable MCM, see Multichip Modules queue, CuuDuongThanCong.com 571 priority, 358 rat’s nest, 221 rip-up and reroute, 12, 260, 273 region, P, 43 n, 43-44, 46 resistance, 40-41, 80 routability, 252, 363 in gate array’s, 258 routing, 247 area, see area clock, see clock detailed, see detailed routing global, see global routing ground, see power and ground routing non-rectilinear, 277 over-the-cell, see over-the-cell power, see power and ground routing rectlinear, 247, 306 region, 247, 306 river, 363, 366 single layer, 304, 363 single row, 306, 311 switchbox, see switchbox rubber-band sketches, 517 scaling, 76 constant voltage, 76 full, 76 search, 104, 367 breadth first, 105, 264, 267, 269, 271 depth first, 104, 264, 268 semiconductor, 41-43, 46, 51 separability, 274, 279 short-circuit, 247 shove-aside, 260, 273 silicon, dioxide, see layer wafer, 2, 39, 44, 50, 55-56 simulated annealing, partitioning, see partitioning placement, see placement simulated evolution, 104, 367 partitioning, see partitioning 572 placement, see placement selection, 230 skew, see clock spanning forest, minimum density, 376 source, 46, 55 spanning tree, 106 minimum cost, 106 Kruskal’s algorithm, 106-107 Prim’s algorithm, 275 separable, 274 standard cell, partitioning, 167 placement, 224 global routing, 257, 287 steiner, 102, 111-112 points, 112, 255 tree, see steiner tree steiner tree, 112, 253, 273, 287 diameter, 255 minimum cost, 290 min-max, 279 rectilinear, 112, 273, 287, 359 L-, 274 S-, 274-275, 277 Z-, 274-276 weighted, 281 subgraph, 99, 142-143, 151 bipartite, 393 substrate, p, 46, 53 superconductor, 41 SURF routing system, 517 switchbox, 12, 249 routing, 251 temperature, decrement, 227 terminal, 157 vacant, 297, 391 thermal oxidation, 55 transistor, 43, 45-46, 53, 63, 76 bipolar, 43-44, 48, 54, 345 depletion mode, 48, 62 enhancement mode, 47, 64 unipolar, 43 tree, 99 CuuDuongThanCong.com Subject Index minimum spanning, 273 separable, 279 rooted, 99 steiner, see steiner TTL, 43, 45 vertex, 99, 105, 108, 110, 136 adjacent, 99-100, 138 blocked, 261-262 coloring, 102, 405 cover, 102, 405 degree, 99 outdegree, 99 in a hypergraph, 100 unblocked, 261-262 via, minimization, 400 constrained, 370 topological, 410 unconstrained, 370 stacked, 27, 294 weight, 336 YACR2, see channel yield, 58 zero skew, see clock zone, refining, 469 ... Over-the-Cell Routing and Via Minimization 10.1 Over-the-cell Routing 10.1.1 Cell Models 10.1.2 Two-Layer Over-the-Cell Routers 10.1.2.1 Basic OTC Routing Algorithm 10.1.2.2 Planar Over-the-Cell... Over-the-Cell Routing 10.1.2.3 Over-the-Cell Routing Using Vacant Terminals 10.1.3 Three-Layer Over-the-cell Routing 10.1.4 Multilayer OTC Routing 10.1.5 Performance Driven Over-the-cell Routing 10.2 Via... YORK, BOSTON, DORDRECHT, LONDON, MOSCOW CuuDuongThanCong.com eBook ISBN: Print ISBN: 0-3 0 6-4 7509-X 0-7 92 3-8 39 3-1 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print
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