This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called AtSpeed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect the new focus on the design methodology. This book was written to help hardware design engineers learn how to write good VHDL design descriptions. The goal is to provide enough VHDL and design methodology information to enable a designer to quickly write good VHDL designs and be able to verify the results. It will also attempt to bring the designer with little or no knowledge of VHDL, to the level of writing complex VHDL descriptions. It is not intended to show every possible construct of VHDL in every possible use, but rather to show the designer how to write concise, efficient, and correct VHDL descriptions of hardware designs. This book is organized into three logical sections. The first section of the book will introduce the VHDL language, the second section walks through a VHDL based design process including simulation, synthesis, place and route, and VITAL simulation; and the third section walks through a design example of a small CPU design from VHDL capture to final gatelevel implementation, and AtSpeed debugging. At the back of the book are included a number of appendices that contain useful information about the language and examples used throughout the book. In the first section VHDL features are introduced one or more at a time. As each feature is introduced, one or more real examples are given to show how the feature would be used. The first section consists of Chapters 1 through 8, and each chapter introduces a basic description capability of VHDL. Chapter 1 discusses how VHDL design relates to schematic based design, and introduces the basic terms of the language. Chapter 2 describes some of the basic concepts of VHDL, including the different delay mechanisms available, how to use instance specific data, and defines VHDL drivers. Chapter 2 discusses concurrent statements while Chapter 3 introduces the reader to VHDL sequential statements. Chapter 4 talks about the wide range of types available for use in VHDL. Examples are given for each of the types showing how they would be used in a real example. In Chapter 5 the concepts of subprograms and packages are introduced. The different uses for functions are given, as well as the features available in VHDL packages. Chapter 6 introduces the five kinds of VHDL attributes. Each attribute kind has examples describing how to use the specific attribute to the designers best advantage. Examples are given which describe the purpose of each of the attributes. Chapters 7 and 8 will introduce some of the more advanced VHDL features to the reader. Chapter 7 discusses how VHDL configurations can be used to construct and manage complex VHDL designs. Each of the different configuration styles are discussed along with examples showing usage. Chapter 8 introduces more of the VHDL advanced topics with discussions of overloading, user defined attributes, generate statements, and TextIO. The second section of the book consists of Chapters 9 through 11. Chapters 9 and 10 discuss the synthesis process and how to write synthesizable designs. These two chapters describe the basics of the synthesis process including how to write synthesizeable VHDL, what is a technology library, what does the synthesis process look like, what are constraints and attributes, and what does the the optimization process look like. Chapter 11 discusses the complete high level design flow from VHDL capture through VITAL simulation. The third section of the book walks through a description of a small CPU design from the VHDL capture through simulation, synthesis, place and route, and VITAL simulation. Chapter 12 describes the top level of the CPU design from a functional point of view. In Chapter 13 the RTL description of the CPU is presented and discussed from a synthesis point of view. Chapter 14 begins with a discussion of VHDL testbenches and how they are used to verify functionality. Chapter 14 finishes the discussion by describing the simulation of the CPU design. In Chapter 15 the verified design is synthesized to a target technology. Chapter 16 takes the synthesized design and places and routes the design to a target device. Chapter 17 begins with a discussion of VITAL and ends with the VITAL simulation of the placed and routed CPU design. Chapter 18 is a new chapter that discusses the new technique of AtSpeed debugging. This chapter provides the reader with an indepth look at how a hardware implementation of the CPU design can help speed verification. Finally there are three appendices at the end of the book to provide reference information. Appendix Ais a listing of the IEEE 1164 STD_LOGIC package used throughout the book. Appendix B is a set of useful tables that condense some of the information in the rest of the book into quick reference tables. Finally, Appendix C describes how to read the BachusNaur format(BNF) descriptions found in the VHDL Language Reference Manual. I can only hope that you the reader will have as much fun reading this book and working with VHDL as I did in writing it.
CuuDuongThanCong.com https://fb.com/tailieudientucntt VHDL: Programming by Example Douglas L Perry Fourth Edition McGraw-Hill New York • Chicago • San Francisco • Lisbon • London Madrid • Mexico City • Milan • New Delhi • San Juan Seoul • Singapore • Sydney • Toronto CuuDuongThanCong.com https://fb.com/tailieudientucntt abc McGraw-Hill Copyright © 2002 by The McGraw-Hill Companies, Inc All rights reserved Manufactured in the United States of America Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher 0-07-140070-2 All trademarks are trademarks of their respective owners Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark Where such designations appear in this book, they have been printed with initial caps McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs For more information, please contact George Hoare, Special Sales, at george_hoare@mcgraw-hill.com or (212) 904-4069 TERMS OF USE This is a copyrighted work and The McGraw-Hill Companies, Inc (“McGraw-Hill”) and its licensors reserve all rights in and to the work Use of this work is subject to these terms Except as permitted under the Copyright Act of 1976 and the right to store and retrieve one copy of the work, you may not decompile, disassemble, reverse engineer, reproduce, modify, create derivative works based upon, transmit, distribute, disseminate, sell, publish or sublicense the work or any part of it without McGraw-Hill’s prior consent You may use the work for your own noncommercial and personal use; any other use of the work is strictly prohibited Your right to use the work may be terminated if you fail to comply with these terms THE WORK IS PROVIDED “AS IS” McGRAW-HILL AND ITS LICENSORS MAKE NO GUARANTEES OR WARRANTIES AS TO THE ACCURACY, ADEQUACY OR COMPLETENESS OF OR RESULTS TO BE OBTAINED FROM USING THE WORK, INCLUDING ANY INFORMATION THAT CAN BE ACCESSED THROUGH THE WORK VIA HYPERLINK OR OTHERWISE, AND EXPRESSLY DISCLAIM ANY WARRANTY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE McGraw-Hill and its licensors not warrant or guarantee that the functions contained in the work will meet your requirements or that its operation will be uninterrupted or error free Neither McGraw-Hill nor its licensors shall be liable to you or anyone else for any inaccuracy, error or omission, regardless of cause, in the work or for any damages resulting therefrom McGraw-Hill has no responsibility for the content of any information accessed through the work Under no circumstances shall McGraw-Hill and/or its licensors be liable for any indirect, incidental, special, punitive, consequential or similar damages that result from the use of or inability to use the work, even if any of them has been advised of the possibility of such damages This limitation of liability shall apply to any claim or cause whatsoever whether such claim or cause arises in contract, tort or otherwise DOI: 10.1036/0071409548 CuuDuongThanCong.com https://fb.com/tailieudientucntt This Book is Dedicated to my wife Debbie and my son Brennan Thank you for your patience and support CuuDuongThanCong.com https://fb.com/tailieudientucntt This page intentionally left blank CuuDuongThanCong.com https://fb.com/tailieudientucntt CONTENTS Foreword xiii Preface xv Acknowledgments Chapter Chapter CuuDuongThanCong.com xviii Introduction to VHDL VHDL Terms Describing Hardware in VHDL Entity Architectures Concurrent Signal Assignment Event Scheduling Statement Concurrency Structural Designs Sequential Behavior Process Statements Process Declarative Region Process Statement Part Process Execution Sequential Statements Architecture Selection Configuration Statements Power of Configurations 3 6 9 10 10 11 11 12 Behavioral Modeling 15 Introduction to Behavioral Modeling Transport Versus Inertial Delay Inertial Delay Transport Delay Inertial Delay Model Transport Delay Model Simulation Deltas Drivers Driver Creation Bad Multiple Driver Model Generics Block Statements Guarded Blocks 16 20 20 21 22 23 23 27 27 28 29 31 35 https://fb.com/tailieudientucntt vi Contents Chapter Chapter Chapter CuuDuongThanCong.com Sequential Processing 39 Process Statement Sensitivity List Process Example Signal Assignment Versus Variable Assignment Incorrect Mux Example Correct Mux Example Sequential Statements IF Statements CASE Statements LOOP Statements NEXT Statement EXIT Statement ASSERT Statement Assertion BNF WAIT Statements WAIT ON Signal WAIT UNTIL Expression WAIT FOR time_expression Multiple WAIT Conditions WAIT Time-Out Sensitivity List Versus WAIT Statement Concurrent Assignment Problem Passive Processes 40 40 40 42 43 45 46 47 48 50 53 54 56 57 59 62 62 62 63 64 66 67 70 Data Types 73 Object Types Signal Variables Constants Data Types Scalar Types Composite Types Incomplete Types File Types File Type Caveats Subtypes 74 74 76 77 78 79 86 98 102 105 105 Subprograms and Packages 109 Subprograms Function 110 110 https://fb.com/tailieudientucntt Contents vii Chapter Chapter CuuDuongThanCong.com Conversion Functions Resolution Functions Procedures Packages Package Declaration Deferred Constants Subprogram Declaration Package Body 113 119 133 135 136 136 137 138 Predefined Attributes 143 Value Kind Attributes Value Type Attributes Value Array Attributes Value Block Attributes Function Kind Attributes Function Type Attributes Function Array Attributes Function Signal Attributes Attributes ’EVENT and ’LAST_VALUE Attribute ’LAST_EVENT Attribute ’ACTIVE and ’LAST_ACTIVE Signal Kind Attributes Attribute ’DELAYED Attribute ’STABLE Attribute ’QUIET Attribute ’TRANSACTION Type Kind Attributes Range Kind Attributes 144 144 147 149 151 151 154 156 157 158 160 160 161 164 166 168 169 170 Configurations 173 Default Configurations Component Configurations Lower-Level Configurations Entity-Architecture Pair Configuration Port Maps Mapping Library Entities Generics in Configurations Generic Value Specification in Architecture Generic Specifications in Configurations Board-Socket-Chip Analogy Block Configurations Architecture Configurations 174 176 179 180 181 183 185 188 190 195 199 201 https://fb.com/tailieudientucntt viii Contents Chapter Chapter Chapter 10 CuuDuongThanCong.com Advanced Topics 205 Overloading Subprogram Overloading Overloading Operators Aliases Qualified Expressions User-Defined Attributes Generate Statements Irregular Generate Statement TextIO 206 206 210 215 215 218 220 222 224 Synthesis 231 Register Transfer Level Description Constraints Timing Constraints Clock Constraints Attributes Load Drive Arrival Time Technology Libraries Synthesis Translation Boolean Optimization Flattening Factoring Mapping to Gates 232 237 238 238 239 240 240 240 241 243 243 244 245 246 247 VHDL Synthesis 251 Simple Gate — Concurrent Assignment IF Control Flow Statements Case Control Flow Statements Simple Sequential Statements Asynchronous Reset Asynchronous Preset and Clear More Complex Sequential Statements Four-Bit Shifter State Machine Example 252 253 256 257 259 261 262 264 266 https://fb.com/tailieudientucntt Contents ix Chapter 11 Chapter 12 Chapter 13 High Level Design Flow 273 RTL Simulation VHDL Synthesis Functional Gate-Level Verification Place and Route Post Layout Timing Simulation Static Timing 275 277 283 284 286 287 Top-Level System Design 289 CPU Design Top-Level System Operation Instructions Sample Instruction Representation CPU Top-Level Design Block Copy Operation 290 290 291 292 293 299 CPU: Synthesis Description 303 ALU Comp Control Reg Regarray Shift Trireg Chapter 14 Chapter 15 CuuDuongThanCong.com 306 309 311 321 322 324 326 CPU: RTL Simulation 329 Testbenches Kinds of Testbenches Stimulus Only Full Testbench Simulator Specific Hybrid Testbenches Fast Testbench CPU Simulation 330 331 333 337 340 342 345 349 CPU Design: Synthesis Results 357 https://fb.com/tailieudientucntt 464 Appendix D: VHDL93 Updates ROL—rotate left q