VHDL1 ebook,VHDL tutorial

v3.4 Contents VHDL Compiler Reference About This Manual Audience Manual Contents Conventions Synopsys Products i i ii v vi Design Process Hardware Description Languages Typical Uses for HDLs Advantages of HDLs About VHDL About VHDL Compiler Using VHDL Compiler with Design Compiler A Model of the Design Process VHDL Example Design Problem VHDL Design Description Synthesizing the VHDL Design 1–1 1–3 1–3 1–4 1–5 1–8 1–9 1–10 1–13 1–13 1–14 1–16 Description Styles Design Hierarchy Data Types Design Constraints Register Selection Asynchronous Designs Language Constructs 2–1 2–2 2–3 2–4 2–4 2–5 2–6 Describing Designs VHDL Entities VHDL Constructs Entities 3–1 3–2 3–5 3–6 HOME INDEX For further assistance, email support_center@synopsys.com or call your local support center Design Process VHDL Compiler, a member of the Synopsys HDL Compiler family, translates and optimizes a VHDL description to an internal gate-level equivalent This representation is then compiled with the Synopsys Design Compiler Family to produce an optimized gate-level design in a given ASIC technology Conversely, an existing technology-dependent gate-level description (such as a netlist) can be read by Design Compiler, then written out as a technology-independent VHDL description by VHDL Compiler This translation capability is called reverse synthesis; it provides a powerful means of leveraging existing designs HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference To work with VHDL, familiarize yourself with the following concepts: Hardware Description Languages About VHDL About VHDL Compiler Using VHDL Compiler with Design Compiler A Model of the Design Process VHDL Examples Design Problem VHDL Design Description Synthesizing the Example VHDL Design The United States Department of Defense, as part of its VeryHigh-Speed Integrated Circuit (VHSIC) program, developed VHSIC HDL (VHDL) in 1982 VHDL describes the behavior, function, and inputs and outputs of a digital circuit design VHDL is similar in style and syntax to modern programming languages, but includes many hardware-specific constructs Appendix A contains sample VHDL designs, with schematics of their synthesized circuits VHDL Compiler reads and parses the supported VHDL syntax Appendix C lists all VHDL constructs with the level of Synopsys support for each HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Hardware Description Languages Hardware description languages (HDLs) are used to describe the architecture and behavior of discrete electronic systems HDLs were developed to deal with increasingly complex designs An analogy is often made to the history of what can be called software description languages, from machine code (transistors and solder), to assembly language (netlists), to high-level languages (HDLs) Top-down, HDL-based system design is most useful in large projects, where several designers or teams of designers are working concurrently HDLs provide structured development After major architectural decisions have been made, and major components and their connections have been identified, work can proceed independently on subprojects Typical Uses for HDLs HDLs typically support a mixed-level description where structural or netlist constructs can be mixed with behavioral or algorithmic descriptions With this mixed-level capability, you can describe system architectures at a high level of abstraction; then incrementally refine a design into a particular component-level or gate-level implementation Alternatively, you can read an HDL design description into the Synopsys Design Compiler, then direct the compiler to synthesize a gate-level implementation automatically HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Advantages of HDLs A design methodology that uses HDLs has several fundamental advantages over a traditional gate-level design methodology Among the advantages are the following: HOME F You can verify design functionality early in the design process, and immediately simulate a design written as an HDL description Design simulation at this higher level, before implementation at the gate-level, allows you to test architectural and design decisions F By using VHDL Compiler with Synopsys’ logic synthesis, you can automatically convert a VHDL description to a gate-level implementation in a given technology This methodology eliminates the former gate-level design bottleneck and reduces circuit design time and errors introduced when hand-translating a VHDL specification to gates With Synopsys’ logic optimization, you can automatically transform a synthesized design to a smaller or faster circuit You can apply information gained from the synthesized and optimized circuits back to the VHDL description, perhaps to fine-tune architectural decisions Synopsys Design Compiler, which is described in the , provides logic synthesis and optimization F HDL descriptions provide technology-independent documentation of a design and its functionality An HDL description is more easily read and understood than a netlist or schematic description Since the initial HDL design description is technology-independent, you can later reuse it to generate the design in a different technology, without having to translate from the original technology CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference F VHDL, like most high-level software languages, provides strong type checking A component that expects a four-bit-wide signal type cannot be connected to a three- or five-bit-wide signal; this mismatch causes an error when the HDL description is compiled If a variable’s range is defined as to 15, an error results from assigning it a value of Incorrect use of types has been shown to be a major source of errors in descriptions Type checking catches this kind of error in the HDL description even before a design is generated About VHDL VHDL is one of just a few HDLs in widespread use today VHDL is recognized as a standard HDL by the IEEE (IEEE Standard 1076, ratified in 1987) and by the United States Department of Defense (MIL–STD–454L) VHDL divides entities (components, circuits, or systems) between an external or visible part (entity name and connections) and an internal or hidden part (entity algorithm and implementation) After you define the external interface to an entity, other entities can use that entity when they all are being developed This concept of internal and external views is central to a VHDL view of system design An entity is defined, with respect to other entities, by its connections and behavior You can explore alternate implementations (architectures) of an entity without changing the rest of the design After you define an entity for one design, you can reuse it in other designs as needed You can develop libraries of entities for use by many designs, or for a family of designs The VHDL model of hardware is shown in Figure 1–1 HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Figure 1–1 VHDL Hardware Model Entity (Architecture) Process Ports Process red, blue Sequential Process wait ; if A then X else Y end if; Combinational Process (Signals) to 15 X and (Y xor Z); Subprogram Component A VHDL entity (design) has one or more input, output, or input-output ports that are connected (wired) to neighboring systems An entity is itself composed of interconnected entities, processes, and components, all which operate concurrently Each entity is defined by a particular architecture, which is composed of VHDL constructs such as arithmetic, signal assignment, or component instantiation statements In VHDL, independent processes model sequential (clocked) circuits, such as flip-flops, and combinational (unclocked) circuits, such as AND or XOR gates Processes can define and call (instantiate) subprograms (subdesigns) Processes communicate with each other by signals (wires) HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference A signal has a source (driver), one or more destinations (readers), and a user-defined type, such as “color” or “number between and 15.” VHDL provides a broad set of constructs With VHDL you can describe discrete electronic systems of varying complexity (systems, boards, chips, modules) with varying levels of abstraction VHDL language constructs are divided into three categories by their level of abstraction: behavioral, dataflow, and structural These categories are described as follows: behavioral The functional or algorithmic aspects of a design, expressed in a sequential VHDL process dataflow The view of data as flowing through a design, from input to output An operation is defined in terms of a collection of data transformations, expressed as concurrent statements structural The view closest to hardware; a model where the components of a design are interconnected This view is expressed by component instantiations HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference About VHDL Compiler VHDL Compiler converts VHDL source code to an internal format used by the Synopsys Design Compiler VHDL Compiler is accessed in dc_shell or Design Analyzer by executing elaborate and analyze VHDL Compiler performs two functions: translating VHDL to an internal format, and optimizing the block level representation through various optimization methods Design Compiler reads the design in internal format from VHDL Compiler, then optimizes and maps the design’s logical structure for a specific ASIC technology library, as shown in Figure 1–2 Figure 1–2 VHDL Compiler Used with VHDL System Simulator (VSS) and Design Compiler VHDL Description VHDL System Simulator (functionality verification) VHDL Compiler (translation, block level optimization) ASIC Technology Library HOME CONTENTS Design Compiler (logical optimizations, technology–specific netlist /schematic) INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference A VHDL description is first simulated to verify design functionality, by using a VHDL simulator such as the Synopsys VSS Family (VSS Expert or VSS Professional) When analyzing VHDL design files for simulation you can use vhdlan –spc to verify Synopsys synthesis policy For more information, refer to the chapter on the VHDL Analyzer in the or the VHDL Compiler is called by Design Compiler when you read in or write out a VHDL design VHDL Compiler synthesizes VHDL descriptions according to the VHDL synthesis policy defined in Chapter 2, “Description Styles.” The Synopsys VHDL synthesis policy has three parts: design methodology, design style, and language constructs You use the VHDL synthesis policy to produce high quality VHDLbased designs Using VHDL Compiler with Design Compiler When VHDL Compiler reads a VHDL design, the design is converted to Design Compiler’s internal database format When Design Compiler performs logic optimization on a design, Design Compiler can restructure part or all of the design You control the degree of restructuring You can keep a design hierarchy intact, move modules up or down the design hierarchy, combine modules, or compress the entire design into one module HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Sequential Statements wait The wait statement is unsupported unless it is of one the following forms: wait until clock = VALUE; clock’event and clock = VALUE; wait until wait until not clock’stable and clock = VALUE; where VALUE is ’0’, ’1’ or an enumeration literal whose encoding is or A wait statement in this form is interpreted to mean “wait until the falling (VALUE is ’0’) or rising (VALUE is ’1’) edge of the signal named clock.” wait statements cannot be used in subprograms or for loops assertion Assertion statements are ignored signal Guarded signal assignment is unsupported transport and after are ignored Multiple waveform elements in signal assignment statements are unsupported variable Variable statements are fully supported procedure call Type conversion on formal parameters is unsupported Assignment to single bits of vectored ports is unsupported if If statements are fully supported case Case statements are fully supported HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference loop for loops are supported, with two constraints: the loop index range must be globally static, and the loop body must not contain a wait statement while loops are supported, but the loop body must contain at least one wait statement loop statements with no iteration scheme (infinite loops) are supported, but the loop body must contain at least one wait statement next Next statements are fully supported exit Exit statements are fully supported return Return statements are fully supported null Null statements are fully supported HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Concurrent Statements block Guards on block statements are unsupported Ports and generics in block statements are unsupported process Sensitivity lists in process statements are ignored concurrent procedure call Concurrent procedure call statements are fully supported concurrent assertion Concurrent assertion statements are ignored concurrent signal assignment The guarded and transport keywords are ignored Multiple waveforms are unsupported component instantiation Type conversion on the formal port of a connection specification is unsupported generate Generate statements are fully supported HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Predefined Language Environment severity_level type severity_level type is unsupported time type time type is unsupported now function now function is unsupported TEXTIO package The TEXTIO package is unsupported predefined attributes Predefined attributes are unsupported, except for base, left, right, high, low, range, reverse_range, and length The event and stable attributes are supported only in the if and wait statements, as described in Chapter HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference VHDL Reserved Words The following words are reserved for the VHDL language and cannot be used as identifiers: abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded HOME CONTENTS if in inout is select severity signal subtype label library linkage loop map mod then to transport type units until use nand new next nor not null of on open or others out variable wait when while with xor package port procedure process range record register rem report return INDEX For further assistance, email support_center@synopsys.com or call your local support center D Using Design Libraries Synopsys provides the ability to store designs in design libraries Design libraries are particularly useful for storing VHDL packages When a VHDL package has been analyzed into a design library, it is automatically found by the tool, even in subsequent runs of dc_shell You can store designs in a design library by using the analyze command Designs in design libraries are used by the elaborate command as well as by synthetic libraries Using design libraries requires you to understand the following concepts: Using Predefined Libraries Defining Design Libraries Storing Designs in Libraries Reporting on the Contents of Libraries Using Design Units from Design Libraries HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Using Predefined Libraries Certain standard libraries are predefined by Synopsys These libraries include the synopsys library and the IEEE library To get a complete list of predefined libraries in the current release, use the report_design_lib command To view the contents of an individual library, use report_design_lib library_name Packages defined in these libraries can be used by your VHDL source code These packages are found automatically The following example demonstrates how to use a predefined package Note: Subdesigns are not automatically selected and elaborated from any design directory other than WORK library IEEE; use IEEE.std_logic_1164.all; Defining Design Libraries Intermediate format files are stored in design libraries, which are mapped onto UNIX directories on disk You can define these libraries by using the define_design_lib command The syntax is define_design_lib library_name –path directory where library_name is the name of the design library to map, and –path directory is the name of the UNIX directory on disk HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference An example of this command is dc_shell> define_design_lib MY_LIB –path ~/library In this example, the library MY_LIB is mapped to the directory ~/library Library mappings can be stored in your start-up files in one of two ways: F You can store define_design_lib commands in your synopsys_dc.setup file F To maintain consistency with the VSS Family, you can use the file pointed to by the design_library_file variable By default, the value of this variable is synopsys_vss.setup The format for this file in the same as the synopsys_vss.setup file used by VSS Family An example of a line from one of these files is library_name : directory_name The file is read in whenever the variable is changed or the file is modified If the design_library_file variable is set to a full pathname, the file described by the full pathname is read If, however, the variable is set to a relative path, both the home directory and the current working directory are searched for the mapping information file You can write mapping information to a new file by using the write_design_lib_paths command The syntax is write_design_lib_paths [–filename file][–dc_setup] HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference –filename file designates the name of the file in which to store library information, and –dc_setup indicates that the file must be written in synopsys_dc.setup format The default value of the file argument depends on whether or not the –dc_setup option is used: F If –dc_setup is used, the default value of file is synopsys_dc.setup F If –dc_setup is not used, the default value of file is determined by the design_library_file variable Also, by default, the file is written in synopsys_vss.setup format write_design_lib_paths cannot modify an existing file If file already exists, the write_design_lib_paths command fails The following command writes design library path names to the synopsys_dc.setup file in the home directory dc_shell> write_design_lib_paths –file ~/.synopsys_dc.setup –dc_setup To find a directory where a library is mapped, use the get_design_lib_path command The syntax is get_design_lib_path library_name library_name is the name of the library to find HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Storing Designs in Libraries Normally, if you use the read command to read in HDL files, only templates and packages are saved in a design library The read command always stores these files in the WORK library To save all design units (as opposed to only templates and packages) in a design library, you must use the analyze command analyze translates HDL files to the intermediate file format and stores them in a designated library The syntax is analyze [–work library_name or –library library_name] [–format hdl_format]input_files –work library_name –library library_name Stores design elements in the library called library_name Effectively, this maps the working library to library_name and stores all output there –library is an alias for –work or Both options are functionally equivalent –format hdl_format Designates the format of the files to be analyzed hdl_format can either be vhdl or verilog input_files Are the files to be analyzed When you analyze more than one file, use braces ({}) to enclose the file names You cannot analyze design units into a nonreadable directory In the following example, the HDL file packages.vhd is analyzed, and the resulting intermediate format file is stored in the library MY_LIB dc_shell> analyze –work MY_LIB –f vhdl packages.vhd HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Stored Files After packages and templates have been analyzed, they no longer need to be explicitly read in These files are pulled in automatically from the appropriate library as needed The file needs to be recreated only when the HDL code changes Files remain in existence from one run of dc_shell to the next Synthesis Policy Checking The –spc_elab option invokes Synthesis Policy Checking (SPC) vhdlan compares the source files to the VHDL subset (policy) supported by the VHDL Compiler Constructs that cause synthesis problems are flagged with SPC_Warning and SPC_Error Before you can analyze a file with the –spc option, you must first analyze all the files it uses with the –spc option The Analyzer creates extra design library files when it checks the synthesis policy These files have a syn suffix Synthesis policy errors and warnings are for your information They not affect the creation design library files, or the total error and warning count reported by the Analyzer The –spc option reduces the time and memory required for synthesis policy checking by not reporting synthesis elaboration errors Elaboration errors are reported by the synthesis elaborate command HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Reporting on the Contents of Libraries To list the contents of a design library, you can use the report_design_lib command The syntax is report_design_lib [–libraries][–designs][–architectures] [–packages][library_names] where –libraries Lists the mappings of libraries –designs Lists the designs in libraries (Verilog modules, VHDL entities, or configurations) –architectures Lists the designs in libraries and their architectures –packages Lists the packages contained in libraries library_names Is the list of libraries whose contents are to be displayed If library_names is not used, all libraries are displayed by default The options for this command define specific types of information to list Example D–1 is a sample report generated by the command HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Example D–1 Report Generated by report_design_lib dc_shell> report_design_lib WORK **************************************** Report : hdl libraries Version: v3.0 **************************************** Contents of current design libraries WORK (/user/ron/work) entity : p add architecture : add(cla) architecture : m add(rpl) package : components entity : design architecture : m design(structural) package : types p ––– This design has parameters m ––– This architecture is the most recently analyzed In this example D–1, the contents of the library WORK are listed Since none of the options is used in the command, all information is displayed by default HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference Using Design Units from Design Libraries Design libraries contain both designs and packages These files can be used through the elaborate command, through instantiation, and through the use clause in VHDL Subdesigns are first linked by searching through designs in memory VHDL Compiler then searches in the current design library for preexisting analyzed files of the subdesigns db files in the search path are also automatically linked during elaboration of a top level design The use clause is not used to elaborate subdesigns It is used to resolve packages It can be used to make the subdesign’s entity declaration visible to the design Note: The design file format is not compatible with other releases of the software A version number is stored in the intermediate format file, and the file can be read in only by the version in which it was created You can use the elaborate command to build the intermediate format for configurations and entities into designs The syntax is elaborate [–parameters parameter_list] [–library library_name][–update] [–architecture architecture_name] design_name –parameters parameter_list Defines the list of parameters for the design Parameters within the list must be separated by commas Different parameters can be distinguished by name (”N=8,M=6”) or by position (”8,7,5”) HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center V3.4 VHDL Compiler Reference –library library_name Designates the library in which the design file is found –update Causes all out-of-date intermediate format files to be analyzed again –architecture architecture_name Defines the implementation of the design design_name Is the name of the design file to be elaborated The –update option causes outdated design units to be analyzed again A design unit is outdated if its source code has changed or if it depends on other design units that have been analyzed more recently The second method for using designs from design libraries is through instantiation For example, in VHDL, you can instantiate the design adder by using U1: adder generic map(N => 16) port(A,B,Z); In Verilog, the functionally equivalent statement is adder #(16) U1(A,B,Z); Finally, you can use packages from design libraries with the VHDL use clause The use clause allows an entity to use a package from a library The syntax of the use clause is use library_name.package_name.all; library_name is the name of the library where the package is and package_name is the name of the package to be used HOME CONTENTS INDEX For further assistance, email support_center@synopsys.com or call your local support center