Luận văn, Điện tử công suất, đề tài tốt nghiệp, đồ án, thực tập tốt nghiệp, đề tài
A new modular voltage source inverter topology A. Lesnicar, R. Marquardt INSTITUTE OF POWER ELECTRONICS AND CONTROL Universität der Bundeswehr München Werner-Heisenberg-Weg 39 85577 München, Germany Phone: +49-(0)89-60043938 / Fax+49-(0)89-60043944 e-mail: anton.lesnicar@unibw-muenchen.de http://et6-server.et.unibw-muenchen.de Keywords Multilevel converter, Transmission of electrical energy, HVDC, Power conditioning, Emerging topologies Abstract This paper introduces a new modular multilevel converter (M 2 LC) topology suitable for very high voltage applications, especially network interties in power transmission. The fundamental concept, the applied control scheme and simulation results of a 36MW–network intertie are presented. With reference to the expenditure of components, a comparison between the new modular multilevel converter and a conventional converter topology is given. A suitable structure of the converter control is proposed. 1 Introduction The deregulation of international energy markets and the trend to decentralized power generation are increasing the demand for advanced power electronic systems. For this application field, multilevel converters with a high number of voltage levels are the most suitable types, because of the need for multiple series connection of semiconductors and low voltage distortion on the line side [1-3]. Besides these points, a lot of other important aspects have to be taken into account for these applications. Main technical and economical aspects for the development of multilevel converters are: Modular realization: - scalable to different power- and voltage levels - insensitive to variable semiconductor parameters Multilevel waveform: - expandable to any number of voltage steps - low total harmonic distortion - dynamic voltage sharing of the power devices High availability: - use of approved semiconductor devices - redundant operation Failure management: - fail safe operation on device failures - avoidance of mechanical destruction (high magnetic forces caused by surge currents) Investment and life cycle cost: - modular construction - standard components 2 Concept of the new Modular MultiLevel Converter M 2 LC 2.1 Principle of M 2 LC In order to fulfil the above mentioned requirements, a converter system solely composed of an arbitrary number of identical “submodules” was a prerequisite. For the sake of stringent modular and scalable realization, additional “central” components have to be avoided. The DC-link capacitor of conventional voltage source inverters presents an example of such a component – independent of its realization out of a number of series connected capacitors or not. The same applies to the associated high voltage, low inductance DC-bus bars. The new concept consists of submodules which are two terminal devices composed of switches and a local DC-storage capacitor C 0 (Fig. 1, 2). No additional external connection or energy transmission to the submodules is needed, for full 4-quadrant operation of the converter system. The interface is composed solely of two electrical terminals and one bi-directional fibre-optic cable. By this means, the voltage of each submodule is transmitted and can be freely controlled by software. The individual voltages of the submodules may even be chosen unequal. This can be used to increase the number of resulting voltage steps (e.g. together with PWM-operation). Unlike the conventional VSI, a common central capacitive storage is abundant. This advantage eases the protection of the converter against mechanical destruction in case of a short circuit or insulation failures, significantly. In addition, a defective submodule can be replaced by a redundant submodule in the arm without the need for mechanical switches. This results in an increased safety and availability. Fig. 1 illustrates an inverter leg consisting of n submodules in each arm. In a first step, the submodules can be considered as controlled voltage sources. In this given structure, it can be shown that the submodules must be able to carry a DC-component ( i 0 a ≠ ) of the current i a , but do not have to supply real power in steady state operation. Concerning control, a realization with 2-level voltage sources leads to the simplest realization (Fig. 2). A realization with 3-level voltage sources leads to a generalized concept for “matrix type” converters [8]. Regardless of the sign of the current i a,i , the terminal voltage V x,i of each submodule can be impressed. By switching a number of the n submodules in the upper and lower arm, the voltage V N is adjusted. In a similar manner, the voltage V d can be adjusted, independently. P N V d i a.1 V d 2 V d 2 V x2.n V x2.1 V x1.n V x1.1 i a.2 i N V N SM SM SM SM N Fig. 1: Inverter leg consisting of 2n submodules Only the sum of the voltages V d (t) and V N (t) is restricted depending on the number n of submodules per arm: CNd Vn2)t(V2)t(V ⋅⋅≤⋅+ (1) When - for example - Cd VnV ⋅= is chosen, the amplitude of the output voltage will be restricted to: CN VnV ˆ ⋅≤ (2) + - i C i T1 T 2 i FD1 i a i FD2 i T2 C 0 T 1 V X V C + - q·I d i T1 T 1 T 2 i FD1 i N C d V d D 1 D 1 D 2 D 2 i T2 i FD2 i C P N + - i C i T1 T 2 i FD1 i a i FD2 i T2 C 0 T 1 V X V C + - q·I d i T1 T 1 T 2 i FD1 i N C d V d D 1 D 1 D 2 D 2 i T2 i FD2 i C P N Fig. 2: Structure of a submodule (SM) Fig. 3: Structure of a conventional leg (Two terminal device) (Three terminal device) 2.2 Concept of controlled voltage balancing In order to keep the capacitors on the same voltage level and to ensure equal stress for the power devices the following algorithm is applied for each arm: The voltages of the capacitors are periodically measured with a typical sampling-rate in the millisecond-range. According to their voltage, the capacitors are sorted by software. In case of positive current in the arm the required number of submodules, determined by output state controller, with the lowest voltages are switched on. When the current in the corresponding arm is negative, the demanded number of submodules with the highest voltages are selected. Instead of measuring the current in the arm, the information about the sign may be derived from the voltage difference of two subsequent voltage samples. By this method, continuous balancing of the capacitor voltages is achieved. Inherently, this concept supports an optimized utilisation of the stored energy and evenly distributed power losses for the installed electrical devices. Additionally, the power losses can be kept low by switching the submodules solely, when a change of the output state is requested. 3 Control scheme With regard to the modular and scalable topology of the M 2 LC, the applied control scheme should be easily expandable to any number of levels. With this in mind, the space-vector PWM is a suitable control scheme. In general, all concepts based on the space-vector PWM theory are compatible with the following concept: The first task is the transformation of the three phase voltages into the two-dimensional space by using the equation (3). ⋅ −+ −− ⋅= 3 2 1 Im Re v v v 2 3 2 3 0 2 1 2 1 1 3 2 v v (3) The second step is to find the three active switching vectors adjacent to the setpoint vector v ref . The three active switching points next to the setpoint vector have to be located to minimize the harmonics. Finally, the correspondent dwelling times have to be calculated [3]-[6]. As an example Fig. 4 shows a 5-level space-vector diagram, assuming that the capacitor-voltages of the submodules are equal and scaled to the value 1. (From this it follows that the normalized terminal- voltages V X of the submodules have either the value 0 or 1.) −3.33 −2.67 2.67 3.33 −2.00 −1.33 −0.67 −0.00 0.67 1.33 2.00 2.89 2.31 1.73 1.15 0.58 0.00 −0.58 −1.15 −1.73 −2.31 −2.89 Re Im 1 3 4 5 2 Fig. 4: Space-vector diagram of a 5-level converter with the corresponding number of possible different DC-link voltages The M 2 LC offers the degree of freedom to control the DC-link voltage directly, using the different switching states. The proposed control scheme adopts the fundamental principles of the abovementioned general concept of space-vector theory. In addition to the two dimensions, the DC- voltage V d can be taken into account. This results in a three-dimensional space consisting of tetrahedrons. 0 20.00m3.33m 6.67m 10.00m 13.33m 16.67m -5.0 5.0 0.0 -4.0 -3.0 -2.0 -1.0 1.0 2.0 3.0 4.0 time[ms] 0 20.00m3.33m 6.67m 10.00m 13.33m 16.67m -1.33 1.33 0.0 -1.00 -0.67 -0.33 0.33 0.67 1.00 time[ms] Fig. 6: Line-to-line voltages Fig. 7: Example of common-mode voltage (5-level topology, normalized to V C ) (corresponding to Fig. 6) For synthesizing the setpoint vector by using the most convenient switching states, a suitable algorithm shall be roughly described: In the same way, like in the planar representation, the phase voltages have to be transformed. The third dimension is given by the DC-voltage axis. The next surrounding switching-state vectors to the setpoint vector have to be located. Compared to the planar graph now 4 points have to be determined, which encase the setpoint vector by a tetrahedron. Analogue to the conventional duty cycle computation the four dwelling times of the correspondent switching-state vector can be calculated. Simulation results of the three-phase voltages using the proposed space-vector PWM are shown in Fig. 6. 4 Simulation results A network intertie model has been built and tested to verify the concept. For this task, the program SIMPLORER was used. A prototype of a 2 MW converter system is under construction. In the model, 5 inverter legs are connected to a common DC-link (one three-phase inverter and one single phase inverter). Each arm is composed of 22 identical submodules (Fig. 8). No additional, central, capacitive energy storage at the DC-link is installed. V d N 0 V 12 V 23 V 45 V 31 n=22 SM SM SM SM SMSM SM SMSM SMSM SM SM SM SM SM SMSMSM SM N 0 P N i a.11 i a.15 i a.14 i a.13 i a.12 V d controlled V d 0 time[ms] 10.0 20.0 30.0 40.0 50.0 60.0 70.0 20.0 10.0 0 - 10.0 - 20.0 - 30.0 - 40.0 40.0 30.0 50.0 U[kV] 80.0 V d V45 P out i a.14 Fig. 8: Model of network intertie Fig. 9a: Output voltage and DC-link voltage 0 80.010.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 0 -50.0 -40.0 -30.0 -20.0 -10.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 time [ms] P in P[MW] 0 80.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 -0.5 U[kV] 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 time [ms] -1. 0 I[kA] 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 V C V C.1 - V C.22 Fig. 9b: Input and output power versus time Fig. 9c: Current and submodule voltages in an arm Parameters: Transmitted real power P d = 36 MW; C 0 = 2.0 mF; single-phase-system: V 1,rms =25.0 kV, f 1 = 25 Hz; three-phase-system: V 3,rms =23.0 kV, f 3 = 60 Hz) The curves shown in Fig. 9a, 9b and 9c are under steady state conditions. The single phase and the three phase voltages are synthesized by 21 levels (+1 redundant submodule). As mentioned above, the DC-voltage V d has been controlled by appropriate control of the switching states, too. Fig. 9a shows the controlled DC-link voltage. By this means, the expected, severe voltage pulsation caused by the single phase supply could be remarkably suppressed. The remaining low ripple content of the 2 nd harmonic on the DC-link voltage has no effect on the input and output power characteristic (Fig 9b). Fig. 9c illustrates the good voltage balancing of the submodule voltages in an arm and the associated current in the arm. The voltage ripple of the submodules has been chosen high, in order to demonstrate the capabilities of the system. Another characteristic of the M 2 LC-converter is the very low di/dt of the (internal) arm currents. The possible control of the converter, however, has not yet been fully optimized - as may be seen from the low amplitude oscillations in the arm current. 5 Expenditure of installed components Because the structure of M 2 LC is quite different from conventional converters, a comparison with respect to the expenditure of the installed components is not a simple task. At least, the following major points should be taken into account: 1. Sum of the installed, stored energy of the converter (i.e. capacitors) 2. Sum of the power losses of the silicon devices 3. Required, total silicon area of the converter 4. Number of switches, gate drivers and snubbers 5. Mechanical construction requirements including low inductance bus bars at high voltage and high surge current 6. Protection hardware The comparison must be based on an equal power and voltage level. In order to be precise, the technical requirements of a certain application must be considered. On the other hand, an analytical investigation can contribute to better basic understanding of the main points. In the following, this investigation will be given – focused on the important points 1 to 3. With respect to the remaining points, a brief comment shall be given: Point 4 is a clear disadvantage of the M 2 LC – concept, because the number of switches is doubled compared to a conventional converter. The number of switches, however, is less important than the total required silicon area (point 3) when using modern MOS-gated and snubberless devices. The points 5 and 6 are clear advantages of the new system, because the absence of heavy high voltage bus bars and additional protection hardware enables a modular, simple and robust mechanical construction of the whole converter. The absence of passive filters and the resulting superior control characteristics are important advantages, too [8]. 5.1 Capacitive energy storage requirement An analytical expression of the required, total stored energy (point 1) can be given under the following conditions: a) Sine wave output voltages (V N ) and line currents (i N ) b) Smooth DC-link voltage (V d ) c) Equally divided real power flow of the converter legs These conditions are not necessary for operation of the converter, but they are fulfilled with good approximation, in general. Condition b) leads to a very simple expression of the real power flow dd PVI=⋅ d (5) where d I denotes the average current in the DC-link (Fig. 8). Condition c) gives the DC-component of the converter arm current. a iqI=⋅ d (6) where q denotes a constant share of d I , depending on the number of converter legs sharing the real power flow. For the single phase converter section – which shall be discussed here – this value is . Defining a normalized current ratio: 0.5q = ˆ N d i m I = (7) of peak line current to DC-current, it becomes possible to express the pulsation of energy ( ) per submodule, directly: SM W∆ 3 2 2 1 1 2 d SM N mP W nm ω ⋅ ∆= − ⋅⋅ (8) In this equation, N ω denotes the angular frequency of the line current (a more detailed explanation of these equations is given in [2]). It shall be noticed, that the current ratio (m) – because of basic laws of physics – is restricted to values , for all possible output voltages (V 2m ≥ N ) and arbitrary power factor. The necessary capacitance of each submodule follows from equation (8), when the ripple factor of the submodule voltage (0 < ε < 0.5) is introduced: () 2 3 2 N 2 C d 0 m 1 1 nU4 Pm C − ⋅⋅⋅⋅ ⋅ = ωε (9) The comparison of stored energy of a conventional converter (with central DC-link capacitors) depends on the particular application. If there are requirements concerning operation with short line interruptions or operation on single phase lines, the M 2 LC compares very well - see [2] and [8] for examples. When none of these requirements exist, a conventional 3-phase/3-phase – converter system could be equipped with negligible DC-link capacitance – depending only on pulse frequency, theoretically. In these applications the M 2 LC would not compare well, because it needs a considerably higher minimum of installed energy for operation. For the present application (Fig. 8 and 9) it turned out, that the M 2 LC – converter could operate with about the same amount of capacitive stored energy, than a conventional voltage source converter of the same power rating – but it is saving the installed magnetic energy of the additional passive filters. 5.2 Required silicon area and power losses The required total silicon area of the converter gives a good approximation of the cost, especially when used only for comparison at the same semiconductor voltage level and the same cooling system. The required total silicon area can be assumed to be proportional to the total semiconductor power losses,, if the cooling system is the limiting factor. This assumption is reasonable for high power converters and will be made here, in order to enable an analytical comparison. In a next step, the load dependent peak junction temperature and peak current for any semiconductor chip would have to be considered. This, however, can be done for a special application, only. It will be seen from the following analysis, that this is not necessary for a basic comparison. Concerning semiconductor losses, the switching losses shall be discussed first: The conventional leg with direct series connection (Fig. 3) needs a high switching frequency, in order to assure a reasonable quality of the line currents spectrum. Multi level waveforms enable better quality at reduced switching frequencies, which is well known. With respect to this point, the M 2 LC-converter is similar to a multi- level-diode-clamped converter. In addition, it gives the control freedom, to ensure ideal sharing of the switching losses of all the submodules in each arm. Owing to these reasons, the following comparison will focus on the on state losses. The on state losses of an IGBT (or free wheeling diode) can be expressed in the form (see Fig. 3) * FTF PiU=⋅ (10) where T i represents the IGBT average current (arithmetic mean value) and U represents an “equivalent on state voltage”, which has to be determined form the current wave form of the load current. Even if i is completely unknown, it can be proven that U must be in the range: * F () T t * F * ˆ () ( FN F FN Ui U Ui≤≤ ) (11) Using this approach, a general comparison of on state losses F P becomes possible, when the semiconductor average current T i , the average of the absolute value of the load current N i and the peak value of the load current i is known. The arithmetic mean values of the semi-conductor currents ( ˆ N T i , FD i ) can be expressed in general equations, based on Kirchhoff’s law (see Table 1). When the on state voltages of IGBT and diodes are similar, a comprehensive result for the on state losses ( F P ∑ ) can be given, finally. (16) Table I: On state power dissipation of the semiconductor devices (for comparison) submodule (two terminal device) conventional leg (three terminal device) => 2 I 4 1 ii N 1FD1T ⋅== (12.a) 2 11 42 2 N T I =⋅ + ⋅ d Iiq (13) 2 11 42 2 N FD d I =⋅ − ⋅iq (14.a) I Maximum peak current in any semiconductor: 11 ˆˆ 24 TN ≤⋅+ ˆ N iii (15.a) Power dissipation with 2n submodules per leg: * 2 2 N FF I PU=⋅⋅ ∑ n (16.a) dN2T1T Iq 2 1 I 4 1 i ⋅⋅+⋅==i (12.b) dN2FD1FD Iq 2 1 I 4 1 i ⋅⋅−⋅==i (14.b) Maximum peak current in any semiconductor ˆˆ T ii N ≤ (15.b) Power dissipation with 2n switches per leg: * FNF PIUn= ⋅⋅ ∑ (16.b) As may be noticed form Table I, the submodules of the M 2 LC-converter are carrying half of the AC- current (i N ) amplitude, only. The peak current (î T ) is lower, too (see (10.a) for the worst case m=2). Owing to these reasons, the resulting total on state losses ( F P ∑ ) would be lower than for the conventional leg. This is not true, however, when the total silicon area of both converters is made equal. When the silicon area per IGBT (and diode) is reduced in accordance with the reduced average current ( T i ) in the M 2 LC, the total on state losses ( F P ∑ ) of both converters become very similar. This result has been proven (with a reasonable accuracy of approximately ±10%) by several detailed computations for actual applications. 6 Structure of M 2 LC-control The following control structure for M 2 LC is chosen (Fig. 10), consisting of three different fundamental units. d u p l e x o p t i c a l - f i b r e cable Converter Cubicle • • • flat ribbon cable Supervisory Computer Central Control Unit (CCU) I n t e r f a c e Submodule T1,T2 Vc1 Vc1 I n t e r f a c e Arm-Circuit Current Measurement A Submodule T1,T2 Vc1 Submodule T1,T2 Vc1 Vc1 Fig. 10: Structure of M 2 LC – control The supervisory unit manages the feedback and general control of the entire system. According to the setpoint values, the feedback control supplies data to the central control unit in real-time mode. A digital signal processor DSP (or FPGA) is well suited to solve these tasks. The presented concept of voltage balancing is implemented in the modulator. The output state controller - which has to determine the optimized output states and the operating sequence for the next PWM-period - is integrated, too. The PWM-generator calculates the dwelling-times for the appendant switching states. The converter cubicles are equipped with a number of identical submodules, which are connected to the central control unit solely by duplex optical-fibre cable. Each submodule receives the correspondent switching commands, opto-electronically and sends its capacitor-voltage back to the central control unit, periodically. The power supply voltage for data transfer and the drive circuits of the IGBTs is supplied from the local capacitor of the submodule [7]. The system for current measurement is connected fibre-optically, too. This structure leads to clear and safe separation of the low voltage and the high voltage part of the system. 7 Conclusion This paper introduced the topology of the new modular multilevel converter M 2 LC and its relevant characteristics. The modular concept allows the application for a wide power range. The proposed control scheme is well suited for a different number of voltage levels. It is shown that the control scheme allows to control phase-voltages and the DC-voltage at the same time, independently. Simulations have demonstrated a good performance of the M 2 LC-concept. The start under de- energized condition can be safely realized. The structure of M 2 LC-control enables good separation of the low voltage units and the high voltage units of the converter cubicles. Presently, a prototype of a 2 MW – converter system is being built. This modular system will enable further experimental investigations. 8 References 1. Jih-Sheng Lai, Fang Zheng Peng, “Multilevel Converters – A new breed of power converters”, IEEE Trans. Ind. Applicat., vol. 32, pp 509-517, May./June. 1996 2. Rainer Marquardt, Anton Lesnicar, Jürgen Hildinger, “Modulares Stromrichterkonzept für Netzkupplungsanwendung bei hohen Spannungen”, ETG-Fachtagung, Bad Nauheim, Germany, 2002 3. José Rodriguez, Jih-Sheng Lai, Fang Zheng Peng, “Multilevel Inverters: A survey of topologies, controls, and applications”, IEEE Trans. Ind. Electr., vol. 49, pp 724-738, Aug. 2002 4. A. R. Bakhshai, H. R. Saligheh Rad, G. Joos, “Space vector modulation based on classification method in three- phase multi-level voltage source inverters”, IEEE Trans. Ind. Applicat., vol. 1, pp 597 – 602, Sep./Oct. 2001 5. Nikola Celanovic, Dushan Boroyevich, “A fast space-vector modulation algorithm for multilevel three- phase converters”, IEEE Trans. Ind. Applicat. vol. 37, pp 637 – 641, March/April 2001 6. Fei Wang, “Sine-triangle versus space-vector-modulation for three level PWM voltage-source inverters“, IEEE Trans. Ind. Applicat. vol. 38, pp 500 – 506, March/April 2002 7. Jürgen Hildinger, Rainer Marquardt, “Erzeugung stabilisierter Hilfsspannungen aus dem Leistungsteil von U-Umrichtern”, ETG-Fachtagung, Bad Nauheim, Germany, 2002 8. Martin Glinka, Rainer Marquardt, , “A New Single Phase AC/AC-Multilevel Converter For Traction Vehicles Operating on AC Line Voltage”, EPE 2003