Optimizing designs

Part Optimizing Designs In this part of the book we will introduce a number of ‘advanced’ topics In the other parts of the book, the emphasis is on the ‘what’, however in this part is it more about the ‘how’ How can we make designs synthesize? How can our designs be made smaller or faster? How can we interface to mixed signal systems in practice? How can we develop verifiable designs? All of these design challenges will be addressed in this part of the book This page intentionally left blank 14 Synthesis Introduction The original intention of VHDL was to have a design specification language for digital circuits The main goal of the work was to have a design representation that could be simulated to test whether the specification was fit for purpose When VHDL was standardized as IEEE Std 1076, the broader application of VHDL for not just simulation but as an integral part of the hardware design flow became possible The original method of designing digital circuits was primarily through the development of schematic-based designs, using gate libraries to effectively generate Register Transfer Logic (RTL) netlists directly from the schematics This is clearly a reasonable technique when the designs are relatively small, however it quickly becomes apparent that for designs of any size this approach is simply not realistic for modern Field Programmable Gate Arrays (FPGAs) that require millions of gates EDA companies realized fairly early on in the VHDL development process that if there was a standard language that could represent a data flow and a control flow, then the potential existed for automatically generating the gate level VHDL from a higher level description, and RTL was the obvious place to start RTL has the advantage of representing the data flow and control flow directly, and can be mapped easily onto standard gate level logic The resulting synthesis software (such as the Design Compiler from Synopsys) quickly established an important role in the digital design flow for both ASIC and FPGA designs and have in fact provided to be the driving force in the explosion of productivity of digital designers The modern high density designs would not be possible without RTL synthesis Design Recipes for FPGAs As such, modern day designers often simplify ‘RTL synthesis’ to just ‘synthesis’, however this is not the whole story As designs have continued to get more complex, there has been a push to ever increasing behavioral synthesis however there is not the same support from the EDA industry for behavioral synthesis software VHDL supported in RTL synthesis While VHDL is standardized, synthesis is not, and as such the VHDL that can be synthesized is a subset of the complete VHDL language Another common problem for designers is the fact that different synthesis software packages will give different output results for the same input VHDL, even to the extent that some will synthesize and some will not under certain conditions There are some standard VHDL techniques that cannot be synthesized however and these are summarized in this chapter There are two types of unsupported elements in VHDL – those that will cause a synthesis failure and those that are ignored The failure elements are in many respects easier to manage as the synthesis software will provide an error message It is the ‘ignored’ elements that can be more insidious as they can obviously leave errors in the synthesized design that may not be picked up until the hardware is tested Initial conditions VHDL supports the initial condition being set for signals and variables, however this is not physically realized In practice the initial conditions in the synthesized design are random and so in a practical design a reset condition should always be defined using an external reset pin This is because during synthesis, the initial conditions are ignored Concurrent edges It is common to use a clock edge as a trigger for a model, so a simple VHDL model may have a process with VHDL something like this to wait for the rising edge of a clock: Process (clk) If rising_edge(clk) then Q