Expanding Memory and I-O

Chapter 13 Expanding Memory and I/O Since the H8/3048 has a 128kbyte internal ROM and an 8kbyte internal RAM, it can accommodate a relatively large program without externally expanding the memory If the internal memory is insufficient, however, you can externally expand it, which is essential for hardware design engineers to know Although software engineers can still develop programs without this knowledge, they are also expected to understand some of the basic techniques Although the H8/3048 can accommodate a dynamic RAM, this chapter focuses on the basic functions and describes the ROM and static RAM In this chapter, you learn about which signals are required for expanding the memory, how they change at reading/writing and how to calculate if the CPU and memory speed match This chapter also helps you understand memory signals and timings Note: The following are negative logic signals: Although the H8/3048 has an internal ROM and RAM, external memory expansion may be required due to insufficient capacity The following describes how to connect the memory and CPU and match their speeds using EPROM and SRAM as examples 13.1 H8/3048 Operating Mode When expanding the H8/3048 memory, you can determine how much memory capacity to be added and how to use the data bus The mode set pins (MD0, MD1 and MD2) are used to select one of seven operating modes, which determine the uses of the address bus, data bus and read/write signals Table 13.1 shows each mode: * Status at resetting It is available as either an 8- or 16-bit bus according to the setting Since mode represents single-chip mode, no external memory can be added http://resource.renesas.com Page 161 Table 13.1: H8/3048 Operating Mode The internal ROM and RAM are always connected to the CPU through the 16-bit data bus irrespective of the mode setting "Disabled" in the "Internal ROM" column means that the internal ROM, though it exists, is disabled by being disconnected from the CPU In this case, an external ROM must be connected When the internal ROM and RAM are enabled, no external memory can be added to the same address If the same address is used, the internal memory has priority, disabling reading/writing from/to the externally connected memory 13.2 Pins for Memory Connection Table 13.2 shows the pins relating to memory connection provided for the H8/3048 and their functions Connected memory size Since there are 24 address buses (A0 to A23), up to 16Mbytes of memory can be connected If the memory to be connected is 1Mbyte or smaller, only 20 address buses (A0 to A19) are required and the remaining pins can be used for other purposes Data bus width Since the H8/300H is a 16-bit CPU, it has 16 pins (D0 to D15) for reading and writing 16-bit data If word data is allowed to be divided into two by the MOV.W instruction, only data bus pins (D8 to D15) are required and the remaining pins (D0 to D7) can be used for other purposes As described above, the use of pins determines whether the memory address is 16M or 1M and the data bus is either 16 or bits So you have to figure out the most effective use with the limited number of pins http://resource.renesas.com Page 162 Table 13.2: Pins Relating to Memory Connection Address strobe Indicates that an address is valid and that it is external when it is at low level It is not set at low level if an address is internal (internal ROM or RAM) When the CPU is reading or writing data from/to the internal ROM or RAM, reading/writing is not available externally The RD, HWR and LWR signals are not changed to low level, either Read/write signals When the data bus width is bits (RD and HWR are used): Data buses D8 to D15 are used, and D0 to D7 are not http://resource.renesas.com Page 163 When the data bus width is 16 bits (RD, HWR and LWR are used): The RD signal is used as the read signal for both 8- and 16-bit widths, the HWR signal is used for writing to an even-numbered address, and the LWR signal is used for writing to an odd-numbered address During 16-bit data writing, both the HWR and LWR signals are output For details, refer to the section describing connection between the CPU and memory [Explanation with motion pictures and sound] 13.3 Read Timing from External Memory Figure 13.1 shows the read timing from an external memory This is an example for 24-bit address and 16-bit data buses Reading is completed in a 3system clock time (3-state access) To read data or instructions from the memory, the setup time and hold time of the read data must be satisfied http://resource.renesas.com Page 164 Figure 13.1: Read Timing from External Memory 13.4 Write Timing to External Memory Figure 13.2 shows the write timing to an external memory This is an example for 24-bit address and 16-bit data buses Writing is completed in a 3-system clock time (3-state access) Figure 13.2: Write Timing to External Memory http://resource.renesas.com Page 165 Figure 13.3 shows the read/write timings including waits If the WAIT input is at low level at the trailing edge of T2, the CPU inserts a wait state to slow reading/writing When the WAIT input is returned to high level, reading/writing is completed Depending on the address output by the CPU, users have to design circuits to input WAIT signals if the memory connected to the address is slow, or to prevent WAIT signals from being input if it is fast The H8/3048 is provided with a wait state controller so that the wait state can be input without creating such circuits Figure 13.3: Read/Write Timings Including Waits Since the H8/3048 has an internal wait controller, waits can be inserted in various ways Wait state controller enable register (WCER) Determines for which area the wait state controller is enabled from area to area WCER H'FFFFEF address http://resource.renesas.com Page 166 Figure 13.4: Wait State Controller Enable Register (WCER) The wait state controller is enabled for the area with "1" written and disabled for that with "0" By default, it is enabled for all areas Wait control register Determines how to insert waits for the wait-enabled area WCR H'FFFFEE address Figure 13.5: Wait Control Register (WCR) Wait mode select and01 (WMS1 and WMS0) Programmable wait mode Without using the WAIT pin, forcibly inserts the wait set by the wait count Pin wait mode Waits for the wait cycle specified by the program and inserts an additional wait depending on the WAIT pin status (Figure 13.3) Pin auto wait mode The WAIT signal input to the WAIT pin only determines whether to insert a wait state or not, and how many states to be inserted is determined by the wait count Wait is inserted as necessary Wait count and01 (WC1 and WC0) http://resource.renesas.com Page 167 This determines how many wait states to be inserted in a programmable wait or pin auto wait mode By default, the wait controller is enabled for all areas and three states are set to be inserted in programmable wait mode In other words, three wait states are forcibly inserted in all areas Change the setting as soon as possible after resetting if necessary 13.5 Sample Memory (EPROM) The HN27C4001G is used here as an EPROM example The HN27C4001G has a 4Mbit capacity and 524288 word × bit configuration Figure 13.6 shows the pin assignment Figure 13.6: NH27C4001G Pin Assignment Diagram There are 19 address input pins, A0 to A18.Since addresses are input in 19-bit units, this memory has 512-kbyte (to be more precise, 524,288) addresses The address count of the memory IC is determined by the address pin count There are data pins, I/O0 to I/O7, meaning that the memory uses bits per address Since this is a ROM, it is a read only memory when connected to a CPU and the data pins are set to output They are changed to input pins for writing by an EPROM writer Here, we consider the case in which it is connected to a CPU and serves as a ROM only The Vpp pin is designed to apply the write voltage (12V) for writing by an EPROM writer It is fixed to high or low level for operation as a ROM with connection to a CPU http://resource.renesas.com Page 168 CE (Chip Enable) is a memory select signal and the memory is selected when it is set at low level This is used to assign a specific address by adding an address-decoded signal OE (Output Enable) is an output enable signal and read data is output from a data pin when it is set at low level The table below summarizes this In read mode, the CPU reads data from the EPROM and sets both CE and OE at low level In output disable mode, the memory is selected but read data is not output to an I/O pin The I/O pin is set in high impedance mode (disconnected state) In standby mode, the memory is not selected When CE is set at high level, the system is set in standby mode irrespective of the OE setting Since the memory IC is not operating in this mode, power consumption is low Table 13.3 shows the HN27C4001G read timing There are 100ns and 120ns types Table 13.3: HN27C4001G Read Timing Read timing waveform Figure 13.7 shows the HN27C4001G read timing Read data is output from an I/O pin when the access time (tACC), CE output delay time (tCE) and OE output delay time (tOE) are satisfied http://resource.renesas.com Page 169 Figure 13.7: Read Timing Waveform 13.6 Sample Memory (SRAM) The HM628512BI is used here as a static RAM example It has a 4Mbit memory capacity and 524288 word × bit configuration Figure 13.8 shows the pin assignment Figure 13.8: HN628512BI Pin Assignment There are 19 address pins, using 512 kbytes, and data pins, using bits per address http://resource.renesas.com Page 170 Figure 13.17: Setup Time Calculation (1) Data are output from the memory only when all the access time, OE output delay time and CE output delay time requirements are satisfied Address delay time + Access time = 30ns + 100ns (max.) = 130ns (max.) Refer to Figure 13.18 Figure 13.18: Setup Time Calculation (2) Time until the read signal is output + OE output delay time = 50ns + 30ns (max.) + 60ns (max.) = 140ns (max.) Refer to Figure 13.19 http://resource.renesas.com Page 179 Figure 13.19: Setup Time Calculation (3) Time until the address strobe is output + Decoder delay time + CE output delay time = 50ns + 30ns (max.) + 10.5ns (max.) + 100ns (max.) = 190.5ns (max.) Refer to Figure 13.20 Figure 13.20: Setup Time Calculation (4) The longest time for data to be output is 190.5ns due to the CE output delay time As for the setup time, it causes no problem since the calculation results are 190.5ns (max.) against the requirement of 240ns (max.), providing an allowance of about 50ns Hold time calculation The input data hold time required by the H8/3048F is 0ns (min.) for the address strobe leading edge In other words, it is acceptable as long as data are not changed before the address strobe leading edge The following three factors change data in the memory: - An address is changed - CE is set at high level - OE is set at high level http://resource.renesas.com Page 180 An address is changed after the address hold time has passed following the address strobe leading edge As a result, the hold time of 0ns (min.) is secured On the other hand, CE is set at high level after the decoder delay time has passed following the address strobe leading edge As a result, the hold time of 0ns (min.) is also secured As for OE, RD is used as it is RD is set at high level at the same time AS is set at high level The memory outputs data for 0ns (min.) after OE is set at high level As described above, the hold time of 0ns (min.) is satisfied in all cases Consequently, you can see that the requirements for both setup and hold times are satisfied regarding EPROM reading This method has a wide range of uses and can be applied to various connections between the CPU and the memory The setup time required by the CPU, however, may not be satisfied if the address decoder delay time is long In addition, the address strobe (AS) is used in the address decode circuit and delayed AS tightens the requirement for the setup time To simplify a decode circuit, the H8/3048 is provided with signals from CS0 to CS7 These signals are obtained by decoding the upper bits of the CPU addresses Since bits are decoded, the 16Mbyte memory space is divided into equal parts These are called area to area When the CPU accesses area 0, CS0 is set at low level This is shown in Table 13.9 Table 13.9: Address Decoding Using Chip Select Signals In the case of the H8/3048, the CS0 to CS7 signals are available instead of the AS signals In this case, bits of addresses need not be decoded In addition, the CS0 to CS7 signals are output faster than the AS signals and at the same timing as address signals, allowing for setup time and enabling slower memory to be connected In order to use the CS0 to CS7 signals, you must set the bus controller accordingly Since CS0 to CS3 are commonly used with port 8, set the corresponding bit of the P8DDR at (output) http://resource.renesas.com Page 181 Figure 13.21: Port Data Direction Register (P8DDR) CS0, CS1, CS2 and CS3 correspond to P84DDR, P83DDR, P82DDR and P81DDR, respectively, and are switched to chip select pins when is written In internal ROM disable mode, however, the CS0 pin is set at and enabled by default The data direction register is a write-only register and thus incapable of reading This means that the bit handling instruction is not available for it CS0 to CS3 can be used as chip select signals simply by setting the P8DDR CS4 to CS7, on the other hand, can be used as chip select signals simply by setting the chip select control register Figure 13.22: Chip Select Control Register (CSCR) CS7E, CS6E, CS5E and CS4E correspond to CS7, CS6, CS5 and CS4, respectively, and are switched to chip select pins when is written Since the EPROM is connected to the H'000000 address, it is assigned as area and uses CS0.If CS0 is L and both A20 and A19 are 0, it is the EPROM address Figure 13.23 shows a decode circuit using CS0 Figure 13.23: Decode Circuit Using CS0 http://resource.renesas.com Page 182 13.8 Connecting CPU to Memory (Connecting SRAM Using 8-bit Data Bus) This section considers a case for connecting a 512kbyte SRAM (HM628512BI-8) to a CPU Although you only need take read timings into account for connecting to an EPROM, both read and write timings must be matched for a RAM Since there is no specific address for a RAM to be connected, locate it next to the EPROM between H'080000 and H'0FFFFF The SRAM address is where CS0 = L, A20 = and A19 = For connection to the CPU, connect the high-write (HWR) of the CPU to the write enable (WE) of the memory As with the EPROM, connect the read (RD) of the CPU to the output enable (OE) of the memory Connection between the CPU and the SRAM is shown in Figure 13.24 Figure 13.24: Connection Between CPU and SRAM Timing calculation (read timings) Read timings are calculated in the same way for both EPROM and SRAM As described earlier, the address access time for the EPROM is 100ns and both the setup and hold times are satisfied Since it is 85ns at the slowest for the SRAM (HM628256BI), requirements are completely satisfied Specific calculations are omitted here Timing calculation (write timings) Figure 13.25 shows the CPU write cycle waveform required for timing calculation http://resource.renesas.com Page 183 Figure 13.25: CPU Write Cycle Waveform The following are important for write timings as specified by the SRAM standard: Input data setup time (tDW) = 35ns (min.) Input data hold time (tDH) = 0ns (min.) Writing is conducted at either the CS or WE leading edge, whichever is earlier WE inputs the HWR signals of the CPU as they are CS is created based on CS0 and address signals and delayed by the decoder delay time As a result, writing is conducted at the WE (HWR) leading edge The setup time is the shortest when write data is output the latest and the WE leading edge is the earliest This is shown in Figure 3.26 You can see that the setup time of 90ns is secured, causing no problem Figure 13.26: SRAM Data Setup Time http://resource.renesas.com Page 184 As for the hold time, there is no problem since the hold time of tWDH = 20ns (min.) is provided for the write data output by the CPU against the WE leading edge 13.9 Connecting CPU to Memory (16-bit Data Bus) When connecting a CPU and a memory using a 16-bit data bus, use a pair of memories having bits per address, or use a memory having 16 data pins The example described here uses a pair of memories having bits per address, which are connected as memories at even- and odd-numbered addresses, respectively To read/write 16-bit data, two addresses must be accessed simultaneously It is impossible, however, to output two addresses to the address bus simultaneously Remember that the upper digits of 16-bit data in the memory must be stored in an even-numbered address and the lower in an odd-numbered address (even-numbered address + 1) An "even-numbered address" and an "even-numbered address + 1" are the same from A23 to A1 in binary notation and only A0 differs No problem arises if A0 is not used, since A1 to A23 are the same A0 = represents an even number and A0 = an odd number A combination of an "odd-numbered address" and an "odd-numbered address + (even-numbered address)" does not make A1 to A23 the same, disabling access as 16-bit data This situation is not limited to the H8/3048 but common to all 16-bit microcomputers HWR and LWR are used instead of the A0 signal HWR = L represents 8-bit writing to an even-numbered address (A0 = 0) and LWR = L means that to an odd-numbered address (A0 = 1) HWR = LWR = L means writing to both even- and odd-numbered addresses Only the RD signal is used for reading by the CPU During reading, data are always handled as 16 bits without distinguishing between 8- and 16-bit data Sixteen bits are read even if the MOV.B instruction is used for reading from the memory Non-used bits are not read into the CPU although they are output from the memory Reading data not required for the memory will not have a negative effect For writing, however, 8- and 16-bit writing must be clearly distinguished since it changes the contents of the memory This is shown in Table 13.10 Table 13.10: Reading/Writing on 16-bit Data Bus http://resource.renesas.com Page 185 Figure 13.27 shows an example to connect the CPU and SRAMs using a 16-bit data bus Figure 13.27: Connection Between CPU and SRAMs (16-bit Data Bus) The capacity becomes 1Mbyte since two SRAMs are connected and the addresses are between H'100000 and H'1FFFFF since CS0 = and A20 = Address, CS and OE signals are commonly input to two memories For the memory at an even-numbered address, HWR is input to the WE pin and the data pins are connected to the upper bits of the CPU As for the memory at an odd-numbered address, on the other hand, LWR is input to the WE pin and the data pins are connected to the lower bits of the CPU 13.10 I/O Port Expansion External expansion of the H8/3048 memory decreases the number of pins available as I/O ports, which may require ports to be externally expanded This section describes how to expand input-only pins and output-only pins using standard CMOS logic Since the memory-mapped I/O method is employed, this I/O function is also connected by assigning addresses to the memory map as with a ROM and RAM described earlier Since the internal peripheral functions are located at area 7, it is assumed here that the I/O ports to be externally expanded are also connected to area HD74AC244 for input ports The HD74AC244 Octal Buffer/Line Driver is a CMOS logic chip having eight 3-state outputs Figure 13.28 shows the pin assignment http://resource.renesas.com Page 186 Figure 13.28: HD74AC244 Pin Assignment Diagram Table 13.11 lists its functions Table 13.11: Function Table Notes: X = Either "H" or "L" Z = High impedance Four buffers are configured into two pairs and each output pin is controlled by the OE1 or OE2 signal, which is transferred from input to output when the OE1 or OE2 pin is set at low When the OE1 or OE2 pin is set at high, the output pins are set in the high-impedance state Since the OE1 and OE2 pins are used as 8-bit input-only pins, it is assumed here that they are short-circuited to serve as one OE pin Eight input pins are connected to external signals and eight output pins to the CPU data bus Input data is output to the data bus when OE is set at low and the following two conditions are satisfied at the same time: • The CPU outputs the address of this input-only port http://resource.renesas.com Page 187 • The RD signal of the CPU is set at low and in the read state Accordingly, the OE signal is created based on address-decoded and RD signals Unlike the memory, the OE signal is regarded to have both CE and OE functions The connection outline to the CPU is shown in Figure 13.29 Figure 13.29: Connection Outline to CPU HD74AC373 for output ports The HD74AC373 Octal Transparent Latch is a D-type latch having eight 3-state outputs Figure 13.30 shows the pin assignment and Table 13.12 lists its functions Figure 13.30: Pin Assignment Diagram http://resource.renesas.com Page 188 Table 13.12: Function Table Notes: X = Either "H" or "L" Z = High impedance O0 = O0 level before the input conditions shown in the table are fixed Figure 13.31 shows the logic diagram Figure 13.31: Logic Diagram When using this IC for output ports, connect D0 to D7 to the data bus and use O0 to O7 as signals to be externally output When the OE pin is set at high, output enters the high-impedance state The OE pin, however, is fixed at low here since the output pins need not be set to high impedance When LE is changed from high to low, the output data at that time is maintained LE is changed to high when the following two conditions are satisfied: • The CPU outputs the address of this output-only port • The HWR signal of the CPU is set at low and in write state Accordingly, the LE signal is created based on address-decoded and HRW signals Unlike the memory, the LE signal is regarded to have both CS and WE functions Figure 13.32 shows connection outline to the CPU http://resource.renesas.com Page 189 Figure 13.32: Connection Outline to CPU Address decoder Both input and output ports have a capacity of only one address when considered as memory If you attempt to fully decode them so that they only have one address, all of the 21 address buses must be decoded, making an extremely complicated circuit Here, we use CS7 only and omit the address decoder As a result, addresses between H'E00000 and H'FFFFFF of area are all used for expanded I/O ports excluding those for the internal RAM and I/O They are used as input ports for reading and output ports for writing As for parts that have overlapping addresses, the internal RAM or I/O port has priority, disabling the CS7, RD and HWR signals to be output Addresses between H'FFFF10 and H'FFFF1B on the boundary between the internal RAM and I/O ports are assumed to be used here The 8-bit absolute addressing instruction is available for these addresses Figure 13.33 shows an expanded I/O circuit Since the CS7 pin is set to input at resetting, pull it up to the power supply http://resource.renesas.com Page 190 Figure 13.33: Expanded I/O Circuit Note the following when using these I/O ports: • Develop a program assuming that the address range is between H'FFFF10 and H'FFFF1B • The addresses of the input and output ports are the same They are used as input ports for reading and output ports for writing • The BTST instruction is available for input ports • Since output ports are dedicated for output, they are incapable of reading the current output state • The BTST, BSET, BCLR and BNOT instructions are not available for output ports • The default values of output ports vary and the output state is not fixed even after the CPU is reset • Instead, they are set by a program • The CS7 signal is not output by default Before using the expanded I/O ports, set CS7E (b7) of CSCR (H'FFFFFF5F address) of the bus controller at 1 Enter an appropriate word in parentheses There is a CPU having 16 address pins and data pins A memory of up to (64k) bytes can be connected to it http://resource.renesas.com Page 191 Since there are 16 address pins, the memory addresses are represented by 16 bits To be precise, a memory of 65536 bytes can be connected since there are to 65535 addresses This is generally referred to as 64kbytes Enter an appropriate word in parentheses There is a memory having 10 address pins and data pins This memory uses (8) bits per address and has a capacity of (1024) addresses Since it has 10 address pins, it has a capacity of 1024 addresses (1k) from to 1023 Eight bits are used for one address since there are data pins Enter an appropriate word in parentheses Up to (64) of 256kbyte memories can be connected to a CPU having a 16Mbyte memory space Dividing 16M by 256k makes 64 To be precise, 16M represents 16777216 and 256k represents 262144 Enter an appropriate word in parentheses In order to read data from an EPROM, both (CE) and (OE) pins must be set at low level The memory IC starts operation when CE (Chip Enable) is set at low level Reading is enabled when OE (Output Enable) is set at low level Enter an appropriate word in parentheses Writing to an SRAM is conducted at the leading edge of either the (CS) or (WE) pin, whichever is earlier The memory IC starts operation when CS (Chip Select) is set at low level Writing is enabled when WE (Write Enable) is set at low level Enter an appropriate word in parentheses When connecting a CPU to a memory using a 16-bit data bus, not use the (A0) pin in the CPU address bus Connect the (upper) bits of the CPU data bus to the memory at an evennumbered address and the (lower) bits to the one at an odd-numbered address A0 is not available since two addresses must be specified for reading/writing 16-bit data simultaneously and addresses of A0 = and A0 = are read/written at a time http://resource.renesas.com Page 192 Connect them so that the contents at the even-numbered address are treated as upper and those at the odd-numbered address as lower Enter an appropriate word in parentheses The CS0 to CS7 signals of the H8/3048 are obtained by decoding the upper (3) bits of addresses By decoding the upper bits of addresses, the entire memory space can be divided into equal parts Signals correspond to addresses as follows: CS0: Addresses whose upper bits are 000 (H'000000 to H'1FFFFF) CS1: Addresses whose upper bits are 001 (H'200000 to H'3FFFFF) CS7: Addresses whose upper bits are 111 (H'E00000 to H'FFFFFF) http://resource.renesas.com Page 193 ... externally connected memory 13.2 Pins for Memory Connection Table 13.2 shows the pins relating to memory connection provided for the H8/3048 and their functions Connected memory size Since there... HWR and LWR signals are output For details, refer to the section describing connection between the CPU and memory [Explanation with motion pictures and sound] 13.3 Read Timing from External Memory. .. are input to the memory OE pin When the CPU is in read mode, the RD signal and OE are set at low and reading starts This completes logical connection between the CPU and the memory Next, it must