This paper proposes a new approach to parallel implementation of BCH and LDPC encoders with adjustable encoding parameters, supporting all the different BCH + LDPC code configurations. The proposed solution is fully backward compatible to legacy decoder on the receiving side.
2016 International Conference on Engineering and Telecommunication Development of the parallel BCH and LDPC encoders architecture for the second generation digital video broadcasting standards with adjustable encoding parameters on FPGA Tran Van Nghia Ph.D student of Computer science Moscow Institute of Physics and Technology, State University Moscow, Russia nghiamosmipt@gmail.com are reported in section IV Finally, section V concludes the paper Abstract - In the second generation digital video broadcast standards, such as DVB-T2, DVB-S2, DVB-C2, etc., is applied a powerful channel coding scheme to transmit data on the nonideal communication channels with limited bandwidth due to the serial concatenation of BCH (Bose-Chaudhuri-Hocquenghen) and Low-Density-Parity-Check (LDPC) codes The high-speed requirements, long data block lengths and multi-parametric encoding present complex challenges in the efficient implementation of a hardware architecture This paper proposes a new approach to parallel implementation of BCH and LDPC encoders with adjustable encoding parameters, supporting all the different BCH + LDPC code configurations The proposed solution is fully backward compatible to legacy decoder on the receiving side II A The traditional BCH encoder The encoding of BCH codes [1, 2, 3, 4] can be simply expressed by: m( x).x n r ( x) = q( x) + g ( x) g ( x) Keywords: Forward Error Correction code; BCH encoder; LDPC encoder; Galois field; DVB; FPGA; DVB-T2 modulator (1) where, m( x) = mKbch −1 x Kbch −1 + mKbch − x Kbch − + + m1 x + m0 is a degree KBCH-1 polynomial of k-bit message M = (mKbchí1,mKbchí2, ,m1,m0); g ( x) = x n + g n −1 x n −1 + + g x + g1 x + is the degree n generator polynomial of the BCH code in Galois fields; r(x) is the remainder polynomial of dividing m(x).xn by g(x); q(x) is the quotient polynomial of dividing m(x).xn by g(x) I INTRODUCTION Forward Error Correction systems play a crucial role in the digital transmission systems and storage devices In particular, the second generation digital video broadcast standards use a combination of outer coding BCH and inner coding LDPC [1, 2, 3, 4], which allows to operate near the Shannon limit The DVB standards support two different frame lengths (64800 bits for normal frame and 16200 bits for short frame) and 11 different code rates (1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10) for both frame lengths Each mode of operation defines a different BCH and LDPC code and different correcting capability, since the BCH encoder uses different generator polynomials and LDPC encoder uses different parity check matrices Therefore, this poses an enormous challenge on the development of BCH and LDPC encoders, which is fully compliant with all operating modes So, this work proposes a development of reconfigurable parallel BCH and LDPC encoder to satisfy the various requirements for correcting capability and to eliminate the bottleneck The output code-word polynomial is given as follows: c( x) = m( x).x n + r ( x) This paper is organized as follow: Section II describes the traditional BCH encoder A recursive formula is derived based on serial LFSR architecture for implementation of the parallel BCH encoder with adjusting correcting capability Section III makes a short description of the LDPC encoder The parallel LDPC encoder architecture is proposed based on the periodicity of the LDPC-IRA codes The experimental results 978-1-5090-4553-2/16 $31.00 © 2016 IEEE DOI 10.1109/EnT.2016.29 NEW PARALLEL BCH ENCODER ARCHITECTURE Fig Schematic of the traditional BCH encoder 103 104 (2) BCH codes are a class of cyclic error-correcting codes Therefore, the hardware implementation of BCH encoders is usually performed by a n-stage serial linear feedback shift register (LFSR) architecture, as plotted in Fig 1, in which the feedback terms are determined by the generator polynomial g(x) All add operations perform addition modulo-2 (XOR) The multiply operations are simplified to a connection or a disconnection when gi (0 i n-1) equals to '1' or '0', respectively Therefore, they are replaced by AND gates ª g n -1 º « » g n -2 » ª I n -1 º « and F = «G » = « » , where, the first column ẳ ô ằ ô g1 0 » « g 0 » ¬ ¼ G = [ g n -1 g n -2 g1 g0 ] of matrix F contains the coefficients of the generator polynomial g(x); In-1 is a (n-1)-identity matrix T During the first kbch clock cycles, kbch bits of message are entered in the LFSR for calculating the remainder r(x) Meanwhile, the message bits are also sent to the output to form the systematic part of the code word After kbch clock cycles, LFSR contains the bits of remainder They are then shifted out of the registers to form the remaining systematic part of the code word Expression (4) can be written as: R(T + 1) = F × [ R(T ) + M (T + 1)] = F × R(T ) + m(T + 1) × G (5) According to expression (4) or (5), a recursive formula for the state of remainder register at time T+w can be derived as: B BCH encoder with adjustable correction capability LFSR architecture is simple and can run at very high frequency, but it suffers from the serial-in and serial-out limitation If the BCH encoder can process w bits simultaneously, then its process speed is w times as high as a conventional encoder In order to realize a higher data rate, parallel BCH encoder should be employed To implement a parallel BCH encoder algorithm we consider dependence of the state of the remainder register at time T+w on the state of the remainder register at time T and on the w bits of input information From Fig 1, the states of the remainder registers at time T and T+1 and (T+1)-th bit input information m(T+1) are related as: rn -1 (T + 1) = rn -2 (T ) + g n -1 [ rn -1 (T ) + m(T + 1) ] ° °rn -2 (T + 1) = rn -3 (T ) + g n -2 [ rn -1 (T ) + m(T + 1) ] ° ® °r (T + 1) = r (T ) + g r (T ) + m(T + 1) ] [ n -1 °1 °r0 (T + 1) = rn -1 (T ) + m(T + 1) ¯ R(T + w) = F w × [ R(T ) + M (T + w)] (6) where, M (T + w) = [ m(T + 1) m(T + 2) m(T + w) | 0] is a vector of input data group; and T ª The first (n - w + 1) F w = ô F w-1 ì G F w-2 × G F × G » (7) columns of matrix F ẳ For any (nìn) matrix A when multiplied by the matrix F is obtained: ª The first (n -1) Aì F = ô Aì G ằ columns of A ẳ (3) (8) To prove the expressions (6) and (7) we consider for w = From the expressions (5) and (8) we get: The above equations can be rewritten as following matrix: R (T + 2) = F × R (T + 1) + m (T + 2)G = F [ R (T ) + M (T + 1) ] + m (T + 2)G ª rn −1 (T + 1) º ªg n-1 0 º ª rn -1 (T ) + m(T + 1) º « » « » » « « rn − (T + 1) » «g n-2 0 » « rn -2 (T ) + » « » = ô ằ ằ ì ô ằ ô » « » « » « r1 (T + 1) » «g1 0 » « r1 (T ) + » « r (T + 1) » «g 0 0» « r (T ) + ẳ ơ0 ẳ ơ0 ẳ ê The first (n -1) º F = F × F = ôF ì G ằ columns of F ẳ (4) We have: To simplify the expression (4), we denote: ªThe first column ( n - 2) columns º m(T + 2)G = ô G ằì with any values ẳ ¬ with any values R (T + 1) = [ rn −1 (T + 1) rn − (T + 1) r1 (T + 1) r0 (T + 1) ] ° T ° ® R (T ) = [ rn −1 (T ) rn − (T ) r1 (T ) r0 (T ) ] ° T M (T + 1) = êơ m(T + 1) 0 ẳ T ì [ m(T + 2) 0 0] = F M (2) (T + 2) T 105 104 (9) (10) where, M (2) (T + 2) = [ m(T + 2) 0] is a n-dimensional vector, the second element of which equals to the data bit m(T+2), and the others are zeros where, M ( k +1) (T + k + 1) = [ 0 m(T + k + 1) 0] T T is a n- dimensional vector, the (k+1)-th element of which equals to the data bit m(T+k+1), and the others are zeros Expression (9) can be rewritten as: R(T + k + 1) = F × R(T + k ) + m(T + k + 1)G R (T + 2) = F × ª¬ R (T ) + M (T + 1) + M (2) (T + 2) º¼ = F [ R (T ) + M (T + 2) ] = F k +1 [ R(T ) + M (T + k )] + m(T + k + 1)G (11) Put the (12) and (13) into the expression (*): From the expressions (10) and (11) we see that the expressions (6) and (7) are true for w = Assume that the expressions (6) and (7) are also true for w = k We will look for w = k + We have: R (T + k + 1) = F k +1 êơ R (T ) + M (T + k ) + M ( k +1) (T + k + 1) º¼ = F k +1 [ R (T ) + M (T + k + 1) ] In the DVB standards, BCH codes are performed in the Galois field GF(216) (for normal frames) and GF(214) (for short frames) and have the correcting capability t = {8, 10, 12} errors To change the correcting capability we must update the generator polynomial (i.e change the matrix Fw), which leads to change the hardware architecture To implement the BCH encoder with variable correcting capacity, the proposed solution includes: The first (n -1) ê F k +1 = ô F k ì G ằ columns of F k ằẳ ôơ (12) The first (n - k ) º ª k k -1 = ô F ì G F ì G F ì G ằ columns of F ẳ k +1 comprises the ª k columns with (n - k -1) columns º m(T + k + 1)G = ô G ằì with any values ẳ any values × [ 0 m(T+k+1) 0] T (14) Expressions (12) and (14) show that the expressions (6) and (7) also hold true for w = k + By the mathematical induction, the expressions (6) and (7) applied to w n ª The first (n - k + 1) F k = ô F k ì G F k -2 × G F × G ằ columns of matrix F ẳ From (12) we see that the matrix F vector G in the (k+1)-th column Therefore: (*) (13) = F k +1 M ( k +1) (T + k + 1) • The dimension of the matrix F, the length of the remainder register and also the dimension of vector G need to design in the worst case (equal to the maximum degree nmax of the generator polynomial) • For the less degree generator polynomial g(x) (n < nmax), the vector G is inserted (nmax - n) zeros to the right, i.e is got a new generator polynomial g new ( x) = g ( x).x( nmax − n ) From Fig show that n bits of remainder are not changed Thus, the resulted matrix Fw from gnew(x) can use for calculating the remainder Fig Schematic of the BCH encoder with adjustable correction capability 106 105 III PARALLEL LDPC-ENCODER ARCHITECTURE WITH ADJUSTABLE CODE RATE storage requirements, and Hp is a staircase lower triangular matrix corresponding to parity bits P = [p0, p1, …, pm-1] Recently, LDPC-codes are widely used in modern digital communication systems and video broadcast standards because of its excellent efficiency LDPC encode design poses the biggest challenge, due to their huge dimension It has been a sufficiently large number of different algorithms for constructing the check matrices H DVB standard [1-5] has adopted a special class of LDPC codes, known by Irregular Repeat-Accumulate (LDPC-IRA) by a compacted memory mapping of the parity check matrices LDPC-IRA codes usually represented by Tanner graphs, which can be partitioned into two submatrices H = [HuHp] ª h11 h12 h1k º « » 1 h h h 21 22 2k ằ H = êơ H u H p ẳ = « « H u H p » ô ằ 1ẳằ ơô hm1 hm hmk The matrix A design technique is based on dividing the information nodes in disjoint groups of M = 360 consecutives bits Thus it is only necessary to the check nodes (with indices c1,c2, ,cwl) that connect to the first information node of the group in order to specify the check nodes that connect to each one of the remaining M-1 information bits of that group This allows a significant reduction on the storage requirement without code performance loss And the indices of the check nodes that connect to the i-th information bit of that group can be obtained by: [ c1 + (i -1)q ] mod (n - k ) ° °[ c2 + (i -1)q ] mod (n - k ) ® ° °[ c + (i -1)q ] mod (n - k ) ¯ wl (15) (16) where, k is the number of input information bits; n is the codeword length; q =(ník)/Q where, Hu is a sparse matrix associating to information bits I = [i0, i1, …, ik1], which allows a significant reduction of the Fig Architecture for the DVB LDPC-IRA encoder However, the number of information groups (q) is different based on the code rate and frame length To develop an efficient parallel encoder algorithm shared by all code options (length and rate) we proposed the architecture shown in Fig 3, where we only need to design the SRAM for maximum value q (i.e., qmax = 135) used in DVB standards ª pk º ª pk º ª pk −1 º « » « » « » « pk +1 » = « pk +1 » ⊕ « pk » « » « » « » « » « » « ằ ơô pk + ẳằ ơô pk + ẳằ ơô pk + ẳằ Indices c1,c2, ,cwl for all code options are stored in the ROMs Based on the code rate, we select the corresponding ROM (Q×qmax) bits SRAM stores the check bits in the calculation The proposed LDPC-encoder operates in two periods In the first period, based on the indices c1,c2, ,cwl, LDPC-encoder computes addresses of the parity check bits stored in the SRAM according to information bits, performs addition operator in the GF(2) of these parity check bits and information bits Results of the GF(2) sum are overwritten into the SRAM The second period is performed after q information groups entering the LDPC-encoder In this period, eight check bits read from SRAM by columns of the first q rows and fed into the “Total GF(2) sum” to calculate the parity bits by using the following procedure: (17) The resulted parity bits (pk, pk+1, …, pk+7) from (17) are sent to the output to form the parity bits part of the code word and bit pk+7 is also left for the next computation IV EXPERIMENTAL RESULTS The proposed hardware architecture for the BCH and LDPC encoders was tested in the DVB-T2 modulator [6], which synthesized on the Digilent NetFPGA-1G-CML Development Board using the Xilinx Kintex-7 XC7K325T chip and on the AD9789 Evaluation Board, as seen on Fig The binary coefficients in hexadecimal digits represented the generator polynomials are shown in Table LDPC and BCH 107 106 coding schemes [7], used in the DVB standards and also in the others Encoders are parallelized for data bus width of bits So we use the matrix F8 for computing the BCH codes The sequences of the first eight elements of the rows of the matrix F8 are shown in Table TABLE I TABLE II THE COEFFICIENTS OF THE GENERATOR POLYNOMIALS USED IN THE DVB STANDARDS The coefficients of the generator polynomials Degree 1C07255F712797BD19FC6D7504F9662B 128 60150CEDFC2A331F6A785703EFD12301B8BB6591 160 4E260E83845C511C50CF2CD8DC350889034785F7660255E7 192 4062DBEA9869B262CD23A39069528FE7D7D11905A5 168 For modeling the non-ideal communication channel, the additive white Gaussian noise is generated in the FPGA chip RF signals without the additive white noise and with the noise on the output of the DVB-T2 modulator are observed on the television analyzer PROMAX TV EXPLORER HD+ as in Fig 5a and Fig 5b, respectively In the case there is no the noise, CBER (Bit error rate for the digital signal before error correction) and LBER (Bit error rate for the digital signal after error correction) are less than 1xE-6 and 1xE-8, respectively, and MER (Modulation error ratio with noise margin indication) is more than 35dB These values are the limit values of the analyzer TV EXPLORER In the presence of noise, BER (probability of error) increases (approximately E-3 ÷ E-6) and MER decreases, but LBER is also less than 1xE-8 This means that the bit errors due to the noise are completely corrected The experimental results on the FPGA chip have shown the correctness of proposed solution for BCH and LDPC encoders and their effectiveness Obviously, these encoders are backward compatible to legacy decoders on the receiving side and can change the traditional The first eight elements of the rows in the matrix F8 Degree B85CAE57937180C0E070B8DCEE7703B964B25994CA658 A459A4D1E0F3F272B2D2E17B3E1C8E472392412897C3E9 FF74319341A8D7E3FA76B8DFEFF479B758241188CC6630 9BC5EAFEFCF5F97F3C1582C964B9DF6FBC5DA6D0E073 BA56AB562312090482412093C9E4F9FF74399F4FAFD46A 3E9CC66332128140A857A3D269371 128 4EA79D0080402090C8E47239D269FA7D70B85C2E97858C 46235F61FEFFB1160B4BEB3B53E7BD90C8E472395229D AEDB85CAED7A51C8EC72D58AC562BDB23DF21DEEFB 912898A45EC763B53E7BD90C864B2D9A2D1A6D3A71DC 060B058AC562B5B63FFB196CBAB9B03CFA99ACDA8D4 EAF5B4DAED389C4EA79D80C0E0F0F8FC7E3FD1269387 8D8844221146235FE13E1F416EB795048241EE77F5349A4 DE8743A9D 160 DAED2C964B7F6568349A4D7CBE5F7560B0D86CB65B77 61EA7560B0582C168B9F155028944A25C8643299964BFF A508844221CAE528140A05582C964BFFA50884C2E1AA5 5F078BCDEEFAD8CC6E32B4FFD2412095EAF8D9C4E274 97E3FC5381C0E8799168B1F5570B85CAED731C2E12A155 02894CAE52894CA65E8743A1DD46A35C0E070B8DCEEF 7A10A85188C46A38B9F9590C8E4F2796633C3BB0759F6F BA7095E2F4D7CBEDFB58040A0D0E8F47A3DC4E2F1A2 517239C6636B6FED2C160BDFB5 192 AA5580C0E0F0F87CBEDFC5482492498EC7C9CE6719261 323BB7711A2D1C2E15AADFC7E3FB570B85C2E97E1DA 6D1C0E87E95E2F3DB45AAD7CBEDFC548A4D2691E8FE D5C2E17A1FA7D94CAE5D8ECF6FBD7C1CAE5582C160B AFFD542A95E070B85C2E1721BADD44A2D14221BA5D04 82C1CA6598CC66B3F3D3C3CBCFCD4C2613233B373132 192613A3FBD7410A0528944AA578BC5EAFFD542A15209 0482412092E1721BA5D040201AA55 168 Fig Experimental DVB-T2 modulator 108 107 THE FIRST EIGHT ELEMENTS OF THE ROWS IN THE MATRIX F8 (ɚ) (b) Fig Measuring results on the analyzer TV EXPLORER HD+ V [2] CONCLUSIONS This paper proposed a new solution for designing the reconfigurable parallel BCH and LDPC encoders, based on the traditional scheme Their reconfigurability (parameterization) is universal, and should be given the opportunity to optimize the hardware implementation These encoders and the other modules of DVB-T2 modulator are integrated into a single XC7K325T FPGA Parallel implementation of these encoders leads to achieve high speed and high throughput On the other hand, the same approach of parallelization can be used in decoding on the receiver [3] [4] [5] [6] REFERENCES [1] [7] ETSI EN 302 307 V1.2.1, “Digital video broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broadband satellite applications,” Aug 2009, 78p 109 108 ETSI EN 302 755 V1.4.1, “Digital video broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system,” July 2015, 188p ETSI EN 302 769 V1.3.1, “Digital video broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital transmission system for cable systems,” Oct 2015, 112p V P Dvorkovich, A V Dvorkovich, “Digital video-information systems (theory and practice),” Moscow: Technosphera, 2012, 1008p Marco Gomes, Gabriel Falcao, Alexandre Sengo, Vitor Ferreira, Vitor Silva, Miguel Falcao, “High Throughput Encoder Architecture for DVBS2 LDPC-IRA Codes,” IEEE International Conference on Microelectronics, 29-31 Dec 2007, pp 271–274 Tran Van Nghia, Le Van Ky, Nguyen Huy Hoang, “Implementation of FPGA-based DVB-T2 transmitter for a second generation digital terrestrial television broadcasting system,” The 17-th International Conference on Digital Signal Processing And Its Applications, Moscow, Russia, 25-27 March 2015 Tran Van Nghia, Le Van Ky, Tran Minh Hai, Le Thi Trang Linh, “Efficient implementation of FPGA-based forward error correcting combination and bit to cell word de-multiplexer for a second generation digital terrestrial television broadcasting system,” The 17-th International Conference on Digital Signal Processing And Its Applications, Moscow, Russia, 25-27 March 2015 ... the GF(2) of these parity check bits and information bits Results of the GF(2) sum are overwritten into the SRAM The second period is performed after q information groups entering the LDPC- encoder... output to form the parity bits part of the code word and bit pk+7 is also left for the next computation IV EXPERIMENTAL RESULTS The proposed hardware architecture for the BCH and LDPC encoders. .. means that the bit errors due to the noise are completely corrected The experimental results on the FPGA chip have shown the correctness of proposed solution for BCH and LDPC encoders and their effectiveness