Lecture VLSI Digital signal processing systems - Chapter 17: Low-power design includes content as: VLSI digital signal processing systems, power consumption in DSP, power dissipation, CMOS power consumption, dynamic power consumption, switching activity (α), increased switching activity due to glitching,…
Chapter 17: Low-Power Design Keshab K Parhi and Viktor Owall Speed Complexity IC Design Space Chapter 17 Power Sp ee Area d New Design Space VLSI Digital Signal Processing Systems • Technology trends: – 200-300M chips by 2010 (0.07 micron CMOS) • Challenges: – – – – – – – Chapter 17 Low-power DSP algorithms and architectures Low-power dedicated / programmable systems Multimedia & wireless system-driven architectures Convergence of Voice, Video and Data LAN, MAN, WAN, PAN Telephone Lines, Cables, Fiber, Wireless Standards and Interoperability Power Consumption in DSP • Low performance portable applications: – Cellular phones, personal digital assistants – Reasonable battery lifetime, low weight • High performance portable systems: – Laptops, notebook computers • Non-portable systems: – Workstations, communication systems – DEC alpha: GHz, 120 Watts – Packaging costs, system reliability Chapter 17 Power Dissipation Two measures are important • Peak power (Sets dimensions) Ppeak = VDD ì iDDmax Average power (Battery and cooling) T VDD iDD (t) dt Pav = T Chapter 17 CMOS Power Consumption Ptot = Pdyn + Psc + Pleakage = = α f CL V DD + VDD I sc + I leakage VDD α = probability for switching Chapter 17 Dynamic Power Consumption VDD Charge Energy charged in a capacitor EC = CV2/2 = CLVDD2/2 Energy Ec is also discharged, i.e Etot= CL VDD2 Discharge Power consumption Chapter 17 P = CL VDD2 f Off-Chip Connections have High Capacitive Load Reduced off Chip Data Transfers by System Integration Ideally a Single Chip Solution Chapter 17 Reduced Power Consumption Switching Activity (α): Example Pa=0.5 Pb=0.5 Pc=0.5 Pd=0.5 Pa=0.5 Px=0.25 Due to correlation Chapter 17 = 0.4375 16 Pz = = 0.375 Py=0.25 Px=0.25 Pb=Pc=0.5 Pd=0.5 Pz = Py=0.25 Increased Switching Activity due to Glitching a b=0 a c x c z Delay in gate Extra transition due to race x Dissipates energy z Chapter 17 10 • • • Dual Supply Voltages for Low Power Systematic capture and elimination of slack using fictitious entities called Unit Delay Fictitious Buffers Switch unnecessarily fast gates to to lower supply voltage VDDL thereby saving power, critical path gates have a high supply voltage of VDDH Use a simple relation between a gate’s speed/power and supply voltage with the UDF’s in its fanout nets Model the problem as an approximately solvable ILP Critical Path = 8, UDF’s in Boxes 33 33 Chapter 17 VDDH Critical Path = 8, UDF’s in Boxes VDDH VDDH 03 03 -3 VDDH LC = Level Converter -3 VDDL VDDH UDF Displacement 20 Variables Dual Threshold CMOS VLSI for Low Power • • • Systematic capture and elimination of slack using fictitious entities called Unit Delay Fictitious Buffers Gates on the critical path have a low threshold voltage VTL and unnecessarily fast gates are switched to a high threshold voltage VTH Use a simple relation between a gate’s speed /power and threshold voltage with the UDF’s in its fanout nets Model the problem as an efficiently approximable 0-1 ILP Critical Path = 8, UDF’s in Boxes 33 33 Chapter 17 VTL VTL VTL 03 03 -3 VTL 3 VTL -3 VTH Critical Path = 8, UDF’s in Boxes UDF Displacement 21 Variables Experimental Results • Table :ISCAS’85 Benchmark Ckts Resizing (20 Sizes) Dual VDD Dual Vt (5v, 2.4v) Ckt C1908 c2670 c3540 c5315 c6288 c7552 #Gates Power Savings 880 1211 1705 2351 2416 3624 15.27% 28.91% 37.11% 41.91% 5.57% 54.05% CPU(s) Power Savings 87.5 164.38 312.51 660.56 69.58 1256.76 49.5% 57.6% 57.7% 62.4% 62.7% 59.6% CPU(s) Power Savings 739.05 1229.37 1743.75 4243.63 7736.05 9475.1 84.92% 90.25% 83.36% 91.56% 61.75% 90.90% V Sundararajan and K.K Parhi, "Low Power Synthesis of Dual Threshold Voltage CMOS VLSI Circuits” Proc of 1999 IEEE Int Symp on Low-Power Electronics and Design, pp 139-144, San Diego, Aug 1999 Chapter 17 22 HEAT: Hierarchical Energy Analysis Tool • Salient features: – – – – Based on stochastic techniques Transistor-level analysis Effectively models glitching activity Reasonably fast due to its hierarchical nature Chapter 17 23 Theoretical Background • Signal probability: – S=T clk / Tgd ,where Tclk :clock period T gd : smallest gate delay NS p1xi = lim j =1 N →∞ xi ( j ) NS p x0i = − p1xi • Transition probability: NS p1x→ = lim i j =1 xi ( j )xi ( j + 1) N →∞ NS p1x→ + p1x→ + p x0i→1 + p x0i→0 = i i • Conditional probability: Chapter 17 p1xi/ = p x0i→1 p x0i→1 + p x0i→0 24 State Transition Diagram Modeling Node2 ( n + 1) = (1 − x1 ( n)) + x1 ( n) ⋅ x2 ( n) ⋅ node2 ( n) node2 (n + 1) = (1 − x1 (n)) + x1 (n) ⋅ x2 (n) ⋅ node2 (n) node3 (n + 1) = (1 − x1 (n)) + (1 − x2 (n)) Chapter 17 25 The HEAT algorithm • • • • Partitioning of systems unit into smaller sub-units State transition diagram modeling Edge energy computation (HSPICE) Computation of steady-state probabilities (MATLAB) • Edge activity computation • Computation of average energy Energy = W j ⋅ EAj Chapter 17 j 26 Performance Comparison Power Run-time 9000 8000 7000 6000 5000 uW 4000 SPICE 3000 HEAT 2000 1000 45000 40000 35000 30000 25000 sec 20000 15000 10000 5000 BW4 HY4 BW8 HY8 BW4 HY4 BW8 HY8 circuit circuit J Satyanarayana and K.K Parhi, "Power Estimation of Digital Datapaths using HEAT Tool", IEEE Design and Test Magazine, 17(2), pp 101-110, April-June 2000 Chapter 17 27 Finite field arithmetic Addition and Multiplication A = am −1α m −1 + +a1α + a0 B = bm −1α m −1 + +b1α + b0 A + B = (am −1 + bm −1 )α m−1 + +(a1 + b1)α + (a0 + b0 ) A ⋅ B = (am −1α m −1 + +a1α + a0 )(bm −1α m −1+ +b1α + b0 )mod(p(x)) Polynomial addition over GF(2) one’s complement operation > XOR gates Chapter 17 Polynomial multiplication and modulo operation (modulo primitive polynomial p(x) ) 28 Programmable finite field multiplier Array-type Parallel Digit-serial MAC2 + DEGRED2 Four Instr Chapter 17 MAC2 MAC2 DEGRED2 DEGRED2 29 Finite field arithmetic-programmable finite field multipliers Programmability:-primitive polynomial p(x) -field order m How to achieve programmability:-control circuitry -zero, pre & post padding Polynomial multiplication Polynomial modulo operation Array-type multiplication Fully parallel multiplication Digit-serial/parallel multiplication L Song and K K Parhi, “Low-energy digit-serial/parallel finite field multipliers”, Journal of VLSI Signal Processing, 19(2), pp 149-166, June 1998 Chapter 17 30 Data-path architectures for low energy RS codecs • Advantages of having two separate sub-arrays – Example: Vector-vector multiplication over GF(2m) [A0 A1 é B0 ù ê B An −1 ]ê = ( A0 B0 + + An −1 Bn −1 ) mod ( p ( x ) ) ê ê ë Bn −1 – Assume energy(parallel multiplier)=Eng Energy(MAC8x8)=0.25 Eng Energy(DEGRED7)=0.75 Eng s= Chapter 17 Total Energy(parallel)=Eng*n Total Energy(MAC-D7)=0.25Eng*n+0.75Eng Eng ⋅ (n − (0.25n + 0.75)) ≅ 75% Eng ⋅n 31 Data-path architectures for lowpower RS encoder • Data-paths – One parallel finite field multiplier – Digit-serial multiplication: MACx and DEGREDy Chapter 17 32 Data-path architectures for low energy RS codecs • Data-path: – one parallel finite field multiplier – Digit-serial multiplication: MACx and DEGREDy Energy MAC8 + DEGRED2 MAC8 + DEGRED1 MAC4 + DEGRED2 MAC4 + DEGRED1 Energy-delay MAC8 + DEGRED4 MAC8 + DEGRED2 L Song, K.K Parhi, I Kuroda, T Nishitani, "Hardware/Software Codesign of Finite Field Datapath for Low-Energy Reed-Solomon Codecs", IEEE Trans on VLSI Systems, 8(2), pp 160-172, Apr 2000 Chapter 17 33 Low power design challenges • System Integration • Application Specific architectures for Wireless/ADSL/Security • Programmable DSPs to handle new application requirements • Low-Power Architectures driven by Interconnect, Crosstalk in DSM technology • How Far are we away from PDAs/Cell Phones for wireless video, internet access Chapter 17 34 and e-commerce? ... multiplication L Song and K K Parhi, “Low-energy digit-serial/parallel finite field multipliers”, Journal of VLSI Signal Processing, 19(2), pp 14 9-1 66, June 1998 Chapter 17 30 Data-path architectures for... Space Chapter 17 Power Sp ee Area d New Design Space VLSI Digital Signal Processing Systems • Technology trends: – 20 0-3 00M chips by 2010 (0.07 micron CMOS) • Challenges: – – – – – – – Chapter 17. .. circuit J Satyanarayana and K.K Parhi, "Power Estimation of Digital Datapaths using HEAT Tool", IEEE Design and Test Magazine, 17( 2), pp 10 1-1 10, April-June 2000 Chapter 17 27 Finite field arithmetic