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Computer Architecture Structured Computer Organization by A Tanenbaum, Prentice Hall, 2005 B W Wah ECE 290 Fall 2006 Introductions CuuDuongThanCong.com https://fb.com/tailieudientucntt Languages, Levels, Virtual Machines A multilevel machine Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Contemporary Multilevel Machines A six-level computer The support method for each level is indicated below it Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt Computer Generations • Zero’th Generation Mechanical Computers (1642 – 1945) • First Generation Vacuum Tubes (1945 – 1955) • Second Generation Transistors (1955 – 1965) • Third Generation Integrated Circuits (1965 – 1980) • Fourth Generation Very Large Scale Integration (1980 – ?) Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Von Neumann Machine The original Von Neumann machine Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt PDP-8 Innovation – Single Bus The PDP-8 omnibus Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Technological and Economic Forces Moore’s law predicts a 60-percent annual increase in the number of transistors that can be put on a chip The data points given in this figure are memory sizes, in bits Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt Personal Computer Pentium socket 875P Support chip Memory sockets AGP connector Disk interface Gigabit Ethernet Five PCI slots USB 2.0 ports Cooling technology 10 BIOS A printed circuit board is at the heart of every personal computer This figure is a photograph of the Intel D875PBZ board The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Example Computer Families • • • Pentium by Intel UltraSPARC III by Sun Microsystems The 8051 chip by Intel, used for embedded systems 10 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt Intel Computer Family (1) The Intel CPU family Clock speeds are measured in MHz (megahertz) where MHZ is million cycles/sec 11 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Intel Computer Family (2) The Pentium chip The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission 12 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt Intel Computer Family (3) Moore’s law for (Intel) CPU chips 13 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Computer Systems Organization CuuDuongThanCong.com https://fb.com/tailieudientucntt Central Processing Unit The organization of a simple computer with one CPU and two I/O devices 15 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CPU Organization The data path of a typical Von Neumann machine 16 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction Execution Steps Fetch next instruction from memory into instr register Change program counter to point to next instruction Determine type of instruction just fetched If instructions uses word in memory, determine where Fetch word, if needed, into CPU register Execute the instruction Go to step to begin executing following instruction 17 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 RISC versus CISC • 1980: RISC has simple instructions that can be executed in one cycle of a simple data path • Execute frequently used instructions efficiently and less frequently used instructions less efficiently • Wins over CISC that takes multiple and longer cycles to execute a complex instruction • May take 4-5 instructions to accomplish a complex operation • CISC is still predominant in today’s market • Backward compatibility to early CISC computers • Starting with 486, Intel CPUs contain a RISC core that executes the simplest (and typically most common) instructions in a single data path cycle, while interpreting the more complicated instructions in the usual CISC way 18 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 CuuDuongThanCong.com https://fb.com/tailieudientucntt Design Principles for Modern Computers • • • • • All instructions directly executed by hardware Maximize rate at which instructions are issued Instructions should be easy to decode Only loads, stores should reference memory Provide plenty of registers 19 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Instruction-Level Parallelism a) b) A five-stage pipeline The state of each stage as a function of time Nine clock cycles are illustrated 20 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt Instruction-Level Parallelism (a) A CPU pipeline (b) A sequence of VLIW instructions 83 (c) An instruction stream with bundles marked Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 The TriMedia VLIW CPU A typical TriMedia instruction, showing five possible operations 84 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 42 CuuDuongThanCong.com https://fb.com/tailieudientucntt On-Chip Multithreading (1) (a) – (c) Three threads The empty boxes indicated that the thread has stalled waiting for memory (d) Fine-grained multithreading (e) Coarse-grained multithreading 85 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 On-Chip Multithreading (2) Multithreading with a dual-issue superscalar CPU (a) Fine-grained multithreading (b) Coarse-grained multithreading (c) Simultaneous multithreading 86 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 43 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hyperthreading on the Pentium Resource sharing between threads in the Pentium NetBurst microarchitecture 87 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Homogeneous Multiprocessors on a Chip Single-chip multiprocessors (a) A dual-pipeline chip (b) A chip with two cores 88 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 44 CuuDuongThanCong.com https://fb.com/tailieudientucntt Heterogeneous Multiprocessors on a Chip (1) The logical structure of a simple DVD player contains a heterogeneous multiprocessor containing multiple cores for different functions 89 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Heterogeneous Multiprocessors on a Chip (2) An example of the IBM CoreConnect architecture 90 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 45 CuuDuongThanCong.com https://fb.com/tailieudientucntt Introduction to Network Processors A typical network processor board and chip 91 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 The Nexperia Media Processor The Nexperia heterogeneous multiprocessor on a chip 92 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 46 CuuDuongThanCong.com https://fb.com/tailieudientucntt Multiprocessors (a) A multiprocessor with 16 CPUs sharing a common memory (b) An image partitioned into 16 sections, each being analyzed by a different CPU 93 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Multicomputers (1) (a) A multicomputer with 16 CPUs, each with its own private memory (b) The bit-map image of Fig 8-17 split up among the 16 memories 94 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 47 CuuDuongThanCong.com https://fb.com/tailieudientucntt Multicomputers (2) Various layers where shared memory can be implemented (a) The hardware (b) The operating system (c) The language runtime system 95 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Taxonomy of Parallel Computers (1) Flynn’s taxonomy of parallel computers 96 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 48 CuuDuongThanCong.com https://fb.com/tailieudientucntt Taxonomy of Parallel Computers (2) A taxonomy of parallel computers 97 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 UMA Symmetric Multiprocessor Architectures Three bus-based multiprocessors (a) Without caching (b) With caching (c) With caching and private memories 98 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 49 CuuDuongThanCong.com https://fb.com/tailieudientucntt UMA Multiprocessors Using Crossbar Switches (a) An × crossbar switch (b) An open crosspoint (c) A closed crosspoint 99 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 UMA Multiprocessors Using Multistage Switching Networks An omega switching network 100 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 50 CuuDuongThanCong.com https://fb.com/tailieudientucntt NUMA Multiprocessors A NUMA machine based on two levels of buses The Cm* was the first multiprocessor to use this design 101 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Cache Coherent NUMA Multiprocessors (a) A 256-node directory-based multiprocessor (b) Division of a 32-bit memory address into fields (c) The directory at node 36 102 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 51 CuuDuongThanCong.com https://fb.com/tailieudientucntt The Sun Fire E25K NUMA Multiprocessor (1) The Sun Microsystems E25K multiprocessor 103 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 BlueGene (1) The BlueGene/L custom processor chip 104 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 52 CuuDuongThanCong.com https://fb.com/tailieudientucntt BlueGene (2) The BlueGene/L (a) Chip (b) Card (c) Board (d) Cabinet (e) System 105 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Red Storm (1) Packaging of the Red Storm components 106 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 53 CuuDuongThanCong.com https://fb.com/tailieudientucntt Red Storm (2) The Red Storm system as viewed from above 107 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 A Comparison of BlueGene/L and Red Storm A comparison of BlueGene/L and Red Storm 108 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 54 CuuDuongThanCong.com https://fb.com/tailieudientucntt Google (1) Processing of a Google query 109 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 Google (2) A typical Google cluster 110 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 55 CuuDuongThanCong.com https://fb.com/tailieudientucntt Grid Computing The grid layers 111 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-148521-0 56 CuuDuongThanCong.com https://fb.com/tailieudientucntt ... Mechanical Computers (1642 – 19 45) • First Generation Vacuum Tubes (19 45 – 1 955 ) • Second Generation Transistors (1 955 – 19 65) • Third Generation Integrated Circuits (19 65 – 1980) • Fourth Generation... 0-13-14 852 1-0 27 CuuDuongThanCong .com https://fb .com/ tailieudientucntt Merging the Interpreter Loop with the Microcode (1) Original microprogram sequence for executing POP 55 Tanenbaum, Structured Computer... Organization, Fifth Edition, (c) 2006 Pearson Education, Inc All rights reserved 0-13-14 852 1-0 The PCI Bus (1) Architecture of an early Pentium system The thicker buses have more bandwidth than the thinner