kiến trúc máy tính dạng thanh tin figs 3 the digital logic level sinhvienzone com

3 THE DIGITAL LOGIC LEVEL CuuDuongThanCong.com https://fb.com/tailieudientucntt +VCC +VCC +VCC Vout V1 Collector Vout Vout Vin V2 V1 V2 Emitter Base (a) (b) (c) Figure 3-1 (a) A transistor inverter (b) A NAND gate (c) A NOR gate CuuDuongThanCong.com https://fb.com/tailieudientucntt NOT A X A NAND X B A X (a) NOR A X B A 0 1 B 1 (b) X 1 AND A X B A 0 1 B 1 (c) X 0 OR A X B A 0 1 B 1 X 0 (d) A 0 1 B 1 X 1 (e) Figure 3-2 The symbols and functional behavior for the five basic gates CuuDuongThanCong.com https://fb.com/tailieudientucntt A B C A B C A A B ABC ABC A 0 0 1 1 B 0 1 0 1 C 1 1 (a) M 0 1 1 B ABC C C ABC (b) Figure 3-3 (a) The truth table for the majority function of three variables (b) A circuit for (a) CuuDuongThanCong.com https://fb.com/tailieudientucntt M A A A A (a) A A AB A+B B B A AB A A+B B B (b) (c) Figure 3-4 Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates CuuDuongThanCong.com https://fb.com/tailieudientucntt AB A B AB + AC A A(B + C) B AC C B+C C A B C AB AC AB + AC A B C A B+C A(B + C) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (a) (b) Figure 3-5 Two equivalent functions (a) AB + AC (b) A(B + C) CuuDuongThanCong.com https://fb.com/tailieudientucntt Name AND form OR form Identity law 1A = A 0+A=A Null law 0A = 1+A=1 Idempotent law AA = A A+A=A Inverse law AA = A+A=1 Commutative law AB = BA A+B=B+A Associative law (AB)C = A(BC) (A + B) + C = A + (B + C) Distributive law A + BC = (A + B)(A + C) A(B + C) = AB + AC Absorption law A(A + B) = A A + AB = A De Morgan's law AB = A + B A + B = AB Figure 3-6 Some identities of Boolean algebra CuuDuongThanCong.com https://fb.com/tailieudientucntt AB = A+B A+B (a) AB = (c) = AB (b) A+B A+B = AB (d) Figure 3-7 Alternative symbols for some gates: (a) NAND (b) NOR (c) AND (d) OR CuuDuongThanCong.com https://fb.com/tailieudientucntt A A B XOR 0 0 1 1 A 1 B B (a) (b) A A B B A A B B (c) (d) Figure 3-8 (a) The truth table for the XOR function (b)-(d) Three circuits for computing it CuuDuongThanCong.com https://fb.com/tailieudientucntt A B F A B F A B F 0V 0V 0V 0 1 0V 5V 0V 1 5V 0V 0V 0 1 5V 5V 5V 1 0 (a) (b) (c) Figure 3-9 (a) Electrical characteristics of a device (b) Positive logic (c) Negative logic CuuDuongThanCong.com https://fb.com/tailieudientucntt 14.0 cm Pentium II SEC cartridge 512 KB unified L2 cache Pentium II processor 6.3 cm 16 KB level instruction cache To local bus 16 KB level data cache Contact 1.6 cm Figure 3-43 The Pentium II SEC package CuuDuongThanCong.com https://fb.com/tailieudientucntt Bus arbitration Request BPRI# LOCK# Misc# A# ADS# REQ# Parity# Error Misc# Snoop Misc# Response RS# TRDY# Parity# Data D# DRDY# DBSY# Parity# RESET# Interrupts 33 5 VID Compatibity 11 Pentium II CPU Diagnostics 3 Initialization Power management 64 Miscellaneous 27 35 Φ Power Figure 3-44 Logical pinout of the Pentium II Names in upper case are the official Intel names for individual signals Names in mixed case are groups of related signals or signal descriptions CuuDuongThanCong.com https://fb.com/tailieudientucntt Bus cycle T1 T2 T3 T4 T5 T6 T7 T8 T9 Req Error Snoop Resp Data Req Error Snoop Resp Data Req Error Snoop Resp Req Error Snoop Resp Req Error Snoop Req Error Snoop Req Error T10 T11 T12 Φ Transaction Data Data Resp Data Resp Snoop Data Resp Data Figure 3-45 Pipelining requests on the Pentium II’s memory bus CuuDuongThanCong.com https://fb.com/tailieudientucntt Pin Index Figure 3-46 The UltraSPARC II CPU chip CuuDuongThanCong.com https://fb.com/tailieudientucntt 18 Tag address Tag valid Level cache tags Bus arbitration Memory address 35 Address parity 25 Tag data Tag parity Address valid UltraSPARC II CPU Wait 20 Data address Level cache data Reply Data address valid UPA interface to main memory Level caches 128 Data 16 Parity Control UDB II memory buffer Memory data 128 Memory ECC 16 Figure 3-47 The main features of the core of an UltraSPARC II system CuuDuongThanCong.com https://fb.com/tailieudientucntt Programmable I/O lines 16 MicroJava 701 CPU Level caches PCI bus Flash PROM I Main memory D Memory bus Figure 3-48 A microJava 701 system CuuDuongThanCong.com https://fb.com/tailieudientucntt Motherboard PC bus connector PC bus Plug-in Contact board Chips CPU and other chips New connector for PC/AT Edge connector Figure 3-49 The PC/AT bus has two components, the original PC part and the new part CuuDuongThanCong.com https://fb.com/tailieudientucntt Local bus Cache bus Level cache Memory bus PCI bridge CPU Main memory PCI bus SCSI USB ISA bridge Graphics adaptor IDE disk Available PCI slot Monitor Mouse Modem Keyboard ISA bus Sound card Printer Available ISA slot Figure 3-50 Architecture of a typical Pentium II system The thicker buses have more bandwidth than the thinner ones CuuDuongThanCong.com https://fb.com/tailieudientucntt PCI device PCI device PCI device PCI device Figure 3-51 The PCI bus uses a centralized bus arbiter CuuDuongThanCong.com GNT# REQ# GNT# REQ# GNT# REQ# GNT# REQ# PCI arbiter https://fb.com/tailieudientucntt Signal CLK AD PAR C/BE FRAME# IRDY# IDSEL DEVSEL# TRDY# STOP# PERR# SERR# REQ# GNT# RST# Sign REQ64# ACK64# AD PAR64 C/BE# LOCK SBO# SDONE INTx JTAG M66EN Lines 32 1 1 1 1 1 Lines 1 32 1 Master Slave × × × × × × × × × × Master × Slave × × × × × Description Clock (33 MHz or 66 MHz) Multiplexed address and data lines Address or data parity bit Bus command/bit map for bytes enabled Indicates that AD and C/BE are asserted Read: master will accept; write: data present Select configuration space instead of memory Slave has decoded its address and is listening Read: data present; write: slave will accept Slave wants to stop transaction immediately Data parity error detected by receiver Address parity error or system error detected Bus arbitration: request for bus ownership Bus arbitration: grant of bus ownership Reset the system and all devices (a) Description Request to run a 64-bit transaction Permission is granted for a 64-bit transaction Additional 32 bits of address or data Parity for the extra 32 address/data bits Additional bits for byte enables Lock the bus to allow multiple transactions Hit on a remote cache (for a multiprocessor) Snooping done (for a multiprocessor) Request an interrupt IEEE 1149.1 JTAG test signals Wired to power or ground (66 MHz or 33 MHz) (b) Figure 3-52 (a) Mandatory PCI bus signals (b) Optional PCI bus signals CuuDuongThanCong.com https://fb.com/tailieudientucntt Bus cycle Read T1 Idle T2 T3 T4 White T5 T6 T7 Φ Turnaround AD C/BE# Address Read cmd Data Enable Address Data Write cmd Enable FRAME# IRDY# DEVSEL# TRDY# Figure 3-53 Examples of 32-bit PCI bus transactions The first three cycles are used for a read operation, then an idle cycle, and then three cycles for a write operation CuuDuongThanCong.com https://fb.com/tailieudientucntt Time (msec) Idle Frame Frame Frame Packets from root Packets from root SOF SOF IN DATA ACK Frame SOF SOF OUT DATA ACK From device Data packet from device SYN PID PAYLOAD CRC SYN PID PAYLOAD CRC Figure 3-54 The USB root hub sends out frames every 1.00 msec CuuDuongThanCong.com https://fb.com/tailieudientucntt CS A0-A1 8255A Parallel I/O chip WR RD RESET D0-D7 8 Port A Port B Port C Figure 3-55 An 8255A PIO chip CuuDuongThanCong.com https://fb.com/tailieudientucntt RAM at address 8000H PIO at FFFCH
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 EPROM at address 0 4K 8K 12K 16K 20K 24K 28K 32K 36K 40K 44K 48K 52K 56K 60K 64K Figure 3-56 Location of the EPROM, RAM, and PIO in our 64K address space CuuDuongThanCong.com https://fb.com/tailieudientucntt A0 Address bus A15 CS CS 2K ϫ EPROM 2K ϫ RAM CS PI0 (a) A0 Address bus A15 CS CS 2K ϫ EPROM 2K ϫ RAM CS PI0 (b) Figure 3-57 (a) Full address decoding (b) Partial address decoding CuuDuongThanCong.com https://fb.com/tailieudientucntt ... Figure 3- 13 A 3- to-8 decoder circuit CuuDuongThanCong .com https://fb .com/ tailieudientucntt EXCLUSIVE OR gate A0 B0 A1 B1 A=B A2 B2 A3 B3 Figure 3- 14 A simple 4-bit comparator CuuDuongThanCong .com. .. the upper one for the AND gates and the lower one for the OR gates CuuDuongThanCong .com https://fb .com/ tailieudientucntt D0 D1 D2 D3 D4 D5 D6 D7 S0 S1 S2 S3 S4 S5 S6 S7 C Figure 3- 16 A 1-bit left/right... C (b) Figure 3- 12 (a) An MSI multiplexer (b) The same multiplexer wired to compute the majority function CuuDuongThanCong .com https://fb .com/ tailieudientucntt D0 D1 A B A D2 A D3 B D4 B C D5