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MINISTRY OF EDUCATION AND TRAINING HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY NGUYEN DINH THUAN ROBUSTSIGNALPROCESSINGTECHNIQUESFORMODERNGNSSRECEIVERS Major: Computer Engineering Code No.: 9480106 COMPUTER ENGINEERING DISSERTATION SUPERVISORS: Assoc Prof Ta Hai Tung Prof Letizia Lo Presti Hanoi - 2019 STATEMENT OF ORIGINALITY AND AUTHENTICITY I confirm that my dissertation is an original and authentic piece of work written by myself The data, results in the thesis is reliable and has never been published by others I further confirm that I have fully referenced and acknowledged all material incorporated as secondary resources in accordance with the regulations Hanoi, SUPERVISORS PHD STUDENT PGS.TS Tạ Hải Tùng Nguyễn Đình Thuận Prof Letizia Lo Presti ACKNOWLEDGEMENTS I would like to express my gratitude to Hanoi University of Technology, Graduate School, School of Information and Communication Technology, Department of Computer Engineering and Politecnico di Torino, NavSaS group for creating favorable conditions for me to work and study I would like to express my special thanks to my supervisors, Assoc Ta Hai Tung and Prof Letizia Lo Presti The supervisors have always been helpful, giving great advice, scientific orientations so that I can develop and complete my research Sincerely thank the lecturers, colleagues in the Department of Computer Engineering, School of Information and Communication Technology, Hanoi University of Science and Technology where I work, study and carry out research projects for the enthusiastic in helping and encouraging me during the research With gratitude to teachers, scientists, colleagues and close friends for encouraging and supporting me in the research process Finally, I would like to express my deep gratitude to my family for encouraging me to overcome all obstacles to complete this thesis Nguyen Dinh Thuan TABLE OF CONTENTS STATEMENT OF ORIGINALITY AND AUTHENTICITY ACKNOWLEDGEMENTS TABLE OF CONTENTS LIST OF ACRONYMS LIST OF TABLES LIST OF FIGURES INTRODUCTION 13 FUNDAMENTAL BACKGROUND 18 1.1 GNSS positioning principle 18 1.2 History and development of GNSS 19 1.3 GNSS Threats .20 1.3.1 Multipath .21 1.3.2 Atmosphere 21 1.3.3 Interference 21 1.3.4 Spoofing 21 1.3.5 GNSS Segment errors 21 1.3.6 Cyber Attacks 22 1.4 GNSS Receiver Architecture 22 1.4.1 Signal Conditioning and Sampling 22 1.4.2 Acquisition 23 1.4.3 Tracking and Data Demodulation 23 1.4.4 Positioning Computation 24 1.5 Countermeasures to GNSS Threats 25 1.5.1 Antenna array processingtechniques 25 1.5.2 Frontend and Digital Signal Conditioning based techniques 28 1.5.3 Correlator/Tracking and PVT based techniques 29 1.6 GNSS Simulator and effect of sampling frequency 30 GNSSSIGNAL SIMULATOR DESIGN AND IMPLEMENTATION 32 2.1 Modeling methodology 32 2.2 Overview of the modeling of antenna array signals in GNSSreceivers 32 2.2.1 General model of the received signal in GNSSreceivers 33 2.2.2 Interference 37 2.2.3 Multipath .38 2.2.4 Noise 39 2.3 Effect of sampling frequency on the positioning performance 39 2.3.1 Residual code phase estimation 40 2.3.2 Correlation output calculation .40 2.3.3 Effect of sampling frequency on correlation shape and DLL discriminator function 42 2.3.4 Effect of the sampling frequency and the integration period selection 42 2.3.5 Effect on the presence of Doppler and local oscillator (LO) clock drift 45 2.3.6 Theoretical code tracking loop error estimate 46 2.3.7 Theoretical results evaluation by simulated, and numerical models 49 2.3.8 Effect of Doppler and coherent integration period 50 2.4 Sampling Frequency Effect Mitigation Technique 53 2.4.1 2.5 Receiver implementation .55 Performance verification .57 2.5.1 Verification of the simulated antenna array signals 58 2.5.2 Antenna distortion simulation 64 2.5.3 Verification of multipath simulation 66 2.6 Conclusion 67 ANTENNA ARRAY PROCESSINGS FORGNSSRECEIVERS 69 3.1 The proposed solution for synchronizing separated antenna array element 69 3.1.1 Determining the samples difference 70 3.1.2 Determining the clock phase shift 71 3.2 Implementation a low-cost antenna array 75 3.3 Antenna array frontend verification 76 3.3.1 Phase difference between frontends 76 3.3.2 Carrier to noise ration improvement 77 3.4 Conclusion 78 GNSS SNAPSHOT PROCESSING TECHNIQUE FORGNSSRECEIVERS 80 4.1 Proposed Design of GNSS Snapshot Receiver 80 4.1.1 GNSS Grabber 80 Implementation of GNSS Grabber 80 Firmware Architecture 81 4.2 Server Software 81 4.2.1 GNSSsignal acquisition 81 4.2.2 Combined Doppler and Snapshot Algorithm 84 4.3 Loosely coupled Snapshot GNSS/INS 89 4.4 Tightly coupled Snapshot GNSS/INS 96 4.5 Results 97 4.5.1 Standalone Snapshot GNSS Receiver 97 4.5.2 4.6 Snapshot GNSS/INS Integration 102 Conclusion 104 CONCLUSIONS AND FUTURE WORKS 105 PUBLICATIONS 107 REFERENCES 109 APPENDIX 116 A Correlation output calculation 116 B Error analysis for coherent early minus late DLL 117 LIST OF ACRONYMS Acronym Meaning ADC Analog to Digital Converter AGC Automatic Gain Control AWGN Additive White Gaussian Noise BB BaseBand BOC Binary Offset Carrier BPSK Binary Phase Shift Keying C/A Coarse/Acquisition C/N0 Carrier-to-Noise-Density Ratio CDC Conventional Differential Combination CDMA Code Division Multiple Access CRC Cyclic Redundancy Check CS Commercial Service DLL Delay Lock Loop DFT Discrete Fourier Transform DSP Digital Signal Processor EGNOS European Geostationary Navigation Overlay Service EU European Union FEC Forward Error Correction FFT Fast Fourier Transform FPGA Field Programmable Gate Array FOC Full Operational Capability GLONASS Global Orbiting Navigation Satellite System I Inphase IF Intermediate Frequency Q Quadrature PVT Position Velocity Time SDR Software Defined Radio LIST OF TABLES Table 2.1: GNSS Simulator Features 57 Table 2.2: The coordinate of elements 58 Table 2.3: The direction of visible satellites 59 Table 2.4: The carrier phase relative to the first element of each satellite at the four elements of the array 59 Table 2.5: The simulation scenario 60 Table 2.6: Estimated carrier phase using the post-correlator beamforming tracking loop 62 Table 4.1: Configuration of the GPS grabber 97 Table 4.2: Information of acquired satellites 99 LIST OF FIGURES Figure 1.1: Satellite navigation principle 18 Figure 1.2: Typical GNSS Threats .20 Figure 1.3: Signal conditioning and sampling stage 22 Figure 1.4: Acquisition Architecture 23 Figure 1.5: Tracking Architecture 23 Figure 1.6: Transmission time estimation in GNSSreceivers 24 Figure 1.7: Interference mitigation techniques in GNSSreceivers 25 Figure 1.8: The traditional low-cost architecture of antenna array forGNSS applications 27 Figure 1.9: The correlation between GPS signal grabbed by antenna array 28 Figure 1.10: Spectrum and histogram of GNSSsignal in the absence of interference 28 Figure 1.11: Snapshot positioning architecture 29 Figure 2.1: Geometry of antenna array 33 Figure 2.2: The model of the received signalfor a single antenna 33 Figure 2.3: GPS multi-antenna frontend 34 Figure 2.4: Flowchart of the simulator 35 Figure 2.5: Bandlimited Gaussian interference model 38 Figure 2.6: Multipath model 38 Figure 2.7: Effect of sampling frequency on the positioning performance .39 Figure 2.8: Residual code phases versus the number of samples per code chip with 4f c < fs < 5fc 40 Figure 2.9: Normalised correlator and EML discriminator functions for different sampling frequencies Results are obtained by correlating the incoming signal with various local -2 generated replica signals that have the time delay from−T c to Tc with step = 10 Tc 42 Figure 2.10: Correlation shapes for ms integration with various sampling frequencies 43 Figure 2.11: Ambiguous synchronization between a local PRN code and two different incoming analog signals of the same PRN sequence, but with slightly differing code phase offset .43 Figure 2.12: Correlation shapes and their errors with respect to the ideal correlation at a sampling frequency fs =16.3676 MHz using various coherent integration periods 44 Figure 2.13: Representation of code tracking loop [54] 46 Frequency on GNSS Code Tracking." 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frequency domain as: −1 () −2 (A.2) − ( +1) {} () =∑ ( ) =0 and its reverse Fourier transform is: −1 ⁄2 −1 (A.3) ∑ =0 ∑ [ − − ] =∫ ( ) =0 − /2 where βr is the receiver front-end bandwidth (A.4) Replacing (A.4) to (6), it yields to: (A.5) 116 −1 −1 −1 ⁄2 [ − − ( ) = ∑ ∑ ∑ −⌊ + () ⌋ () ]∫ {} =0 − /2 =0 =0 ⁄2 −1 −1 −1 = ∫ ∑ ()∑ [ − − ∑ −⌊ + () ⌋ ] {} =0 − =0 =0 ⁄2 −1 −1 0 ( {} ) ∫ ≅ ∑ ) ( ( − /2 ( +⌊ + () ⌋ −2 ) ∑ {} ) =0 ⁄2 =0 −1 | (⌊ + () ⌋ ) | {} ( ) −1 = ∫ ∑ ( ) ( (( )+⌊ + − () ⌋ ) ) +∑ { } {} − /2 =0 =0, ≠ ( −1 sin( = ∑ ∫ ) ( ) sin( =0 ) ⁄2 (⌊ + () ⌋ ) ) − /2 for a pseudorandom noise code sequence Ck, k=0, 1, 2, , N, all misaligned chips with k = l have equal probability of having +1 or −1 values Their product sum approaches zero B Error analysis for coherent early minus late DLL Define an error signal at the output of the real-part operator in the coherent early minus late TOA estimator as ( ) = ℜ{ ( − Δ/2) − ( + Δ/2) −1 −1 −1 + ∑ ()(∑ √ ∑ [ − −− ⌊ − Δ/2 + () ⌋ (B.1 ) ] {} =0 =0 =0 −1−1 {} −∑ =0 [ − −− ⌊ + Δ/2 +( ) ⌋ ∑ ])} =0 where ε = t0 −ts is the code phase misalignment, to is the mean value of the un-smoothed TOA estimate (tu), ts is the smoothed TOA estimate, and ∆ is the Early - Late code space (0